TSDxx Unidirectional TVS Diodes in SOD-323 datasheet (Rev. C)
Document overview
- Manufacturer or author: Texas Instruments, Incorporated [SLVSH43,C]
- PDF pages: 21
Technical content
TSDxx Unidirectional TVS Diodes in SOD-323
1 Features
- IEC 61000-4-2 ESD protection: – ±30kV contact discharge – ±30kV air gap discharge
- IEC 61000-4-5 surge protection: – 7-60A (8/20µs)
- IO capacitance < 20pF (typical)
- Ultra low leakage current: 50nA (maximum)
- Industrial temperature range: –55°C to +150°C
- Industry standard SOD-323 leaded package (2.65mm × 1.3mm)
2 Applications
- I/O Protection
- Power Line Protection
- USB VBUS
- Grid infrastructure
- Portable electronics
3 Description
The TSDxx are a family of unidirectional TVS protection diodes designed for clamping harmful transients such as ESD and surge. The TSDxx devices are rated to dissipate ESD strikes up to ±30kV (contact and air gap discharge) and also meets the maximum level specified in the IEC 61000-4-2 international standard (Level 4). Combining the robust clamping performance and low capacitance of this device, TSDxx are excellent TVS diodes to protect both data and power lines in many different applications. The TSDxx family is offered in the industry standard, leaded SOD-323 package to enable easy solderability.
Package Information
PART NUMBER PACKAGE (1) PACKAGE SIZE (2) TSDxx DYF (SOD-323, 2) 2.65mm × 1.3mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) The package size (length × width) is a nominal value and includes pins, where applicable. Functional Block Diagram TSD03, TSD05, TSD12, TSD15, TSD18, TSD24, TSD36 SLVSH43C – JULY 2023 – REVISED MAY 2025 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
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4 Pin Configuration and Functions
Figure 4-1. DYF Package, 2-Pin SOD-323 (Top View) Table 4-1. Pin Functions PIN TYPE(1) DESCRIPTION NO. NAME
1 IO I/O Protected Channel
2 GND GND Ground. Connect to ground. (1) I = input, O = output. GND = ground www.ti.com TSD03, TSD05, TSD12, TSD15, TSD18, TSD24, TSD36 SLVSH43C – JULY 2023 – REVISED MAY 2025 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TSD03 TSD05 TSD12 TSD15 TSD18 TSD24 TSD36
5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) Parameter DEVICE MIN MAX UNIT PPP IEC 61000-4-5 power (tp – 8/20µs) at 25°C TSD03 170 W TSD05 529 W TSD12 300 W TSD15 300 W TSD18 300 W TSD24 250 W TSD36 300 W IPP IEC 61000-4-5 current (tp – 8/20µs) at 25°C TSD03 25 A TSD05 60 A TSD12 18 A TSD15 15 A TSD18 15 A TSD24 9 A TSD36 7 A TA Ambient Operating Temperature -55 150 °C Tstg Storage Temperature -65 155 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality, performance, and shorten the device lifetime.
5.2 ESD Ratings - JEDEC Specification
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2500 V Charged device model (CDM), per JEDEC specification JS-002 (2) ±1000 V (1) JEDEC document JEP155 states that 500V HBM allows safe manufactuuring with a standard ESD control proccess (2) JEDEC document JEP157 states that 250V CDM allows safe manufactuuring with a standard ESD control proccess.
5.3 ESD Ratings - IEC Specification
V(ESD) Electrostatic discharge IEC 61000-4-2 contact discharge ±30000 V IEC 61000-4-2 air-gap discharge ±30000
5.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT TA Operating free-air temperature -55 150 °C TSD03, TSD05, TSD12, TSD15, TSD18, TSD24, TSD36 SLVSH43C – JULY 2023 – REVISED MAY 2025 www.ti.com
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5.5 Thermal Information
THERMAL METRIC (1) TSD03 TSD05 TSD12 / TSD15 / TSD18 / TSD24 / TSD36 UNITDYF (SOD-323) DYF (SOD-323) DYF (SOD-323)
2 PINS 2 PINS 2 PINS
RθJA Junction-to-ambient thermal resistance 739.2 672.0 693.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 287.7 230.5 254.7 °C/W RθJB Junction-to-board thermal resistance 605.5 541.4 566.6 °C/W ΨJT Junction-to-top characterization parameter 118.4 64.4 78.6 °C/W ΨJB Junction-to-board characterization parameter 591.1 527.5 552.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
5.6 Electrical Characteristics - TSD03
At TA = 25°C unless otherwise noted (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VRWM Reverse stand-off voltage IIO < 50nA, across operating temperature range 3.6 V VBR Breakdown voltage IIO = 1mA, IO to GND 4.5 V ILEAK Reverse leakage current VIO = 3.6V, IO to GND 5 50 nA VFWD Forward voltage IIO = 1mA, GND to IO 0.8 V VCLAMP Surge clamping voltage, tp = 8/20µs (2) IPP = 12A, IO to GND 6.3 V IPP = 25A, IO to GND 7.7 V IPP = 12A, GND to IO 3 V IPP = 25A, GND to IO 4.9 V TLP clamping voltage, tp = 100ns IPP = 16A, IO to GND 6.5 V IPP = 16A, GND to IO 3.4 V CL Line capacitance VIO = 0V, Vp-p = 30mV, f = 1MHz, IO to GND 4.5 pF (1) Typical parameters are measured at 25°C (2) Nonrepetitive current pulse 8 to 20μs exponentially decaying waveform according to IEC 61000-4-5 www.ti.com TSD03, TSD05, TSD12, TSD15, TSD18, TSD24, TSD36 SLVSH43C – JULY 2023 – REVISED MAY 2025 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TSD03 TSD05 TSD12 TSD15 TSD18 TSD24 TSD36
5.7 Electrical Characteristics - TSD05
At TA=25℃ (unless otherwise noted) (1) PARAMETER TEST CONDITION MIN TYP MAX UNIT VRWM Reverse stand-off voltage IIO <50nA, across operating temperature range 5.5 V VBR Breakdown voltage IIO = 1mA, IO to GND 6 V ILEAK Reverse leakage current VIO = 5.5V, IO to GND 5 50 nA VFWD Forward voltage IIO = 1mA, GND to IO 0.7 V VCLAMP Surge clamping voltage, tp = 8/20µs (2) IPP = 24A, IO to GND 8 11.5 V IPP = 60A, IO to GND 9 15 V IPP = 60A, GND to IO 5.5 V TLP clamping voltage, tp = 100ns IPP = 16A, IO to GND 7.5 V IPP =16A, GND to IO 2.5 V CL Line capacitance VIO = 0V; ƒ = 1MHz, IO to GND 19 pF (1) Typical parameters are measured at 25°C (2) Nonrepetitive current pulse 8 to 20µs exponentially decaying waveform according to IEC 61000-4-5
5.8 Electrical Characteristics - TSD12
At TA=25℃ (unless otherwise noted) (1) PARAMETER TEST CONDITION MIN TYP MAX UNIT VRWM Reverse stand-off voltage IIO <50nA, across operating temperature range 12 V VBR Breakdown voltage IIO = 10mA, IO to GND 12.7 V ILEAK Reverse leakage current VIO = 12V, IO to GND 2 20 nA VFWD Forward voltage IIO = 1mA, GND to IO 0.7 V VCLAMP Surge clamping voltage, tp = 8/20µs (2) IPP = 1A, IO to GND 18 V IPP = 5A, IO to GND 19 V IPP = 18A, IO to GND 23 V IPP = 18A, GND to IO 8 V TLP clamping voltage, tp = 100ns IPP = 16A, IO to GND 17 V IPP =16A, GND to IO 3 V CL Line capacitance VIO = 0V; ƒ = 1MHz, IO to GND 12 pF (1) Typical parameters are measured at 25°C (2) Nonrepetitive current pulse 8 to 20µs exponentially decaying waveform according to IEC 61000-4-5 TSD03, TSD05, TSD12, TSD15, TSD18, TSD24, TSD36 SLVSH43C – JULY 2023 – REVISED MAY 2025 www.ti.com
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5.9 Electrical Characteristics - TSD15
At TA=25℃ (unless otherwise noted) (1) PARAMETER TEST CONDITION MIN TYP MAX UNIT VRWM Reverse stand-off voltage IIO <50nA, across operating temperature range 15 V VBR Breakdown voltage IIO = 10mA, IO to GND 18.3 V ILEAK Reverse leakage current VIO = 15V, IO to GND 2 20 nA VFWD Forward voltage IIO = 10mA, GND to IO 0.7 V VCLAMP Surge clamping voltage, tp = 8/20µs (2) IPP = 1A, IO to GND 25 V IPP = 5A, IO to GND 26 V IPP = 15A, IO to GND 31 V IPP = 15A, GND to IO 7 V TLP clamping voltage, tp = 100ns IPP = 16A, IO to GND 23 V IPP =16A, GND to IO 3 V CL Line capacitance VIO = 0V; ƒ = 1MHz, IO to GND 12 pF (1) Typical parameters are measured at 25°C (2) Nonrepetitive current pulse 8 to 20µs exponentially decaying waveform according to IEC 61000-4-5
5.10 Electrical Characteristics - TSD18
At TA=25℃ (unless otherwise noted) (1) PARAMETER TEST CONDITION MIN TYP MAX UNIT VRWM Reverse stand-off voltage IIO <50nA, across operating temperature range 18 V VBR Breakdown voltage IIO = 10mA, IO to GND 18.5 V ILEAK Reverse leakage current VIO = 18V, IO to GND 2 20 nA VFWD Forward voltage IIO = 10mA, GND to IO 0.7 V VCLAMP Surge clamping voltage, tp = 8/20µs (2) IPP = 1A, IO to GND 25 V IPP = 5A, IO to GND 26 V IPP = 15A, IO to GND 31 V IPP = 15A, GND to IO 7 V TLP clamping voltage, tp = 100ns IPP = 16A, IO to GND 23 V IPP =16A, GND to IO 3 V CL Line capacitance VIO = 0V; ƒ = 1MHz, IO to GND 12 pF (1) Typical parameters are measured at 25°C (2) Nonrepetitive current pulse 8 to 20µs exponentially decaying waveform according to IEC 61000-4-5 www.ti.com TSD03, TSD05, TSD12, TSD15, TSD18, TSD24, TSD36 SLVSH43C – JULY 2023 – REVISED MAY 2025 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TSD03 TSD05 TSD12 TSD15 TSD18 TSD24 TSD36
5.11 Electrical Characteristics - TSD24
At TA=25℃ (unless otherwise noted) (1) PARAMETER TEST CONDITION MIN TYP MAX UNIT VRWM Reverse stand-off voltage IIO <50nA, across operating temperature range 24 V VBR Breakdown voltage IIO = 10mA, IO to GND 24.8 V ILEAK Reverse leakage current VIO = 24V, IO to GND 2 20 nA VFWD Forward voltage IIO = 10mA, GND to IO 0.7 V VCLAMP Surge clamping voltage, tp = 8/20µs (2) IPP = 1A, IO to GND 32 V IPP = 5A, IO to GND 36 V IPP = 9A, IO to GND 39 V IPP = 9A, GND to IO 4 V TLP clamping voltage, tp = 100ns IPP = 16A, IO to GND 33 V IPP =16A, GND to IO 3 V CL Line capacitance VIO = 0V; ƒ = 1MHz, IO to GND 12 pF (1) Typical parameters are measured at 25°C (2) Nonrepetitive current pulse 8 to 20µs exponentially decaying waveform according to IEC 61000-4-5
5.12 Electrical Characteristics - TSD36
At TA=25℃ (unless otherwise noted) (1) PARAMETER TEST CONDITION MIN TYP MAX UNIT VRWM Reverse stand-off voltage IIO <50nA, across operating temperature range 36 V VBR Breakdown voltage IIO = 10mA, IO to GND 37.1 V ILEAK Reverse leakage current VIO = 36V, IO to GND 2 20 nA VFWD Forward voltage IIO = 10mA, GND to IO 0.7 V VCLAMP Surge clamping voltage, tp = 8/20µs (2) IPP = 1A, IO to GND 44 V IPP = 5A, IO to GND 59 V IPP = 7A, IO to GND 67 V IPP = 7A, GND to IO 4 V TLP clamping voltage, tp = 100ns IPP = 16A, IO to GND 53 V IPP =16A, GND to IO 3 V CL Line capacitance VIO = 0V; ƒ = 1MHz, IO to GND 12 pF (1) Typical parameters are measured at 25°C (2) Nonrepetitive current pulse 8 to 20µs exponentially decaying waveform according to IEC 61000-4-5 TSD03, TSD05, TSD12, TSD15, TSD18, TSD24, TSD36 SLVSH43C – JULY 2023 – REVISED MAY 2025 www.ti.com
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5.13 Typical Characteristics
V o l t a g e ( V ) Current (A) 0 1 2 3 4 5 6 7 8 9 - 4 1 2 1 6 2 0 2 4 2 8 3 2 Figure 5-1. Positive TLP Curve - TSD03 Figure 5-2. Positive TLP Curve - TSD05 Voltage (V) Current (A) 0 0.5 1 1.5 2 2.5 3 3.5 4 Figure 5-3. Negative TLP Curve - TSD05 Figure 5-4. Positive TLP Curve - TSD12 V o l t a g e ( V ) Current (A) 0 4 8 1 2 1 6 2 0 2 4 2 8 - 4 1 2 1 6 2 0 2 4 2 8 3 2 Figure 5-5. Positive TLP Curve - TSD15 V o l t a g e ( V ) Current (A) 0 4 8 1 2 1 6 2 0 2 4 2 8 - 4 1 2 1 6 2 0 2 4 2 8 3 2 Figure 5-6. Positive TLP Curve - TSD18 www.ti.com TSD03, TSD05, TSD12, TSD15, TSD18, TSD24, TSD36 SLVSH43C – JULY 2023 – REVISED MAY 2025 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TSD03 TSD05 TSD12 TSD15 TSD18 TSD24 TSD36
5.13 Typical Characteristics (continued)
V o l t a g e ( V ) Cuurent (A) 0 5 1 0 1 5 2 0 2 5 3 0 3 5 - 4 1 2 1 6 2 0 2 4 2 8 3 2 Figure 5-7. Positive TLP Curve - TSD24 V o l t a g e ( V ) Current (A) 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 6 0 - 4 1 2 1 6 2 0 2 4 2 8 3 2 Figure 5-8. Positive TLP Curve - TSD36 B i a s V o l t a g e ( V ) Capacitance (pF) 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 1 0 1 2 1 4 1 6 1 8 2 0 T S D 0 3 T S D 0 5 T S D 1 2 T S D 1 5 / 1 8 T S D 2 4 T S D 3 6 Figure 5-9. Capacitance vs Bias Voltage T e m p e r a t u r e ( C ) Leakage Current (nA) - 7 5 - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 T S D 0 3 T S D 0 5 T S D 1 2 T S D 1 5 / 1 8 T S D 2 4 T S D 3 6 Figure 5-10. Leakage Current vs Temperature Temperature (C) Capacitance (pF) -75 -45 -15 15 45 75 105 135 14.8 15.6 16.4 17.2 18.8 19.6 20.4 21.2 Figure 5-11. Temperature vs Capacitance - TSD05 TSD03, TSD05, TSD12, TSD15, TSD18, TSD24, TSD36 SLVSH43C – JULY 2023 – REVISED MAY 2025 www.ti.com
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6 Application and Implementation
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.
6.1 Application Information
The TSDxx family are TVS diodes that provide a path to ground for dissipating transient voltage spikes (such as ESD or surge) on signal lines and power lines. Connect the device in parallel to the down stream circuitry for protection. As the current from the transient passes through the TVS, only a small voltage drop is present across the diode. The small voltage drop is presented to the protected IC. The low R DYN of the triggered TVS holds this voltage (VCLAMP) to a safe level for the protected IC. For more information on how to properly use this device, refer to the ESD Packaging and Layout Guide.
7 Device and Documentation Support
7.1 Documentation Support
7.1.1 Related Documentation
For related documentation, see the following:
- Texas Instruments, ESD Layout Guide application reports
- Texas Instruments, Generic ESD Evaluation Module user's guide
- Texas Instruments, Reading and Understanding an ESD Protection data sheet
7.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
7.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
7.4 Trademarks
TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.
7.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
7.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions. www.ti.com TSD03, TSD05, TSD12, TSD15, TSD18, TSD24, TSD36 SLVSH43C – JULY 2023 – REVISED MAY 2025 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TSD03 TSD05 TSD12 TSD15 TSD18 TSD24 TSD36
8 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (March 2025) to Revision C (May 2025) Page Changes from Revision A (January 2025) to Revision B (March 2025) Page Changes from Revision * (July 2023) to Revision A (January 2025) Page DATE REVISION NOTES July 2023 * Initial Release TSD03, TSD05, TSD12, TSD15, TSD18, TSD24, TSD36 SLVSH43C – JULY 2023 – REVISED MAY 2025 www.ti.com
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9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TSD03, TSD05, TSD12, TSD15, TSD18, TSD24, TSD36 SLVSH43C – JULY 2023 – REVISED MAY 2025 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TSD03 TSD05 TSD12 TSD15 TSD18 TSD24 TSD36
9.1 Mechanical Data
www.ti.com PACKAGE OUTLINE 0.15
0.08 TYP
0.2 2.75 2.55
1 MAX
0.1
0.0 TYP
2X 0.35 0.25 1.8 1.6 1.4 1.2 0.40
0.25 TYP
(0.475) (0.85) SOT(SOD-323) - 1 mm max heightDYF0002A SMALL OUTLINE TRANSISTOR 4228484/A 02/2022 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 1 (-) 2 (+) PIN 1 ID GAGE PLANE SCALE 6.000 TSD03, TSD05, TSD12, TSD15, TSD18, TSD24, TSD36 SLVSH43C – JULY 2023 – REVISED MAY 2025 www.ti.com
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www.ti.com EXAMPLE BOARD LAYOUT
0.07 MAX
0.07 MIN
2X (0.9) 2X (0.5) (2.6) (R0.05) TYP 4228484/A 02/2022 SOT(SOD-323) - 1 mm max heightDYF0002A SMALL OUTLINE TRANSISTOR NOTES: (continued) 3. Publication IPC-7351 may have alternate designs. 4. Solder mask tolerances between and around signal pads can vary based on board fabrication site. PKG LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:25X PKG 1 2 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL www.ti.com TSD03, TSD05, TSD12, TSD15, TSD18, TSD24, TSD36 SLVSH43C – JULY 2023 – REVISED MAY 2025 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TSD03 TSD05 TSD12 TSD15 TSD18 TSD24 TSD36
www.ti.com EXAMPLE STENCIL DESIGN (2.6) 2X (0.9) 2X (0.5) (R0.05) TYP SOT(SOD-323) - 1 mm max heightDYF0002A SMALL OUTLINE TRANSISTOR 4228484/A 02/2022 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 6. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:25X PKG PKG 1 2 TSD03, TSD05, TSD12, TSD15, TSD18, TSD24, TSD36 SLVSH43C – JULY 2023 – REVISED MAY 2025 www.ti.com
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www.ti.com 7-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TSD03DYFR Active Production SOT (DYF) | 2 3000 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 125 3N5F TSD03DYFR.B Active Production SOT (DYF) | 2 3000 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 125 3N5F TSD05DYFR Active Production SOT (DYF) | 2 3000 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 125 33MF TSD05DYFR.B Active Production SOT (DYF) | 2 3000 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 125 33MF TSD12DYFR Active Production SOT (DYF) | 2 3000 | LARGE T&R Yes SN Level-3-260C-168 HR -55 to 150 3JIF TSD15DYFR Active Production SOT (DYF) | 2 3000 | LARGE T&R Yes SN Level-3-260C-168 HR -55 to 150 3MOF TSD18DYFR Active Production SOT (DYF) | 2 3000 | LARGE T&R Yes SN Level-3-260C-168 HR -55 to 150 3JLF TSD24DYFR Active Production SOT (DYF) | 2 3000 | LARGE T&R Yes SN Level-3-260C-168 HR -55 to 150 3H2F TSD36DYFR Active Production SOT (DYF) | 2 3000 | LARGE T&R Yes SN Level-3-260C-168 HR -55 to 150 3GJF (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative Addendum-Page 1
www.ti.com 7-Nov-2025 and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TSD12, TSD15, TSD18, TSD24, TSD36 :
- Automotive : TSD12-Q1 , TSD15-Q1 , TSD18-Q1 , TSD24-Q1 , TSD36-Q1 NOTE: Qualified Version Definitions:
- Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 1-May-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 1-May-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TSD03DYFR SOT DYF 2 3000 210.0 200.0 42.0 TSD05DYFR SOT DYF 2 3000 210.0 200.0 42.0 TSD12DYFR SOT DYF 2 3000 210.0 200.0 42.0 TSD15DYFR SOT DYF 2 3000 210.0 200.0 42.0 TSD18DYFR SOT DYF 2 3000 210.0 200.0 42.0 TSD24DYFR SOT DYF 2 3000 210.0 200.0 42.0 TSD36DYFR SOT DYF 2 3000 210.0 200.0 42.0 Pack Materials-Page 2
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