Logic IC

TSB81BA3EIPFP

Texas Instruments

IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER

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www.ti.com SLLS783A –MAY 2009–REVISED MAY 2010 IEEE1394bTHREE-PORTCABLETRANSCEIVER/ARBITER Check forSamples: TSB81BA3E 1FEATURES

FullySupports ProvisionsofIEEE P1394b • InterfacetoLink-LayerControllerSupports Revision1.33+at1-GigabitSignalingRates Low Cost TIBus-HolderIsolation
FullySupports ProvisionsofIEEE 1394a-2000 • InteroperableWith Link-LayerControllers and 1394-1995Standard forHigh Performance Using 3.3-VSupplies SerialBus • InteroperableWith Other 1394 PhysicalLayers
FullyInteroperableWith Firewire,i.LINK,and (PHYs) Using 1.8-V,3.3-V,and 5-V Supplies SB1394 ™ ,ImplementationofIEEE Std 1394 • Low Jitter,ExternalCrystalOscillatorProvides
ProvidesThree FullyBackward Compatible, Transmitand Receive Data at100/200/400/800 (1394a-2000FullyCompliant)BilingualP1394b Mbits/s,and Link-LayerControllerClock at Cable Portsatup to800 Megabits per Second 49.152MHz and 98.304MHz (Mbits/s) • SeparateBias (TPBIAS) forEach Port
ProvidesThree 1394a-2000FullyCompliant • Low Cost,High Performance 80-PinTQFP Cable Portsat100/200/400Mbits/s (PFP)ThermallyEnhanced Package and
Full1394a-2000Support Includes: 168-PinZAJ (BGA) Package – Connection Debounce • SoftwareDevice Reset (SWR) – ArbitratedShortReset • Fail-SafeCircuitrySenses Sudden Loss of Power totheDevice and DisablesthePortsto– MultispeedConcatenation Ensure That theTSB81BA3E Does Not Load– ArbitrationAcceleration theTPBIAS ofAny Connected Device and– Fly-ByConcatenation Blocks any Leakage From thePortBack to – PortDisable/Suspend/Resume Power Plane – Extended Resume Signalingfor • The TSB81BA3E Has a 1394a-2000Compliant CompatibilityWith Legacy DV Devices Common-Mode Noise Filteron theIncoming
Power-Down FeaturestoConserve Energy in Bias DetectCircuittoFilterOut Cross-Talk BatteryPowered Applications Noise
Low-Power Sleep Mode • The TSB81BA3E IsPortProgrammable to Force 1394a Mode toAllow Use of1394a• FullyCompliant With Open Host Controller Connectors (1394bSignalingMust Not Be PutInterface(HCI)Requirements Across 1394a Connectors or Cables)• Cable Power Presence Monitoring
InternalVoltageRegulatorOption• Cable PortsMonitorLineConditionsforActive Connection toRemote Node
RegisterBitsGive SoftwareControlof Contender Bit,Power Class Bits,LinkActive ControlBit,and 1394a-2000Features
Data InterfacetoLink-LayerControllerPin SelectableFrom 1394a-2000Mode (2/4/8 ParallelBitsat49.152MHz) or 1394b Mode (8ParallelBitsat98.304MHz) Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2009–2010,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SLLS783A –MAY 2009–REVISED MAY 2010 www.ti.com

DESCRIPTION

The TSB81BA3E providesthedigitaland analogtransceiverfunctionsneeded toimplementa three-portnode in a cable-basedIEEE 1394 network.Each cable port incorporatestwo differentiallinetransceivers.The transceiversincludecircuitryto monitorthe lineconditionsas needed fordeterminingconnectionstatus,for initializationand arbitration,and forpacketreceptionand transmission.The TSB81BA3E isdesignedtointerface witha link-layercontroller(LLC),such as the TSB82AA2, TSB12LV21, TSB12LV26, TSB12LV32, TSB42AA4, TSB42AB4, TSB12LV01B, or TSB12LV01C. Italsomay be connectedcableporttocableporttoan integrated 1394 Link+ PHY layersuch as theTSB43AB2. The TSB81BA3E can be powered by a single3.3-Vsupplywhen theVREG_PD terminal(terminal73 on thePFP package and terminalB7 on theZAJ package)istiedtoGND. VREG_PD enablestheinternal3.3-Vto1.95-V regulatorwhich providesthe1.95-Vtothecore.The When VREG_PD ispulledhightoVDD throughatleasta 1-kΩ resistortheTSB81BA3E internalregulatorisoffand thedevicecan be powered by two separateexternal regulatedsupplies:3.3-VfortheI/Osand 1.95-Vforthecore.The corevoltageissuppliedtothePLLVDD-CORE and DVDD-CORE terminalstotherequirementsintherecommended operatingconditions(1.95-Vnominal).The PLLVDD-CORE terminalsmust be separatedfrom the DVDD-CORE terminals.The PLLVDD-CORE and the DVDD-CORE terminalsmust be decoupledwith1 uF capacitorsto stabilzethe respectivesupply.Additional 0.10uFand 0.01uFhigh-frequencybypass capacitorsmay alsobe used.The separationbetween DVDD-CORE and PLLVDD-CORE may be implementedby separatepower supplyrails,orby a singlepower supplyrail,where theDVDD-CORE and PLLVDD-CORE areseparatedby a filternetworktokeep noisefromthePLLVDD-CORE supply. The TSB81BA3E requiresan external98.304-MHz crystaloscillatortogeneratea referenceclock.The external clockdrivesan internalphase-lockedloop(PLL),which generatestherequiredreferencesignal.Thisreference signalprovidestheclocksignalsthatcontroltransmissionoftheoutboundencoded information.A 49.152-MHz clock signalis suppliedto the associatedLLC for synchronizationof the two devices and is used for resynchronizationof the receiveddata when operatingthe PHY-linkinterfacein compliancewiththe IEEE 1394a-2000 standard.A 98.304-MHz clocksignalissuppliedtotheassociatedLLC forsynchronizationofthe two deviceswhen operatingthe PHY-linkinterfaceincompliancewiththe IEEE P1394b standard.The power down (PD)function,when enabledby assertingthePD terminalhigh,stopsoperationofthePLL. Data bitstobe transmittedthroughthecableportsarereceivedfromtheLLC on two-,four-,oreight-bitparallel paths(dependingon the requestedtransmissionspeed and PHY-linkinterfacemode of operation).They are Mbits/s(referredto as S100, S200, S400, S400B, or S800 speed,respectively)as the outbound information stream. The PHY-linkinterfacecan followeithertheIEEE 1394a-2000protocolortheIEEE 1394b-2002protocol.When usinga 1394a-2000 LLC such as the TSB12LV26, the BMODE terminalmust be deasserted.The PHY-link interfacethenoperatesinaccordancewiththelegacy1394a-2000standard.When usinga 1394b LLC such as the TSB82AA2, the BMODE terminalmust be asserted.The PHY-linkinterfacethen conformsto the P1394b standard. The cableinterfacecan followeithertheIEEE 1394a-2000protocolorthe1394b protocolon allports.The mode ofoperationisdeterminedby theinterfacecapabilitiesoftheportsbeingconnected.When any ofthethreeports isconnectedto a 1394a-2000 compliantdevice,the cableinterfaceon thatportoperatesinthe 1394a-2000 data-strobemode ata compatibleS100, S200, or S400 speed.When a bilingualportisconnectedtoa 1394b compliantnode,thecableinterfaceon thatportoperatespertheP1394b standardatS400B orS800 speed.The TSB81BA3E automaticallydeterminesthecorrectcableinterfaceconnectionmethod forthebilingualports. NOTE The BMODE terminaldoes notselectthecableinterfacemode ofoperation.The BMODE terminalselectsthe PHY-linkinterfacemode of operationand affectsthe arbitration modes on the cable.When the BMODE terminalis deasserted,BOSS arbitrationis disabled. Duringpacketreceptiontheserialdatabitsaresplitintotwo-,four-,oreight-bitparallelstreams(dependingupon theindicatedreceivespeed and thePHY-linkinterfacemode ofoperation),resynchronizedtothelocalsystem clockand senttotheassociatedLLC. The receiveddataisalsotransmitted(repeated)on theotherconnected and activecableports.

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www.ti.com SLLS783A –MAY 2009–REVISED MAY 2010 Duringpacketreceptiontheserialdatabitsaresplitintotwo-,four-,oreight-bitparallelstreams(dependingupon theindicatedreceivespeed and thePHY-linkinterfacemode ofoperation),resynchronizedtothelocalsystem clockand senttotheassociatedLLC. The receiveddataisalsotransmitted(repeated)on theotherconnected and activecableports. Both thetwistedpairA (TPA) and thetwistedpairB (TPB) cableinterfacesincorporatedifferentialcomparators tomonitorthelinestatesduringinitializationand arbitrationwhen connectedtoa 1394a-2000compliantdevice. The outputsof thesecomparatorsare used by the internallogicto determinethe arbitrationstatus.The TPA channelmonitorstheincomingcablecommon-mode voltage.The valueofthiscommon-mode voltageisused during1394a-mode arbitrationand setsthespeed ofthenextpackettransmission.Inaddition,theTPB channel monitorstheincomingcablecommon-mode voltageon theTPB pairforthepresenceoftheremotelysupplied twistedpairbias(TPBIAS)voltage. When connectedtoa 1394a-2000 compliantnode,theTSB81BA3E providesa 1.86-Vnominalbiasvoltageat the TPBIAS terminalforporttermination.The PHY containsthreeindependentTPBIAS circuits(one foreach port).Thisbiasvoltage,when seen througha cableby a remote receiver,indicatesthepresenceofan active connection.Thisbiasvoltagesourcemust be stabilizedby an externalfiltercapacitorof1 mF. The linedriversinthe TSB81BA3E are designedto work withexternal112-Ω terminationresistornetworksto match the110-Ω cableimpedance.One terminationnetworkisrequiredateach end ofa twisted-paircable.Each networkiscomposed ofa pairofseries-connected~56-Ω resistors.The midpointofthepairofresistorsthatare connectedtotheTPA terminalsisconnectedtoitscorrespondingTPBIAS voltageterminal.The midpointofthe pairof resistorsthatare directlyconnectedto the TPB terminalsiscoupledto ground througha parallelRC networkwithrecommended valuesof5 kΩ and 270 pF.The valuesoftheexternalline-terminationresistorsare designedto meet the standardspecificationswhen connectedinparallelwiththe internalreceivercircuits.A precisionexternalresistorconnectedbetween theR0 and R1 terminalssetsthedriveroutputcurrent,alongwith otherinternaloperatingcurrents. When thepower supplyoftheTSB81BA3E isoffwhilethetwisted-paircablesare connected,theTSB81BA3E transmitterand receivercircuitrypresenta high-impedancesignaltothecablethatdoes notloadthedeviceat theotherend ofthecable. When the TSB81BA3E isused withoutone or more of the portsbroughtout to a connector,the twisted-pair terminalsoftheunused portsmust be terminatedforreliableoperation.For each unused port,theportmust be forcedtothe1394a-onlymode (Data-Strobe-onlymode),thentheTPB+ and TPB – terminalscan be tiedtogether and then pulledto ground;or the TPB+ and TPB – terminalscan be connected to the suggested normal terminationnetwork.The TPA+ and TPA – terminalsof an unused portcan be leftunconnected.The TPBIAS terminalcan be connectedtoa 1-mF capacitortogroundorleftunconnected. To operatea portas a 1394b bilingualport,theforcedata-strobe-onlyterminalfortheport(DS0,DS1, orDS2) needs tobe pulledtoground througha 1-kΩ resistor.The portmust be operatedinthe1394b bilingualmode whenever a 1394b bilingualor a 1394b beta-onlyconnectorisconnectedtotheport.To operatetheportas a 1394a-onlyport,theforcedata-strobe-onlyterminal(DS0,DS1, orDS2) needs tobe pulledto3.3V VCC through a 1-kΩ resistor.The onlytimetheportmust be forcedtothedata-strobe-onlymode isiftheportisconnectedto a 1394a connector(either6 pin,which isrecommended, or 4 pin).Thismode isprovidedtoensurethat1394b Signalingisneversentacrossa 1394a cable. The TESTM, VREG_PD, SE, and SM terminalsare used to setup variousmanufacturingtestconditions.For normaloperation,theTESTM and VREG_PD terminalsmust be connectedtoVDD througha 1-kΩ resistor.The SE and SM terminalsmust be tiedtogroundthrougha 1-kΩ resistor. Three package terminalsare used as inputsto setthe defaultvalueforthreeconfigurationstatusbitsinthe self-IDpacket.They may be pulledhighthrougha 1-kΩ resistororhardwiredlow as a functionoftheequipment design.The PC0, PC1, and PC2 terminalsindicatethe defaultpower classstatusforthe node (theneed for power from the cableor the abilityto supplypower to the cable).The contenderbitinthe PHY registerset indicatesthatthenode isa contendereitherfortheisochronousresourcemanager (IRM)orforthebus manager (BM).On theTSB81BA3E, thisbitmay onlybe setby a writetothePHY registerset.Ifa node desirestobe a contenderforIRM orBM, thenthenode softwaremust setthisbitinthePHY registerset. Copyright© 2009–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):TSB81BA3E

SLLS783A –MAY 2009–REVISED MAY 2010 www.ti.com The LPS (linkpower status)terminalworkswiththeLKON/DS2 terminaltomanage thepower usage inthenode. The LPS signalfrom theLLC isused withtheLCtrlbit(seeTable1 and Table2 intheApplicationInformation section)toindicatetheactive/powerstatusoftheLLC. The LPS signalalsoresets,disables,and initializesthe PHY-LLC interface(thestateofthePHY-LCC interfaceiscontrolledsolelyby theLPS inputregardlessofthe stateoftheLCtrlbit). The LPS inputisconsideredinactiveifitremainslow formore thantheLPS_RESET time(seetheLPS terminal definition)and isconsideredactiveotherwise.When theTSB81BA3E detectsthattheLPS inputisinactive,the PHY-LLC interfaceisplacedintoa low-powerresetstateinwhichtheCTL and D outputsareheldinthelogic0 stateand theLREQ inputisignored;however,thePCLK outputremainsactive.IftheLPS inputremainslow for more than the LPS_DISABLE time(see the LPS terminaldefinition),then the PHY-LLC interfaceisput intoa low-powerdisabledstatein which the PCLK outputis also held inactive.The TSB81BA3E continuesthe necessaryrepeaterfunctionsrequiredfornormal networkoperationregardlessof the stateof the PHY-LLC interface.When theinterfaceisintheresetor disabledstateand theLPS inputisagainobservedactive,the PHY initializestheinterfaceand returnstonormaloperation.The PHY-LLC interfaceisalsoheldinthedisabled stateduringhardwarereset.When theLPS terminalisreturnedtoan activestateafterbeingsensed as having enteredtheLPS_DISABLE time,theTSB81BA3E issuesa bus reset.Thisbroadcaststhenode self-IDpacket, whichcontainstheupdatedL bitstate(thePHY LLC now beingaccessible). The PHY uses theLKON/DS2 terminaltonotifytheLLC topower up and become active.When activated,the outputLKON/DS2 signalisa squarewave. The PHY activatestheLKON/DS2 outputwhen theLLC isinactive and a wake-up eventoccurs.The LLC isconsideredinactivewhen eithertheLPS inputisinactive,as described above,or the LCtrlbitisclearedto 0. A wake-up eventoccurswhen a link-onPHY packetaddressedto this node isreceived,orconditionallywhen a PHY interruptoccurs.The PHY deassertstheLKON/DS2 outputwhen the LLC becomes active(bothLPS sensed as activeand the LCtrlbitsetto 1).The PHY alsodeassertsthe LKON/DS2 outputwhen a bus resetoccurs,unlessa PHY interruptconditionexists,which would otherwise cause LKON/DS2 tobe active.IfthePHY ispower cycledand thepower classis0 through4,thenthePHY assertsLKON/DS2 forapproximately167 ms oruntilboththeLPS isactiveand theLCTRL bitis1.

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A VDD−3.3 DGND DVDD−CORE SM SE CPS DS0 DS1 PLL VDD−3.3 PLL VDD−CORE PLL VDD−CORE PLLGND XI RSVD PLLGND A VDD−3.3 AGND AGND AGND A VDD−3.3 DGND DVDD−CORE PC0 PC1 PC2 DVDD−3.3 DVDD−3.3 DVDD−CORE DGND VREG_PD BMODE RESETz DGND PD TESTM CNA LPS 5 6 7 8 PFP PACKAGE (TOP VIEW) TPB1+ 59 58 57 56 5560 54 TP A2+TP A2−TPB2+TPB2−TPBIAS1 TP A1+ D0 D2 LREQDGNDPCLK DVDD−3.3 LCLK DVDD−CORE 52 51 5053 9 10 1 1 12 13 49 48 PINT TPBIAS0 47 46 45 44 14 15 16 17 DGND D3 D4 D5 TP A0+ TP A0−TPBIAS2 DVDD−3.3 18 19 20 TPB0+ TPB0− 43 42 41 TP A1− TPB1−AGND CTL1 LKON/DS2 D1 D7 A VDD−3.3 TSB81BA3E CTL0 A VDD−3.3 A VDD−3.3AGND TSB81BA3E www.ti.com SLLS783A –MAY 2009–REVISED MAY 2010 PIN ASSIGNMENTS Copyright© 2009–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):TSB81BA3E

(TOP VIEW) TSB81BA3E SLLS783A –MAY 2009–REVISED MAY 2010 www.ti.com

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VREG_PD XI TPA0+ TPA0- TPBIAS0 TPBIAS1 TPBIAS2 Link Interface I/O Received Data Decoder/Retimer Arbitration and Control State Machine Logic Voltage Regulator Transmit Data Encoder Crystal Oscillator, PLL System, and Transmit Clock Generator Bilingual Cable Port 2 Bilingual Cable Port 1 Bilingual Cable Port 0 Bias Voltage and Current Generator TSB81BA3E www.ti.com SLLS783A –MAY 2009–REVISED MAY 2010 FUNCTIONAL BLOCK DIAGRAM Copyright© 2009–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):TSB81BA3E

SLLS783A –MAY 2009–REVISED MAY 2010 www.ti.com TERMINAL FUNCTIONS TERMINAL PFP ZAJ DESCRIPTIONPACKAGE PACKAGE NAME TYPE NO. NO. I/O 21,40,43, Analogcircuitgroundterminals.These terminalsmust be tiedtogethertoAGND (1) Supply See DGND –50,61,62 thelow-impedancecircuitboardgroundplane. Analogcircuitpower terminals.A combinationofhigh-frequencydecoupling capacitorsneareach terminalissuggested,such as paralleled0.1mF and and DVDD-3.3 terminalsmust be tiedtogetherwitha lowdc impedance connectionon thecircuitboard. Beta-mode input.ThisterminaldeterminesthePHY-linkinterface connectionprotocol.When logic-high(asserted),thePHY-linkinterface complieswiththe1394b-2002B PHY-linkinterface.When logic-low (deasserted),thePHY-linkinterfacecomplieswiththelegacy1394a-2000 BMODE CMOS 74 B6 I standard.When usingan LLC such as the1394b-2002TSB82AA2, this terminalmust be pulledhigh.When usingan LLC such as the1394a-2000 TSB12LV26, thisterminalmust be tiedlow. NOTE: The PHY-linkinterfacecannotbe changed between thedifferent protocolsduringoperation. Cablenotactiveoutput.Thisterminalisassertedhighwhen thereareno CNA CMOS 79 A2 O portsreceivingincomingbiasvoltage.When any portreceivesbias,this terminalgoes low. Cable-powerstatusinput.Thisterminalisnormallyconnectedtocable power througha 400-kΩ resistor.Thiscircuitdrivesan internalcomparator CPS CMOS 34 N9 I thatdetectsthepresenceofcablepower.Thistransitionfromcablepower sensed tocablepower notsensed can be used togeneratean interruptto theLLC. CTL0 9 F1 ControlI/Os.These bidirectionalsignalscontrolcommunicationbetween theCMOS I/OCTL1 10 G1 TSB81BA3E and theLLC. Bus holdersarebuiltintotheseterminals. 11,12,13, H1, H2, J2, Data I/Os.These arebidirectionaldatasignalsbetween theTSB82BA3 andD0-D7 CMOS 15,16,17, J1,K2,K1, I/O theLLC. Bus holdersarebuiltintotheseterminals.19,20 L1,M1 E5,F4,F5, F6,F7,F9, G4, G5, G6, G7, G8, G9,4,14,38,64, Digitalcircuitgroundterminals.These terminalsmust be tiedtogethertotheDGND (1) Supply G10, H4, H5, –72,76 low-impedancecircuitboardgroundplane.H6, H7, H8, J4,J5,J6, J7,J8,K7, Data-strobe-onlymode forport0.1394a-onlyport0 enableprogramming terminal.On hardwarereset,thisterminalallowstheusertoselectwhether port0 actslikea 1394b bilingualport(terminalatlogic0)oras a DS0 CMOS 33 N8 I 1394a-2000-onlyport(terminalatlogic1).Programming isaccomplishedby tyingtheterminallowthrougha 1-kΩ orlessresistor(toenable1394b bilingualmode) orhighthrougha 1-kΩ orlessresistor(toenable 1394a-2000-onlymode).A bus holderisbuiltintothisterminal. Data-strobe-onlymode forport1.1394a-onlyport1 enableprogramming terminal.On hardwarereset,thisterminalallowstheusertoselectwhether port1 actslikea 1394b bilingualport(terminalatlogic0)oras a DS1 CMOS 32 M7 I 1394a-2000-onlyport(terminalatlogic1).Programming isaccomplishedby tyingtheterminallowthrougha 1-kΩ orlessresistor(toenable1394b bilingualmode) orhighthrougha 1-kΩ orlessresistor(toenable 1394a-2000-onlymode).A bus holderisbuiltintothisterminal. (1) AllAGND and DGND terminalsareinternallytiedtogetherintheZAJ package.

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www.ti.com SLLS783A –MAY 2009–REVISED MAY 2010 TERMINAL FUNCTIONS (continued) TERMINAL PFP ZAJ DESCRIPTIONPACKAGE PACKAGE NAME TYPE NO. NO. I/O Digitalcorecircuitpower terminals.A combinationofhigh-frequency decouplingcapacitorsneareach terminalissuggested,such as paralleled PLLVDD-CORE, PLLVDD-3.3,and AVDD terminalsinternaltothedeviceto providenoiseisolation. Digital3.3-Vcircuitpower terminals.A combinationofhigh-frequency decouplingcapacitorsneareach terminalissuggested,such as paralleled 0.1mF and 0.001mF.Lower-frequency10-mF filteringcapacitorsarealso recommended. The DVDD-3.3 terminalsmust be tiedtogetherata DVDD-3.3 Supply 6,18,69,70 E4,K5,K6 – low-impedancepointon thecircuitboard.These supplyterminalsare separatedfromthePLLVDD-CORE, PLLVDD-3.3,DVDD-CORE, and AVDD terminalsinternaltothedevicetoprovidenoiseisolation.The PLLVDD-3.3,AVDD, and DVDD-3.3 terminalsmust be tiedtogetherwitha lowdc impedance connectionon thecircuitboard. Linkclock.Link-provided98.304-MHz clocksignaltosynchronizedata LCLK CMOS 7 G2 I transfersfromlinktothePHY when thePHY-linkinterfaceisinthe1394b mode. A bus holderisbuiltintothisterminal. Link-onoutput/Data-strobe-onlyinputforport2.Thisterminalmay be connectedtothelink-oninputterminaloftheLLC througha 1-kΩ resistorif thelink-oninputisavailableon thelinklayer. Data-strobe-onlymode forport2.1394a-onlyport0 enableprogramming terminal.On hardwarereset,thisterminalallowstheusertoselectwhether port2 actslikea 1394b bilingualport(terminalatlogic0)oras a 1394a-2000-onlyport(terminalatlogic1).Programming isaccomplishedby tyingtheterminallowthrougha 1-kΩ orlessresistortoenable1394b bilingualmode orhighthrougha 1-kΩ orlessresistortoenable 1394a-2000-onlymode. A bus holderisbuiltintothisterminal. Afterhardwarereset,thisterminalisthelink-onoutput,whichnotifiesthe LLC orotherpower-uplogictopower up and become active.The link-on outputisa squarewave signalwitha periodofapproximately163 ns (8PCLK cycles)when active.The link-onoutputisotherwisedrivenlow, exceptduringhardwareresetwhen itishighimpedance. The link-onoutputisactivatediftheLLC isinactive(theLPS inputinactive ortheLCtrlbitcleared)and when one: LKON/DS2 CMOS 2 D2 I/O a. The PHY receivesa link-onPHY packetaddressedtothisnode. b. The PEI (port-eventinterrupt)registerbitis1. c. Any of the CTOI (configuration-timeoutinterrupt),CPSI (cable-power-statusinterrupt),or STOI (state-time-outinterrupt) registerbitsis1 and theRPIE (resuming-portinterruptenable)register bitisalso1. d. The PHY ispower-cycledand thepower classis0 through4. Once activated,thelink-onoutputisactiveuntiltheLLC becomes active (boththeLPS inputactiveand theLCtrlbitset).The PHY alsodeasserts thelink-onoutputwhen a bus-resetoccursunlessthelink-onoutputis otherwiseactivebecause one oftheinterruptbitsisset(thatis,thelink-on outputisactivedue solelytothereceptionofa link-onPHY packet). Inthecase ofpower-cyclingthePHY, theLKON signalmust stopafter 167 ms iftheprecedingconditionshave notbeen met. NOTE: Ifan interruptconditionexists,whichotherwisewouldcause the link-onoutputtobe activatediftheLLC were inactive,thenthelink-on outputisactivatedwhen theLLC subsequentlybecomes inactive. Copyright© 2009–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):TSB81BA3E

SLLS783A –MAY 2009–REVISED MAY 2010 www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL PFP ZAJ DESCRIPTIONPACKAGE PACKAGE NAME TYPE NO. NO. I/O Linkpower statusinput.Thisterminalmonitorstheactive/powerstatusof thelink-layercontroller(LLC)and controlsthestateofthePHY-LLC interface.Thisterminalmust be connectedtoeithertheVDD supplyingthe LLC throughan approximately1-kΩ resistorortoa pulsedoutputthatis activewhen theLLC ispowered.A pulsedsignalmust be used when an isolationbarrierexistsbetween theLLC and PHY (seeFigure8). The LPS inputisconsideredinactiveifitissampled lowby thePHY for more thanan LPS_RESET time(~2.6ms),and isconsideredactive otherwise(thatis,assertedsteadyhighoran oscillatingsignalwitha low timelessthan2.6ms).The LPS inputmust be highforatleast22 ns tobe observedas highby thePHY. LPS CMOS 80 D3 I When theTSB81BA3E detectsthattheLPS inputisinactive,itplacesthe PHY-LLC interfaceintoa low-powerresetstate.Intheresetstate,theCTL (CTL0 and CTL1) and D (D0 toD7) outputsareheldinthelogic0 stateand theLREQ inputisignored;however,thePCLK outputremainsactive.Ifthe LPS inputremainslowformore thanan LPS_DISABLE time(~26ms),then thePHY-LLC interfaceisputintoa low-powerdisabledstateinwhichthe PCLK outputisalsoheldinactive. The LLC statethatiscommunicatedintheself-IDpacketisconsidered activeonlyifboththeLPS inputisactiveand theLCtrlregisterbitissetto 1.The LLC statethatiscommunicatedintheself-IDpacketisconsidered inactiveifeithertheLPS inputisinactiveortheLCtrlregisterbitiscleared to0. LLC requestinput.The LLC uses thisinputtoinitiatea servicerequesttoLREQ CMOS 3 E1 I theTSB81BA3E. A bus holderisbuiltintothisterminal. Power classprogramminginputs.On hardwarereset,theseinputssetthe PC0 66 C11 defaultvalueofthepower classindicatedduringself-ID.Programming is PC1 CMOS 67 A9 I done by tyingtheterminalshighthrougha 1-kΩ orsmallerresistororby PC2 68 B8 tyingdirectlytogroundthrougha 1-kΩ orsmallerresistor.Bus holdersare builtintotheseterminals. PHY clock.Providesa 98.304-MHz clocksignal,synchronizedwithdata transfers,totheLLC when thePHY-linkinterfaceisoperatinginthe1394b PCLK CMOS 5 F2 O mode (BMODE asserted).PCLK outputprovidesa 49.152-MHz clock signal,synchronizedwithdatatransfers,totheLLC when thePHY-link interfaceisinlegacy1394a-2000(BMODE inputdeasserted). Power-down input.A highon thisterminalturnsoffallinternalcircuitry exceptthecable-activemonitorcircuits,whichcontroltheCNA output.PD CMOS 77 B3 I AssertingthePD inputhighalsoactivatesan internalpulldownon the RESET terminaltoforcea resetoftheinternalcontrollogic. PHY interrupt.The PHY uses thisoutputtoseriallytransferstatusand PINT CMOS 1 E3 O interruptinformationtothelinkwhen PHY-linkinterfaceisinthe1394b mode. A bus holderisbuiltintothisterminal. PLL circuitgroundterminals.These terminalsmust be tiedtogethertothePLLGND Supply 25,28 F8,N4 – low-impedancecircuitboardgroundplane. PLL corecircuitpower terminals.A combinationofhigh-frequency decouplingcapacitorsneareach terminalissuggested,such as paralleled PLLVDD- 0.1mF and 0.001mF.An additional1-mF capacitorisrequiredforvoltageSupply 29,30 N6 –CORE regulation.The PLLVDD-CORE terminalsmust be separatefromthe DVDD-CORE terminals.These supplyterminalsareseparatedfromthe DVDD-CORE, DVDD-3.

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www.ti.com SLLS783A –MAY 2009–REVISED MAY 2010 TERMINAL FUNCTIONS (continued) TERMINAL PFP ZAJ DESCRIPTIONPACKAGE PACKAGE NAME TYPE NO. NO. I/O PLL 3.3-Vcircuitpower terminal.A combinationofhigh-frequency decouplingcapacitorsneartheterminalaresuggested,such as paralleled 0.1mF and 0.001mF.Lower frequency10-mF filteringcapacitorsarealso a low-impedancepointon thecircuitboard.The PLLVDD-3.3,AVDD-3.3, and DVDD-3.3 terminalsmust be tiedtogetherwitha lowdc impedance connection. Logicresetinput.Assertingthisterminallowresetstheinternallogic.An internalpullupresistortoVDD isprovidedso onlyan externaldelay capacitorisrequiredforproperpower-upoperation(seepower-upresetin RESET CMOS 75 A6 I theApplicationsInformationsection). The RESET terminalalsoincorporatesan internalpulldown,whichis activatedwhen thePD inputisassertedhigh.Thisinputisotherwisea standardlogicinput,and can alsobe drivenby an open-drain-typedriver. Thisterminalmust normallybe leftunconnected.When thisterminalis probed,theterminalshows a 98.304-MHz signal.Ifthisisperceivedas an RSVD Osc Out 26 M5 O EMI problem,thentheterminalmay be pulledtogroundthrougha 10-kΩ resistor.However,thiscausesan increaseofup to340 mA indevicecurrent consumption. Currentsettingresistorterminals.These terminalsareconnectedtoa R0 23 N3 precisionexternalresistancetosettheinternaloperatingcurrentsand cableBias –R1 22 N2 driveroutputcurrents.A resistanceof6.34kΩ,±1%, isrequiredtomeet the IEEE Std1394-1995outputvoltagelimits. Testcontrolinput.Thisinputisused inthemanufacturingtestofthe SE CMOS 35 M10 I TSB81BA3E. Fornormaluse thisterminalmust be pulledloweitherthrough a 1-kΩ resistortoGND ordirectlytoGND. Testcontrolinput.Thisinputisused inthemanufacturingtestofthe SM CMOS 36 N10 I TSB81BA3E. Fornormaluse thisterminalmust be pulledloweitherthrough a 1-kΩ resistortoGND ordirectlytoGND. Testcontrolinput.Thisinputisused inthemanufacturingtestofthe TESTM CMOS 78 A3 I TSB81BA3E. Fornormaluse thisterminalmust be pulledhighthrougha 1-kΩ resistortoVDD . Voltageregulatorpower-down input.When assertedlogichigh,thispinwill power-down theinternal3.3-Vto1.95-Vregulator.Forsingle3.3-Vsupply VREG_PD CMOS 73 B7 I operation,thispinshouldbe tiedtoGND. Ifan externalregulatorisused to supplythe1.95-VPLLVDD-CORE and DVDD-CORE power railsthis terminalsshouldbe pulledtoVcc througha 1-kΩ resistortoVDD . Port-0twisted-pairdifferential-signalterminals.Board tracesfromeach pairTPA0 – 45 K13 ofpositiveand negativedifferentialsignalterminalsmust be keptmatchedTPA0+ 46 J13Cable I/O and as shortas possibletotheexternalloadresistorsand tothecableTPB0 – 41 M13 connector.RequesttheS800 1394b layoutrecommendationsdocumentTPB0+ 42 L13 fromyourTexas Instrumentsrepresentative. Port-1twisted-pairdifferential-signalterminals.Board tracesfromeach pairTPA1 – 52 F13 ofpositiveand negativedifferentialsignalterminalsmust be keptmatchedTPA1+ 53 E13Cable I/O and as shortas possibletotheexternalloadresistorsand tothecableTPB1 – 48 H13 connector.RequesttheS800 1394b layoutrecommendationsdocumentTPB1+ 49 G13 fromyourTexas Instrumentsrepresentative. Port-2twisted-pairdifferential-signalterminals.Board tracesfromeach pairTPA2 – 58 B13 ofpositiveand negativedifferentialsignalterminalsmust be keptmatchedTPA2+ 59 A13Cable I/O and as shortas possibletotheexternalloadresistorsand tothecableTPB2 – 55 D13 connector.RequesttheS800 1394b layoutrecommendationsdocumentTPB2+ 56 C13 fromyourTexas Instrumentsrepresentative. Copyright© 2009–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):TSB81BA3E

SLLS783A –MAY 2009–REVISED MAY 2010 www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL PFP ZAJ DESCRIPTIONPACKAGE PACKAGE NAME TYPE NO. NO. I/O Twisted-pairbiasoutputand signaldetectinput.Thisprovidesthe1.86-V nominalbiasvoltageneeded forproperoperationofthetwisted-paircable driversand receivers,and forsignalingtotheremotenodes thatthereisanTPBIAS0 47 J12 activecableconnectionin1394a-2000mode. Each oftheseterminals,TPBIAS1 Cable 54 E12 I/O exceptforan unused port,must be decoupledwitha 1-mF capacitortoTPBIAS2 60 A12 ground.Fortheunused port,thisterminalcan be leftunconnected.Please requesttheS800 1394b layoutrecommendationdocuments fromyourTI representative. Oscillatorinput.Thisterminalconnectstoa 98.304-MHz lowjitterexternal oscillator.The XIterminalisa 1.8-VCMOS input. Oscillatorjittermust be 5 ps RMS orbetter. Ifonly3.3-Voscillatorscan be acquired,thengreatcaremust be takento XI Osc In 27 N5 – notintroducesignificantjitterby themeans used tolevelshiftfrom3.3V to 1.8V.Ifa resistordividerisused,thena highcurrentoscillatorand low-valueresistorsmust be used tominimizeRC timeconstants.Ifa level-shiftingcircuitisused,thenitmust introduceverylittlejitter.Please see layoutrecommendationsdocument. AbsoluteMaximum Ratings(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT VDD Supplyvoltagerange(2) –0.3 4 V VI Inputvoltagerange(2) –0.5 VDD + 0.5 V VO Outputvoltagerangeatany output –0.5 VDD + 0.5 V Continuoustotalpower dissipation See DissipationRatingsTable TSB81BA3E 0 70 TA Operatingfree-airtemperature °C TSB81BA3EI –40 85 Tstg Storagetemperaturerange 65 150 °C Lead temperature1.6mm (1/16in)fromcase for10 s 260 °C (1) Stressesbeyond thoselistedunder"absolutemaximum ratings"may cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunder"recommended operating conditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) Allvoltagevalues,exceptdifferentialI/Obus voltages,arewithrespecttonetworkground. DissipationRatings TA 25°C DERATING FACTOR (1) TA = 70°C TA = 85°CPACKAGE POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING (1) Thisistheinverseofthetraditionaljunction-to-ambientthermalresistance(RqJA). (2) 2-oz.traceand copperpad withsolder. (3) Formore information,see theTexas InstrumentsapplicationnotePowerPAD ™ ThermallyEnhanced Package,(SLMA002). (4) 2-oz.traceand copperpad withoutsolder.

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www.ti.com SLLS783A –MAY 2009–REVISED MAY 2010 RECOMMENDED OPERATING CONDITIONS MIN TYP (1) MAX UNIT Sourcepower node 3.0 3.3 3.6 3.3VDD Supplyvoltage V Nonsourcepower node 3.0(2) 3.3 3.6 Core Supplyvoltage 1.85 1.95 2.05 VVDD LREQ, CTL0, CTL1, D0-D7,LCLK 2.6 0.7×LKON/DS2, PC0, PC1, PC2, PD, BMODEVIH High-levelinputvoltage VDD V 0.6×RESETz VDD LREQ, CTL0, CTL1, D0-D7,LCLK 1.2 VIL Low-levelinputvoltage LKON/DS2, PC0, PC1, PC2, PD, BMODE 0.2× VDD V RESETz 0.3× VDD VOD 1394b Differentialoutputvoltage 700 mV 1394b Common-mode outputVCM 1.5 Vvoltage VD D = 3.3V 4 mASupplycurrentinlowIDD power/suspend(3) VD D = 3 V 3 mA CTL0, CTL1, D0-D7,CNA, LKON/DS2, PINT,andIOL/OH Outputcurrent –4 4 mAPCLK IO Outputcurrent TPBIAS outputs –5.6 1.3 mA OperatingambienttemperatureTA TSB81BA3E 0 70 °Crange TJ Junctiontemperature(4) TSB81BA3E 0 105 °C VID 1394b Differentialinputvoltage Cableinputs,duringdatareception 200 800 mV Cableinputs,duringdatareception 118 260 VID 1394a Differentialinputvoltage mV Cableinputs,duringarbitration 168 265 TPB cableinputs,sourcepower node 0.4706 2.5151394a Common-mode inputVIC Vvoltage TPB cableinputs,nonsourcepower node 0.4706 2.015(2) tpu Power-upresettime RESETz input 2(5) ms TPA, TPB cableinputs,S100 operation ±1.08 Receiveinputjitter TPA, TPB cableinputs,S200 operation ±0.5 ns TPA, TPB cableinputs,S400 operation ±0.315 Between TPA and TPB cableinputs,S100 ±0.8operation Between TPA and TPB cableinputs,S200Receiveinputskew ±0.55 nsoperation Between TPA and TPB cableinputs,S400 ±0.5operation (1) AlltypicalvaluesareatVDD = 3.3V and TA = 25°C. (2) Fora node thatdoes notsourcepower,see Section4.2.2.2inIEEE 1394a-2000. (3) The lowpower/suspendmode assumes thatthedeviceisnotreceivingpacketsand itistoning. (4) The junctiontemperaturereflectssimulatedconditions.The customerisresponsibleforverifyingjunctiontemperature. (5) Time aftervalidclockreceivedatPHY XIinputterminal. Copyright© 2009–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):TSB81BA3E

SLLS783A –MAY 2009–REVISED MAY 2010 www.ti.com

ELECTRICAL CHARACTERISTICS

overrecommended rangesofoperatingconditions(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOD Differentialoutputvoltage 56 Ω,See Figure1 172 265 mV Driversenabled,speed signalingIDIFF Driverdifferencecurrent,TPA+, TPA –,TPB+, TPB – –1.05(1) 1.05(1) mAoff Common-mode speed signalingcurrent,TPB+,ISP200 S200 speed signalingenabled –4.84(2) –2.53(2) mATPB – Common-mode speed signalingcurrent,TPB+,ISP400 S400 speed signalingenabled –12.4(2) –8.1(2) mATPB – VOFF Off-statedifferentialvoltage Driversdisabled,See Figure1 20 mV (1) Limitsdefinedas algebraicsum ofTPA+ and TPA – drivercurrents.LimitsalsoapplytoTPB+ and TPB – algebraicsum ofdriver currents. (2) Limitsdefinedas absolutelimitofeach ofTPB+ and TPB – drivercurrents. Receiver PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 4 7 kΩ ZID Differentialimpedance Driversdisabled 4 pF 20 kΩ ZIC Common-mode impedance Driversdisabled 24 pF VTH-R Receiverinputthresholdvoltage Driversdisabled –30 30 mV VTH-CB Cablebiasdetectthreshold,TPBx cableinputs Driversdisabled 0.6 1 V PositivearbitrationcomparatorthresholdVTH+ Driversdisabled 89 168 mVvoltage NegativearbitrationcomparatorthresholdVTH – Driversdisabled –168 –89 mVvoltage VTH-SP200 Speed signalthreshold 49 131 mVTPBIAS-TPA common-mode voltage, driversdisabledVTH-SP400 Speed signalthreshold 314 396 mV Device PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 3.3VDD 120 150 IDD Supplycurrent (1) mA Core VDD 79 VTH Power statusthreshold,CPS input(2) 400-kΩ resistor(2) 4.7 7.5 V High-leveloutputvoltage,CTL0, CTL1, D0-D7,PCLK, VDD = 3 to3.6V,VOH 2.8 VLKON/DS2 outputs IOH = 4 mA Low-leveloutputvoltage,CTL0, CTL1, D0-D7,PCLK,VOL IOL = 4 mA 0.4 VLKON/DS2 outputs VDD = 3.6V,IBH+ Positivepeak bus holdercurrent,D0-D7,CTL0-CTL1, LREQ 0.05 1 mAVI= 0 V toVDD Negativepeak bus holdercurrent,D0-D7,CTL0-CTL1, VDD = 3.6V,IBH – –1.0 –0.05 mALREQ VI= 0 V toVDD TSB81BA3E ±5Off-stateoutputcurrent,CTL0, CTL1, D0-D7,LKON/DS2IOZ VO = VDD or0 V mAI/Os TSB81BA3EI ±20 IIRST Pullupcurrent,RESET input VI= 1.5V or0 V –90 –20 mA VO TPBIAS outputvoltage AtratedIO current 1.665 2.015 V (1) Repeat max packet(oneportreceivingmaximum sizeisochronouspacket–8192 bytes,senton everyisochronousinterval,S800,data valueof0xCCCCCCCCh; two portsrepeating;allportswithbeta-modeconnection),VDD3.3 = 3.3V,V DDCORE = 1.95V,TA = 25°C. (2) Measured atcable-powersideofresistor.

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www.ti.com SLLS783A –MAY 2009–REVISED MAY 2010 ElectricalCharacteristics(continued) Thermal Characteristics PARAMETER TEST CONDITIONS (1) TYP TYP UNIT PFP ZAJ Package Package Junction-to-free-airthermalqja Low K JEDEC TestBoard,1s (singlesignallayer),no airflow 50 88.7 °C/Wresistance No airflow 24.8 46.2 Junction-to-free-airthermal HighK JEDEC TestBoard 2s2p (doubleqja 400 LFM °C/Wresistance signallayer,doubleburiedpower plane)

200 LFM

Junction-to-case-thermalqjc Cu ColdPlateMeasurement Process 21.5 23.5 °C/Wresistance Junction-to-boardthermalqjb EIA/JESD 51-8 8.37 27.8resistance Ψjt Junction-to-topofpackage EIA/JESD 51-2 0.46 0.45 °C/W Ψjb Junction-to-board EIA/JESD 51-6 8.2 27.4 °C/W (1) Formore details,pleaserefertoTIapplicationnoteon IC Package ThermalMetrics(SPRA953A) SwitchingCharacteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tr TP differentialrisetime,transmit 10% to90%, At1394 connector 0.5 1.2 ns tf TP differentialfalltime,transmit 90% to10%, At1394 connector 0.5 1.2 ns Setuptime,tsu 1394a-2000 50% to50%, See Figure2 2.5 nsCTL0, CTL1, D1-D7,LREQ toPCLK Holdtime,th 1394a-2000 50% to50%, See Figure2 0 nsCTL0, CTL1, D1-D7,LREQ afterPCLK Setuptime,tsu 1394b 50% to50%, See Figure2 2.5 nsCTL0, CTL1, D1-D7,LREQ toLCLK_PMC Holdtime,th 1394b 50% to50%, See Figure2 0 nsCTL0, CTL1, D1-D7,LREQ afterLCLK_PMC Delaytime, 1394a-2000td 50% to50%, See Figure3 0.5 7 nsPCLK toCTL0, CTL1, D1-D7,PINT and 1394b Copyright© 2009–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):TSB81BA3E

TPAx− TPBx− 56 Ω thtsu Dx, CTLx, LREQ xCLK td Dx, CTLx xCLK TSB81BA3E SLLS783A –MAY 2009–REVISED MAY 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION Figure1.TestLoad Diagram Figure2.Dx, CTLx, LREQ InputSetup and Hold Time Waveforms Figure3.Dx and CTLx Output Delay RelativetoxCLK Waveforms

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APPLICATION INFORMATION

Pleaseobtainfrom theTI websiteor yourlocalTI representativethereferenceschematics,referencelayouts, debug documents,and softwarerecommendationsfortheTSB81BA3E. InternalRegisterConfiguration There are16 accessibleinternalregistersintheTSB81BA3E. The configurationoftheregistersataddresses0h through7h (thebase registers)isfixed,whiletheconfigurationoftheregistersataddresses8h throughFh (the paged registers)isdependent upon which 1 of 8 pages,numbered 0h through7h, iscurrentlyselected.The selectedpage issetinbase register7h.Note thatwhilethisregistersetiscompatiblewith1394a--2000register sets,some fieldshave been redefinedand thisregistersetcontainsadditionalfields. Table1 shows theconfigurationofthebase registers,and Table2 givesthecorrespondingfielddescriptions. The base registerfielddefinitionsareunaffectedby theselectedpage number. A reservedregisterorregisterfield(markedas Reserved orRsvd inthefollowingregisterconfigurationtables)is readas 0,butissubjecttofutureusage.Allregistersinaddresspages 2 through6 arereserved. Table1.Base RegisterConfiguration BIT POSITION ADDRESS 0 1 2 3 4 5 6 7

0000 PhysicalID R CPS

0001 RHB IBR Gap_Count

0010 Extended(111b) Num_Ports (0011b)

0011 PHY_Speed (111b) SREN Delay(1111b)

0100 LCtrl C Jitter(000b) Pwr_Class

0101 WDIE ISBR CTOI CPSI STOI PEI EAA EMC

0110 Max Legacy SPD BLINK Bridge Rsvd

0111 Page_Select Rsvd Port_Select

Table2.Base RegisterFieldDescriptions FIELD SIZE TYPE DESCRIPTION ThisfieldcontainsthephysicaladdressID ofthisnode determinedduringself-ID.The physical-IDis PhysicalID 6 Rd invalidaftera bus resetuntiltheself-IDhas completedas indicatedby an unsolicitedregister0 statustransferfromthePHY totheLLC. Root.Thisbitindicatesthatthisnode istherootnode.The R bitisresetto0 by bus reset,and isR 1 Rd setto1 duringtree-IDifthisnode becomes root. Cable-powerstatus.ThisbitindicatesthestateoftheCPS inputterminal.The CPS terminalis CPS 1 Rd normallytiedtoserialbus cablepower througha 400-kΩ resistor.A 0 inthisbitindicatesthatthe cable-powervoltagehas droppedbelowitsthresholdforensuredreliableoperation. Root-holdoffbit.ThisbitinstructsthePHY toattempttobecome rootafterthenextbus reset.The RHB bitisresetto0 by a hardwareresetand isunaffectedby a bus reset.Iftwo nodes on a singleRHB 1 Rd/Wr bus have theirrootholdoffbitset,thentheresultisnotdefined.To preventtwo nodes fromhaving theirroot-holdoffbitset,thisbitmust onlybe writtenusinga PHY configurationpacket. Initiatebus reset.ThisbitinstructsthePHY toinitiatea long(166-ms)bus resetatthenext opportunity.Any receiveortransmitoperationinprogresswhen thisbitissetcompletesbeforethe IBR 1 Rd/Wr bus resetisinitiated.The IBR bitisresetto0 aftera hardwareresetora bus reset.Care must be exercisedwhen writingtothisbittonotchange theotherbitsinthisregister.Itisrecommended that whenever possiblea bus resetbe initiatedusingtheISBR bitand nottheIBR bit. Arbitrationgap count.Thisvaluesetsthesubaction(fair)gap,arb-resetgap,and arb-delaytimes. The gap countcan be seteitherby a writetotheregister,orby receptionortransmissionofa PHY_CONFIG packet.The gap countisresetto3Fh by hardwareresetoraftertwo consecutiveGap_Count 6 Rd/Wr bus resetswithoutan interveningwritetothegap countregister(eitherby a writetothePHY registerorby a PHY_CONFIG packet).Itisstronglyrecommended thatthisfieldonlybe changed using PHY configurationpackets. Extendedregisterdefinition.FortheTSB81BA3E, thisfieldis111b,indicatingthattheextendedExtended 3 Rd registersetisimplemented. Copyright© 2009–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):TSB81BA3E

SLLS783A –MAY 2009–REVISED MAY 2010 www.ti.com Table2.Base RegisterFieldDescriptions(continued) FIELD SIZE TYPE DESCRIPTION Number ofports.FortheTSB81BA3E, thisfieldindicatesthenumber ofportsimplementedintheNum_Ports 4 Rd PHY. Thisfieldis3. PHY speed capability.FortheTSB81BA3E, thisfieldisno longerused.Thisfieldis111b.SpeedsPHY_Speed 3 Rd for1394b PHYs must be checkedon a port-by-portbasis. PHY repeaterdatadelay.Thisfieldindicatestheworst-caserepeaterdatadelayofthePHY, expressedas 144+ (delay× 20)ns.FortheTSB81BA3E, thisfieldis02h. ThisvalueistherepeaterdelayfortheS400B case,whichisslowerthantheS800B or1394a Delay 4 Rd cases.SincetheIEEE 1394B−2002 StdPhy registersetonlyhas a singlefieldforthedelay parameter,theslowestvalueisused.Ifa networkuses onlyS800B or1394a connections,thena delayvalueof00h may be used.The worstcase Phy repeaterdelayis197 ns forS400B and 127 ns forS800B cablespeeds (trained,raw bitspeed). Link-activestatuscontrol.ThisbitcontrolstheindicatedactivestatusoftheLLC reportedinthe self-IDpacket.The logicalAND ofthisbitand theLPS activestatusisreplicatedintheL field(bit9) oftheself-IDpacket.The LLC bitinthenode self-IDpacketissetactiveonlyifboththeLPS inputis activeand theLCtrlbitisset. The LCtrlbitprovidesa software-controllablemeans toindicatetheLLC self-IDactivestatusinlieu LCtrl 1 Rd/Wr ofusingtheLPS inputterminal. The LCtrlbitissetto1 by hardwareresetand isunaffectedby bus reset. NOTE: The stateofthePHY-LLC interfaceiscontrolledsolelyby theLPS input,regardlessofthe stateoftheLCtrlbit.IfthePHY-LLC interfaceisoperationalas determinedby theLPS inputbeing active,thenreceivedpacketsand statusinformationcontinuetobe presentedon theinterface,and any requestsindicatedon theLREQ inputareprocessed,even iftheLCtrlbitisclearedto0. Contenderstatus.Thisbitindicatesthatthisnode isa contenderforthebus orisochronous resourcemanager.Thisbitisreplicatedinthec field(bit20)oftheself-IDpacket.Thisbitissetto0C 1 Rd/Wr on hardwarereset.Afterhardwarereset,thisbitcan onlybe setviaa softwareregisterwrite.This bitisunaffectedby a bus reset. PHY repeaterjitter.Thisfieldindicatestheworst-casedifferencebetween thefastestand slowestJitter 3 Rd repeaterdatadelay,expressedas (jitter+1)× 20 ns.FortheTSB81BA3E, thisfieldis0. Node power class.Thisfieldindicatesthisnode power consumptionand sourcecharacteristicsand isreplicatedinthepwr field(bits21–23)oftheself-IDpacket.ThisfieldisresettothestatePwr_Class 3 Rd/Wr specifiedby thePC0-PC2 inputterminalsupon a hardwarereset,and isunaffectedby a bus reset. See Table9. Watchdog interruptenable.Thisbit,ifsetto1,enablestheporteventinterrupt(PIE)bittobe set when resume operationsbeginon any port,orwhen any oftheCTOI, CPSI,orSTOI interruptbitsWDIE 1 Rd/Wr aresetand thelinkinterfaceisnonoperational.Thisbitisresetto0 by hardwareresetand is unaffectedby bus reset. Initiateshortarbitratedbus reset.Thisbit,ifsetto1,instructsthePHY toinitiatea short(1.3ms) arbitratedbus resetatthenextopportunity.Thisbitisresetto0 by a bus reset.Itisrecommended thatshortbus resetistheonlyresettypeinitiatedby software.IEC 61883-6requiresthata node ISBR 1 Rd/Wr initiateshortbus resetstominimizeany disturbancetoan audiostream. NOTE: Legacy IEEE Std1394-1995-compliantPHYs arenotcapableofperformingshortbus resets.Therefore,initiationofa shortbus resetina networkthatcontainssuch a legacydevice resultsina longbus resetbeingperformed. Configurationtime-outinterrupt.Thisbitissetto1 when thearbitrationcontrollertimesoutduring tree-IDstartand mightindicatethatthebus isconfiguredina loop.Thisbitisresetto0 by hardwareresetorby writinga 1 tothisregisterbit. IftheCTOI and WDIE bitsarebothsetand theLLC isorbecomes inactive,thenthePHY activates theLKON/DS2 outputtonotifytheLLC toservicetheinterrupt.CTOI 1 Rd/Wr NOTE: Ifthenetworkisconfiguredina loop,thenonlythosenodes thatarepartoftheloop generatea configurationtime-outinterrupt.Allothernodes insteadtimeoutwaitingforthetree-ID and/orself-IDprocesstocompleteand thengeneratea statetime-outinterruptand bus reset.This bitisonlysetwhen thebus topologyincludes1394a nodes;otherwise,1394b loophealingprevents loopsfrombeingformedinthetopology. Cablepower statusinterrupt.Thisbitissetto1 when theCPS inputtransitionsfromhightolow, indicatingthatcablepower mightbe toolowforreliableoperation.Thisbitisresetto1 by hardware CPSI 1 Rd/Wr reset.Itcan be clearedby writinga 1 tothisregisterbit. IftheCPSI and WDIE bitsarebothsetand theLLC isorbecomes inactive,thenthePHY activates theLKON/DS2 outputtonotifytheLLC toservicetheinterrupt.

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www.ti.com SLLS783A –MAY 2009–REVISED MAY 2010 Table2.Base RegisterFieldDescriptions(continued) FIELD SIZE TYPE DESCRIPTION Statetime-outinterrupt.Thisbitindicatesthata statetime-outhas occurred(whichalsocausesa bus resettooccur).Thisbitisresetto0 by hardwareresetorby writinga 1 tothisregisterbit.STOI 1 Rd/Wr IftheSTOI and WDIE bitsarebothsetand theLLC isorbecomes inactive,thenthePHY activates theLKON/DS2 outputtonotifytheLLC toservicetheinterrupt. Porteventinterrupt.Thisbitissetto1 on any change intheconnected,bias,disabled,orfaultbits forany portforwhichtheportinterruptenable(PEI)bitisset.Additionally,iftheresumingportPEI 1 Rd/Wr interruptenable(WDIE) bitisset,thenthePEI bitissetto1 atthestartofresume operationson any port.Thisbitisresetto0 by hardwarereset,orby writinga 1 tothisregisterbit. Enableacceleratedarbitration.ThisbitenablesthePHY toperformthevariousarbitration accelerationenhancements definedin1394a-2000(ACK-acceleratedarbitration,asynchronous fly-byconcatenation,and isochronousfly-byconcatenation).Thisbitisresetto0 by hardwarereset and isunaffectedby bus reset.Thisbithas no effectwhen thedeviceisoperatingin1394b mode. EAA 1 Rd/Wr NOTE: The use ofacceleratedarbitrationiscompletelycompatiblewithnetworkscontaininglegacy IEEE Std1394-1995PHYs. The EAA bitissetonlyiftheattachedLLC is1394a-2000-compliant.If theLLC isnot1394a-2000or1394b-2002-compliant,thentheuse ofthearbitrationacceleration enhancements can interferewithisochronoustrafficby excessivelydelayingthetransmissionof cycle-startpackets. Enablemultispeedconcatenatedpackets.ThisbitenablesthePHY totransmitconcatenated packetsofdifferingspeeds inaccordancewiththeprotocolsdefinedin1394a-2000.Thisbitisreset to0 by hardwareresetand isunaffectedby bus reset.Thisbithas no effectwhen thedeviceis EMC 1 Rd/Wr operatingin1394b mode. NOTE: The use ofmultispeedconcatenationiscompletelycompatiblewithnetworkscontaining legacyIEEE Std1394-1995PHYs. However,use ofmultispeedconcatenationrequiresthatthe attachedLLC be 1394a-2000or1394b-2002-compliant. Maximum legacy-pathspeed.Thisfieldholdsthemaximum speed capabilityofany legacynode Max Legacy SPD 3 Rd (1394a-2000or1394-1995-compliant)as indicatedintheself-IDpacketsreceivedduringbus initialization.Encodingisthesame as forthePHY_SPEED field(butlimitedtoS400 maximum). Beta-mode link.Thisbitindicatesthata Beta-mode-capablelinkisattachedtothePHY. ThisbitisBLINK 1 Rd setby theBMODE inputterminalon theTSB81BA3E. Thisfieldcontrolsthevalueofthebridge(brdg)fieldinself-IDpacket.The power resetvalueis0.Bridge 2 Rd/Wr Detailsforwhen tosetthesebitsarespecifiedintheIEEE 1394.1bridgingspecification. Page_Select.Thisfieldselectstheregisterpage touse when accessingregisteraddresses8Page_Select 3 Rd/Wr through15.Thisfieldisresetto0 by a hardwareresetand isunaffectedby bus reset. Port_Select.Thisfieldselectstheportwhen accessingper-portstatusorcontrol(forexample,when Port_Select 4 Rd/Wr one oftheportstatus/controlregistersisaccessedinpage 0).Portsarenumbered startingat0. Thisfieldisresetto0 by hardwareresetand isunaffectedby bus reset. The portstatuspage providesaccess toconfigurationand statusinformationforeach oftheports.The portis selectedby writing0 to the Page_Selectfieldand the desiredportnumber to the Port_Selectfieldin base register7.Table3 shows theconfigurationoftheportstatuspage registers,and Table4 givesthecorresponding fielddescriptions.Iftheselectedportisunimplemented,thenallregistersintheportstatuspage arereadas 0. Table3.Page 0 (PortStatus)RegisterConfiguration BIT POSITION ADDRESS 0 1 2 3 4 5 6 7

0000 Astat Bstat Ch Con RxOK Dis

0001 Negotiated_speed PIE Fault Standby_fault Disscrm B_Only (0)

0010 DC_connected Max_port_speed LPP Cable_speed

0011 Connection_unreliable Reserved Beta_mode Reserved

0100 Port_error

0101 Reserved Loop_disable In_standby Hard_disable

0110 Reserved

0111 Reserved

SLLS783A –MAY 2009–REVISED MAY 2010 www.ti.com Table4.Page 0 (PortStatus)RegisterFieldDescriptions FIELD SIZE TYPE DESCRIPTION TPA linestate.ThisfieldindicatestheinstantaneousTPA linestateoftheselectedport,encoded as follows: Code Arb Value

11 ZAstat 2 Rd

TPB linestate.ThisfieldindicatestheTPB linestateoftheselectedport.Thisfieldhas thesameBstat 2 Rd encodingas theAstatfield. Child/parentstatus.A 1 indicatesthattheselectedportisa childport.A 0 indicatesthattheselected Ch 1 Rd portistheparentport.A disconnected,disabled,orsuspended portisreportedas a childport.The Ch bitisinvalidaftera bus resetuntiltree-IDhas completed. Debounced portconnectionstatus.Thisbitindicatesthattheselectedportisconnected.The connectionmust be stableforthedebounce timeofapproximately341 ms fortheCon bittobe setto 1.The Con bitisresetto0 by hardwareresetand isunaffectedby bus reset.Con 1 Rd NOTE: The Con bitindicatesthattheportisphysicallyconnectedtoa peerPHY, butthisdoes not mean thattheportisnecessarilyactive.For1394b-coupledconnections,theCon bitissetwhen a portdetectsconnectiontonesfromthepeerPHY and operating-speednegotiationiscompleted. ReceiveOK. In1394a-2000mode thisbitindicatesthereceptionofa debounced TPBias signal.In RxOK 1 Rd Betamode, thisbitindicatesthereceptionofa continuouselectricallyvalidsignal. Note:RxOK issettofalseduringthetimethatonlyconnectiontonesaredetectedinBetamode. Portdisabledcontrol.Ifthisbitis1,thentheselectedportisdisabled.The Disbitisresetto0 by hardwarereset(allportsareenabledfornormaloperationfollowinghardwarereset).The DisbitisnotDis 1 Rd/Wr affectedby bus reset.When thisbitisset,theportcannotbecome active;however,theportstill tones,butdoes notestablishan activeconnection. Indicatesthemaximum speed negotiatedbetween thisPHY portand itsimmediatelyconnectedport. Negotiated_speed 3 Rd The encodingisas forMax_port_speed.Itissetduringconnectionwhen inBetamode ortoa value establishedduringself-IDwhen in1394a-2000mode. Port-event-interruptenable.When thisbitis1,a porteventon theselectedportsetsthe PIE 1 Rd/Wr port-event-interrupt(PEI)bitand notifiesthelink.Thisbitisresetto0 by a hardwareresetand is unaffectedby bus reset. Fault.Thisbitindicatesthata resume faultorsuspend faulthas occurredon theselectedport,and thattheportisinthesuspended state.A resume-faultoccurswhen a resumingportfailstodetect Fault 1 Rd/Wr incomingcablebiasfromitsattachedpeer.A suspend faultoccurswhen a suspendingportcontinues todetectincomingcablebiasfromitsattachedpeer.Writing1 tothisbitclearstheFaultbitto0.This bitisresetto0 by hardwareresetand isunaffectedby bus reset. Thisbitissetto1 ifan errorisdetectedduringa standbyoperationand clearedon exitfromthe Standby_fault 1 Rd/Wr standbystate.A writeof1 tothisbitorreceiptoftheappropriateremotecommand packetclearsitto 0.When thisbitiscleared,standbyerrorsarecleared. Disablescrambler.Ifthisbitissetto1,thenthedatasentduringpackettransmissionisnotDisscrm 1 Rd/Wr scrambled. B_Only 1 Rd Beta-mode operationonly.FortheTSB81BA3E, thisbitissetto0 forallports. Ifthisbitissetto1,theporthas detecteda dc connectiontothepeerportby means ofa 1394a-styleDC_connected 1 Rd connect-detectcircuit.

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www.ti.com SLLS783A –MAY 2009–REVISED MAY 2010 Table4.Page 0 (PortStatus)RegisterFieldDescriptions(continued) FIELD SIZE TYPE DESCRIPTION Max_port_speed The maximum speed atwhicha portisallowedtooperateinBetamode. The encodingis: 000 = S100 001 = S200 010 = S400 011 = S800 100 = S1600 101 = S3200Max_port_speed 3 Rd/Wr 110 = reserved 111 = reserved An attempttowritetotheregisterwitha valuegreaterthanthehardwarecapabilityoftheportresults inthemaximum valuethattheportiscapableofbeingstoredintheregister.The portuses this registeronlywhen a new connectionisestablishedintheBetamode orwhen a portisprogrammed as a Beta-onlyport.When a portisprogrammed as a bilingualport,itisfixedatS400 fortheBeta speed and isnotupdatedby a writetothisregister.The power resetvalueisthemaximum speed capableoftheport.Softwarecan modifythisvaluetoforcea porttotrainata lower-than-maximum speed (when ina Beta-onlymode),butno lowerthantheminimum speed. LPP(Local_plug_ 1 Rd Thisflagissetpermanentlyto1.present) Thisvariableissettothemaximum speed thattheportiscapableof.The encodingisthesame as forCable_speed 3 Rd Max_port_speed. Connection_ Ifthisbitissetto1,thena Beta-mode speed negotiationhas failedorsynchronizationhas failed.A1 Rd/Wrunreliable writeof1 tothisfieldresetsthevalueto0. OperatinginBetamode. Ifthisbitis1,theportisoperatinginBetamode; itisequalto0 otherwise Beta_mode 1 Rd (thatis,when operatingin1394a-2000mode, orwhen disconnected).IfCon is1,RxOK is1,and Beta_mode is0,thentheportisactiveand operatinginthe1394a-2000mode. Incrementedwhen theportreceivesan invalidcodeword,unlessthevalueisalready255.Cleared Port_error 8 Rd/Wr when read(includingbeingreadby means ofa remoteaccesspacket).Intendedforuse by a single bus-widediagnosticprogram. Thisbitissetto1 iftheporthas been placedintheloop-disablestateas partoftheloop-freebuild Loop_disable 1 Rd process(thePHYs ateitherend oftheconnectionareactive,butiftheconnectionitselfwere activated,thena loopwouldexist).Clearedon bus resetand on disconnection. In_standby 1 Rd Thisbitissetto1 iftheportisinstandbypower-management state. No effectunlesstheportisdisabled.Ifthisbitissetto1,theportdoes notmaintainconnectivity statuson an ac connectionwhen disabled.The valuesoftheCon and RxOK bitsareforcedto0.This Hard_disable 1 Rd/Wr flagcan be used toforcerenegotiationofthespeed ofa connection.Itcan alsobe used toplacethe deviceintoa lower-powerstatebecause when hard-disabled,a portno longertonestomaintain 1394b ac-connectivitystatus. The vendoridentificationpage identifiesthevendor/manufacturerand compliancelevel.The page isselectedby writing1 tothePage_Selectfieldinbase register7.Table5 shows theconfigurationofthevendoridentification page,and Table6 shows thecorrespondingfielddescriptions. Copyright© 2009–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLink(s):TSB81BA3E

SLLS783A –MAY 2009–REVISED MAY 2010 www.ti.com Table5.Page 1 (Vendor ID)RegisterConfiguration BIT POSITION ADDRESS 0 1 2 3 4 5 6 7

0000 Compliance

0001 Reserved

0010 Vendor_ID0

0011 Vendor_ID1

0100 Vendor_ID2

0101 Product_ID0

0110 Product_ID1

0111 Product_ID2

Table6.Page 1 (Vendor ID)RegisterFieldDescriptions FIELD SIZE TYPE DESCRIPTION Compliancelevel.FortheTSB81BA3E, thisfieldis02h,indicatingcompliancewiththe1394b-2002Compliance 8 Rd specification. Manufacturer'sorganizationallyuniqueidentifier(OUI).FortheTSB81BA3E, thisfieldis08_00_28hVendor_ID 24 Rd (TexasInstruments)(theMSB isatregisteraddress1010b). Productidentifier.FortheTSB81BA3E, thisfieldcan be either83_13_07h (theMSB isatregisterProduct_ID 24 Rd address1101b). The vendor-dependentpage providesaccess to the specialcontrolfeaturesof the TSB81BA3E, as wellas configurationand statusinformationused inmanufacturingtestand debug.Thispage isselectedby writing7 to the Page_Selectfieldinbase register7. Table 7 shows the configurationof the vendor-dependentpage and Table8 shows thecorrespondingfielddescriptions. Table7.Page 7 (Vendor-Dependent)RegisterConfiguration BIT POSITION ADDRESS 0 1 2 3 4 5 6 7

0000 Reserved Reserved

0001 Reservedfortest

0010 Reservedfortest

0011 Reservedfortest

0100 Reservedfortest

0101 Reservedfortest

0110 SWR Reservedfortest

0111 Reservedfortest

Table8.Page 7 (Vendor-Dependent)RegisterFieldDescriptions FIELD SIZE TYPE DESCRIPTION Softwarehardreset.Writinga 1 tothisbitforcesa hardresetofthePHY (same effectas momentarilySWR 1 Rd/Wr assertingtheRESET terminallow).Thisbitisalwaysreadas a 0. Power-Class Programming The PC0-PC2 terminalsare programmed to setthe defaultvalueof the power-classindicatedinthe pwr field (bits21−23) of the transmittedself-IDpacket.Descriptionsof the variouspower-classesare giveninTable 9. The defaultpower-classvalueisloadedfollowinga hardwarereset,butisoverriddenby any valuesubsequently loadedintothePwr_Classfieldinregister4.

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56 Ω56 Ω 56 Ω56 Ω 5 kΩ 1 µF 400 kΩ 270 pF (see Note A) Cable Power Pair Cable Pair A Cable Pair B Outer Shield T ermination VP VG 1 MΩ 0.1 µF 270 pF TP A_REFGND TPB_REFGND NOTE A: The IEEE Std 1394- 1995 calls for a 250-pF capacitor, which is a nonstandard component value. A 270-pF capacitor isrecommended. TSB81BA3E TSB81BA3E www.ti.com SLLS783A –MAY 2009–REVISED MAY 2010 Table9.Power-Class Descriptions PC0-PC2 DESCRIPTION

000 Node does notneed power and does notrepeatpower

001 Node isself-poweredand providesa minimum of15 W tothebus. 010 Node isself-poweredand providesa minimum of30 W tothebus. 011 Node isself-poweredand providesa minimum of45 W tothebus. Node can be powered fromthebus and isusingup to3 W; no additionalpower isneeded toenablethelink.The node100 can alsoprovidepower tothebus.The amount ofbus power thatitprovidescan be foundintheconfigurationROM. 101 Reservedforfuturestandardization. 110 Node ispowered fromthebus and uses up to3 W. An additional3 W isneeded toenablethelink. 111 Node ispowered fromthebus and uses up to3 W. An additional7 W isneeded toenablethelink. Figure4. TypicalTP Cable Connections Copyright© 2009–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLink(s):TSB81BA3E

1 MΩ 0.001 µF0.01 µF Outer Cable Shield Chassis Ground Outer Cable Shield Chassis Ground LPS LPS 10 kΩ Link Power Square-Wave Input 10 kΩ LPS 13 kΩ Square-Wave Signal 18 kΩ PHY V DD 0.033 /C0109F PHY GND TSB81BA3E SLLS783A –MAY 2009–REVISED MAY 2010 www.ti.com Figure5. TypicalDC-IsolatedOuter ShieldTermination Figure6. Non-DC-IsolatedOuter ShieldTermination Figure7. NonisolatedConnection VariationsforLPS Figure8. IsolatedCircuitConnection forLPS

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www.ti.com SLLS783A –MAY 2009–REVISED MAY 2010 DesigningWith PowerPAD ™ Devices (PFP Package Only) The TSB81BA3E ishoused ina highperformance,thermallyenhanced,80-terminalPFP PowerPAD ™ package. Use of the PowerPAD ™ package does not requireany specialconsiderationsexcept to note thatthe PowerPAD ™ , which isan exposed diepad on the bottom of the device,isa metallicthermaland electrical conductor.Therefore,ifnot implementingPowerPAD ™ PCB features,the use of soldermasks (or other assembly techniques)may be requiredto preventany inadvertentshortingby the exposed PowerPAD ™ of connectionetchesor viasunder thepackage.The recommended option,however,istonotrun any etchesor signalviasunderthedevice,buttohave onlya groundedthermallandas explainedbelow.Althoughtheactual sizeoftheexposed diepad may vary,themaximum sizerequiredforthekeepoutareaforthe80-terminalPFP PowerPAD ™ package is10 mm × 10 mm. The actualPowerPAD ™ sizefortheTSB81BA3E is6 mm × 6 mm. Itis recommended thattherebe a thermalland,which is an area of solder-tinned-copper,underneaththe PowerPAD ™ package.The thermallandvariesinsize,dependingon thePowerPAD ™ package beingused,the PCB construction,and theamount ofheatthatneeds tobe removed.Inaddition,thethermallandmay or may notcontainnumerous thermalviasdependingon PCB construction. Other requirementsforthermallands and thermalviasare detailedin the Texas InstrumentsPowerPAD ™ ThermallyEnhanced Package applicationreport(SLMA002 ) availableviathe Texas Instrumentsweb page at http://www.ti.com. Figure9. Example ofa Thermal Land fortheTSB81BA3E PHY The thermallandmust be grounded tothelow-impedanceground planeofthedevice.Thisimprovesnotonly thermalperformancebut alsothe electricalgroundingof the device.Itisalsorecommended thatthe device groundterminallandingpads be connecteddirectlytothegroundedthermalland.The landsizeoughttobe as largeas possiblewithoutshortingthedevicesignalterminals.The thermallandcan be solderedtotheexposed thermalpad usingstandardreflowsolderingtechniques. Whilethethermallandmay be electricallyfloatedand configuredtoremove heattoan externalheatsink,itis recommended thatthe thermalland be connectedto the low impedance ground plane forthe device.More informationmay be obtainedfromtheTIapplicationnotePHY Layout(SLLA020). Using theTSB81BA3E witha Non-1394b LinkLayer The TSB81BA3E implementsthePHY-LLC interfacespecifiedinthe1394b Supplement.Thisinterfaceisbased on the interfacedescribedinSection14 of IEEE P1394b (draft1.33).When usinga LLC compliantwiththis interface,theBMODE inputmust be tiedhigh. Copyright© 2009–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLink(s):TSB81BA3E

SLLS783A –MAY 2009–REVISED MAY 2010 www.ti.com The TSB81BA3E alsofunctionswitha LLC thatiscompliantwiththe older1394 standards.Thisinterfaceis compatiblewithboththeolderAnnex J interfacespecifiedintheIEEE Std 1394--1995(withtheexceptionofthe Annex J isolationinterfacingmethod) and thePHY-LLC interfacespecifiedin1394a--2000.When usinga LLC compliantwiththisinterface,theBMODE inputmust be tiedlow. Using theTSB81BA3E With a 1394-1995or 1394a-2000LinkLayer When the BMODE inputis tiedlow,the TSB81BA3E implementsthe PHY-LLC interfacespecifiedin the 1394a-2000 Supplement.Thisinterfaceisbased on theinterfacedescribedininformativeAnnex J ofIEEE Std 1394-1995,which isthe interfaceused inthe oldestTexas InstrumentsPHY devices.The PHY-LLC interface specifiedin1394a-2000 iscompatiblewiththeolderAnnex J.However, theTSB81BA3E does notsupportthe Annex J isolationinterfacingmethod.When implementingthe1394a-2000interface,certainsignalsarenotused:

The PINT output(terminal1)can be leftopen.
The LCLK_PMC input(terminal7)must be tieddirectlytogroundorthrougha pulldownresistorof~1 kΩ or less,unlessthePMC mode isdesired(seeLCLK_PMC terminaldescription). Allothersignalsare connected to theircounterpartson the 1394a link-layercontroller.The PCLK output correspondstotheSCLK inputsignalon most LLCs. The 1394a-2000 Supplement includesenhancements to the Annex J interfacethatshouldbe comprehended when usingtheTSB81BA3E witha 1394-1995LLC device.
A new LLC servicerequestwas added whichallowstheLLC totemporarilyenableand disableasynchronous arbitrationaccelerations.Ifthe LLC does not implement thisnew servicerequest,then the arbitration enhancements must notbe enabled(seetheEAA bitinPHY register5).
The capabilityto performmultispeedconcatenation(theconcatenationof packetsof differingspeeds)was added to improve bus efficiency(primarilyduringisochronoustransmission).Ifthe LLC does not support multispeedconcatenation,thenmultispeedconcatenationmust notbe enabledinthePHY (seetheEMC bit inPHY register5).
To accommodate thehighertransmissionspeeds expectedinfuturerevisionsofthestandard,1394a-2000 extendedthespeed code inbus requestsfrom2 bitsto3 bits,increasingthelengthofthebus requestfrom7 bitsto8 bits.The new speed codes were carefullyselectedso thatnew 1394a-2000 PHY and LLC devices would be compatible,forspeeds from S100 to S400, withlegacyPHY and LLC devicesthatuse the 2-bit speed codes.The TSB81BA3E correctlyinterpretsboth7-bitbus requests(with2-bitspeed code)and 8-bit bus requests(with3-bitspeed codes).Moreover,ifa 7-bitbus requestisimmediatelyfollowedby another request(forexample, a registerread or writerequest),then the TSB81BA3E correctlyinterpretsboth requests.Althoughthe TSB81BA3E correctlyinterprets8-bitbus requests,a requestwitha speed code exceedingS400 whilein1394a-2000 PHY-linkinterfacemode resultsintheTSB81BA3E transmittinga null packet(dataprefixfollowedby dataend,withno datainthepacket). Power-Up Reset To ensure properoperationof the TSB81BA3E, the RESET terminalmust be assertedlow fora minimum of 2 ms fromthetimethatPHY power reachestheminimum requiredsupplyvoltageand theinputclocktothePHY is valid.When using a passivecapacitoron the RESET terminalto generatea power-on-resetsignal,the minimum resettimeisensuredifthevalueofthecapacitorsatisfiesthefollowingequation(thevaluemust be no smallerthanapproximately0.1mF): C min = (0.0077× T)+ 0.085+ (external_oscillator_start-up_time× 0.05) where C min istheminimum capacitanceon theRESETz terminalinmF,T istheVDD ramp time,10% −90%, inms, external_oscillator_start-up_timeisthetimefrompower appliedtotheexternaloscillatortilltheoscillatoroutputs a validclockin ms. Ifa fundamentalmode crystalisused ratherthan an oscillatorthen the start−up time parametermay be settozero. CrystalSelection The TSB81BA3E isdesignedtouse an external98.304-MHz crystaloscillatorconnectedtotheXI terminalto providethereferenceclock.Thisclock,inturn,drivesa PLL circuitthatgeneratesthevariousclocksrequiredfor transmissionand resynchronizationofdataattheS100 throughS800 media datarates.

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www.ti.com SLLS783A –MAY 2009–REVISED MAY 2010 A variationoflessthan±100 ppm fromnominalforthemedia dataratesisrequiredby IEEE Std 1394.Adjacent PHYs may thereforehave a differenceofup to200 ppm fromeach otherintheirinternalclocks,and PHYs must be abletocompensate forthisdifferenceoverthemaximum packetlength.Largerclockvariationsmay cause resynchronizationoverflowsorunderflows,resultingincorruptedpacketdata. For the TSB81BA3E, the PCLK outputmay be used to measure the frequencyaccuracyand stabilityof the internaloscillatorand PLL from which itisderived.When operatingthe PHY-LLC interfacewitha non-1394b LLC, thefrequencyofthePCLK outputmust be within±100 ppm ofthenominalfrequencyof49.152MHz. When operatingthePHY-LLC interfacewitha 1394b LLC, thefrequencyofthePCLK outputmust be within±100 ppm ofthenominalfrequencyof98.304MHz. The followingaresome typicalspecificationsforan oscillatorused withtheTSB81BA3E physicallayerfromTIto achievetherequiredfrequencyaccuracyand stability:

RMS jitterof5 picosecondsorbetter
RMS phase noisejitterof1 picosecondorlessovertherange12 kHz to20 MHz orbetter
Frequencytoleranceat25°C: Totalfrequencyvariationforthecompletecircuitis±100 ppm. A devicewith ±30 ppm or±50 ppm frequencytoleranceisrecommended foradequatemargin.
Frequency stability(overtemperatureand age):A devicewith±30 ppm or ±50 ppm frequencystabilityis recommended foradequatemargin. NOTE The totalfrequencyvariationmust be kept below ±100 ppm from nominalwithsome allowancefor errorintroducedby board and device variations.Trade-offsbetween frequencytoleranceand stabilitymay be made as longas thetotalfrequencyvariationis lessthan±100 ppm. For example,thefrequencytoleranceofthecrystalmay be specified at50 ppm and thetemperaturetolerancemay be specifiedat30 ppm togivea totalof80 ppm possiblevariationdue totheoscillatoralone.Agingalsocontributestothefrequency variation. Itisstronglyrecommended thatpartoftheverificationprocessforthedesignistomeasure thefrequencyofthe PCLK outputofthePHY. Thisshouldbe done witha frequencycounterwithan accuracyof6 digitsorbetter. Bus Reset Itisrecommended, thatwhen the user has a choice,the user shouldinitiatea bus resetby writingto the initiate-short-bus-reset(ISBR)bit(bit1,PHY register0101b).Care must be takentonotchange thevalueofany oftheotherwriteablebitsinthisregisterwhen theISBR bitiswrittento. In the TSB81BA3E, the initiate-bus-reset(IBR)bitcan be set to 1 to initiatea bus resetand initialization sequence;however,itisrecommended to use the ISBR bitinstead.The IBR bitislocatedinPHY register1 along with the root-holdoffbit(RHB) and gap-countregister.As requiredby the 1394b Supplement,this configurationmaintainscompatibilitywitholderTexas InstrumentsPHY designswhichwere based on eitherthe suggestedregistersetdefinedinAnnex J of IEEE Std 1394-1995 or the 1394a-2000 Supplement.Therefore, whenever theIBR bitiswritten,theRHB and gap-countregisterarealsonecessarilywritten. Itisrecommended thatthe RHB and gap-countregisteronlybe updated by PHY configurationpackets.The TSB81BA3E is 1394a- and 1394b-compliant,and therefore,both the receptionand transmissionof PHY configurationpackets cause the RHB and gap-count registerto be loaded, unlikeolder IEEE Std 1394-1995-compliantPHYs whichdecode onlyreceivedPHY configurationpackets. The gap-countregisterissettothemaximum valueof63 aftertwo consecutivebus resetswithoutan intervening writeto the gap-countregister,eitherby a writeto PHY register1 or by a PHY configurationpacket.This mechanism allowsa PHY configurationpacketto be transmittedand then a bus resetto be initiatedso as to verifythatallnodes on the bus have updated theirRHBs and gap-countregistervalues,withouthavingthe gap-countregistersetback to63 by thebus reset.The subsequentconnectionofa new node tothebus,which initiatesa bus reset,thencauses thegap-countregisterofeach node tobe setto63.Note,however,thatifa subsequentbus resetisinsteadinitiatedby a writetoregister1 tosettheIBR bit,thenallothernodes on thebus have theirgap-countregistervaluessetto63,whilethisnode'sgap-countregisterremainssettothevaluejust loadedby thewritetoPHY register1. Copyright© 2009–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLink(s):TSB81BA3E

SLLS783A –MAY 2009–REVISED MAY 2010 www.ti.com Therefore,inordertomaintainconsistentgap-countregistersthroughoutthebus,thefollowingrulesapplytothe use oftheIBR bit,RHB, and gap-countregisterinPHY register1:

Followingthetransmissionofa PHY configurationpacket,a bus resetmust be initiatedtoverifythatallnodes have correctlyupdated theirRHBs and gap-countregistervalues,and to ensure thata subsequentnew connectiontothebus causesthegap-countregistertobe setto63 on allnodes inthebus.Ifthisbus resetis initiatedby settingtheIBR bitto1,thentheRHB and gap-countregistermust alsobe loadedwiththecorrect valuesconsistentwiththe just-transmittedPHY configurationpacket.In the TSB81BA3E, the RHB and gap-countregisterhave been updatedtotheircorrectvalueson thetransmissionofthePHY configuration packetand so thesevaluescan firstbe readfromregister1 and thenrewritten.
Otherthantoinitiatethebus reset,whichmust followthetransmissionofa PHY configurationpacket,when the IBR bitisset to 1 to initiatea bus reset,the gap-countregistervaluemust alsobe set to 63 to be consistentwithothernodes on thebus,and theRHB must be maintainedwithitscurrentvalue.
The PHY register1 must notbe writtentoexcepttosettheIBR bit.The RHB and gap-countregistermust not be writtenwithoutalsosettingtheIBR bitto1.
To avoidtheseproblems,allbus resetsinitiatedby softwaremust be initiatedby writingtheISBR bit(bit1 PHY register0101b).Care must be takentonotchange thevalueofany oftheotherwriteablebitsinthis registerwhen theISBR bitiswrittento.Also,theonlymeans tochange thegap countofany node must be by means ofthePHY configurationpacket,whichchanges allnodes tothesame gap count. PRINCIPLES OF OPERATION (1394a-2000INTERFACE) The TSB81BA3E isdesignedtooperatewithan LLC such as theTexas InstrumentsTSB12LV21B, TSB12LV26, TSB12LV32, TSB42AA4, or TSB12LV01B when the BMODE terminalistiedlow.Detailsof operationforthe Texas InstrumentsLLC devicesarefoundintherespectiveLLC datasheets.The followingparagraphsdescribe theoperationofthePHY-LLC interface.ThisinterfaceisformallydefinedinIEEE 1394a-2000,Section5A. The interfacetotheLLC consistsofthePCLK, CTL0-CTL1, D0-D7, LREQ, LPS, and LKON/DS2 terminalson theTSB81BA3E, as shown inFigure10. Figure10. PHY-LLC Interface The PCLK terminalprovidesa 49.152-MHz interfacesystem clock.Allcontroland datasignalsaresynchronized toand sampled on therisingedge ofPCLK. Thisterminalservesthesame functionas theSYSCLK terminalof 1394a-2000-compliantPHY devices. The CTL0 and CTL1 terminalsform a bidirectionalcontrolbus,which controlstheflowofinformationand data between theTSB81BA3E and LLC.

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Each cell represents one clock sample period, and n is the number of bits in the request stream. LR1 LR2 LR3 LR (n-2)LR0 LR (n-1) TSB81BA3E www.ti.com SLLS783A –MAY 2009–REVISED MAY 2010 The D0-D7 terminalsform a bidirectionaldata bus,which transfersstatusinformation,controlinformation,or packetdata between the devices.The TSB81BA3E supportsS100, S200, and S400 data transfersover the D0-D7 databus.InS100 operation,onlytheD0 and D1 terminalsareused;inS200 operation,onlytheD0-D3 terminalsareused;and inS400 operation,allD0-D7 terminalsareused fordatatransfer.When theTSB81BA3E isincontroloftheD0-D7 bus,unused Dn terminalsaredrivenlow duringS100 and S200 operations.When the LLC isincontroloftheD0-D7 bus,unused Dn terminalsareignoredby theTSB81BA3E. The LREQ terminaliscontrolledby theLLC tosend serialservicerequeststothePHY torequestaccesstothe serialbus forpackettransmission,readorwritePHY registers,orcontrolarbitrationacceleration. The LPS and LKON/DS2 terminalsare used forpower management of the PHY and LLC. The LPS terminal indicatesthepower statusoftheLLC and can be used toresetthePHY-LLC interfaceortodisablePCLK. The LKON/DS2 terminalsends a wake-up notificationtotheLLC orexternalcircuitryand indicatesan interrupttothe LLC when eitherLPS isinactiveorthePHY registerL bitis0. The TSB81BA3E normallycontrolstheCTL0-CTL1 and D0-D7 bidirectionalbuses.The LLC isallowedtodrive thesebuses onlyaftertheLLC has been grantedpermissiontodo so by thePHY. There are fouroperationsthatmay occuron thePHY-LLC interface:linkservicerequest,statustransfer,data transmit,and datareceive.The LLC issuesa servicerequesttoreadorwritea PHY register,torequestthePHY togaincontroloftheserial-businordertotransmita packet,ortocontrolarbitrationacceleration. 1. The PHY can initiatea statustransfereitherautonomouslyorinresponsetoa registerreadrequestfromthe LLC. 2. The PHY initiatesa receiveoperationwhenever a packetisreceivedfromtheserialbus. 3. The PHY initiatesa transmitoperationafterwinningcontroloftheserialbus followinga bus requestby the LLC. 4. The transmitoperationisinitiatedwhen thePHY grantscontroloftheinterfacetotheLLC. Table10 and Table11 show theencodingoftheCTL0-CTL1 bus. Table10.CTL Encoding When PHY Has ControloftheBus CTL0 CTL1 NAME DESCRIPTION 0 0 Idle No activity(thisisthedefaultmode) 0 1 Status StatusinformationisbeingsentfromthePHY totheLLC. 1 0 Receive An incomingpacketisbeingsentfromthePHY totheLLC. 1 1 Grant The LLC has been givencontrolofthebus tosend an outgoingpacket. Table11.CTL Encoding When LLC Has ControloftheBus CTL0 CTL1 NAME DESCRIPTION 0 0 Idle The LLC releasesthebus (transmissionhas been completed). The LLC isholdingthebus whiledataisbeingpreparedfortransmissionorindicatingthat0 1 Hold anotherpacketistobe transmitted(concatenated)withoutarbitrating. 1 0 Transmit An outgoingpacketisbeingsentfromtheLLC tothePHY. 1 1 Reserved None LLC ServiceRequest To requestaccess to the bus,to read or writea PHY register,or to send a linknotificationto PHY, the LLC sends a serialbitstreamon theLREQ terminalas shown inFigure11. Figure11. LREQ Request Stream Copyright© 2009–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLink(s):TSB81BA3E

SLLS783A –MAY 2009–REVISED MAY 2010 www.ti.com The lengthofthestreamvariesdependingon thetypeofrequestas shown inTable12. Table12.Request Stream BitLength REQUEST TYPE NUMBER OF BITS Bus request 7 or8 Read registerrequest 9 Writeregisterrequest 17 Accelerationcontrolrequest 6 Regardlessofthetypeofrequest,a startbitof1 isrequiredatthebeginningofthestreamand a stopbitof0 is requiredattheend ofthestream.The second throughfourthbitsoftherequeststreamindicatethetypeofthe request.Inthefollowingdescriptions,bit0 isthemost significantand istransmittedfirstintherequestbitstream. The LREQ terminalisnormallylow. Table13 shows theencodingfortherequesttype. Table13.Request Type Encoding LR1-LR3 NAME DESCRIPTION Immediatebus request.On detectionofidle,thePHY takescontrolofthebus immediatelywithout000 ImmReq arbitration. Isochronousbus request.On detectionofidle,thePHY arbitratesforthebus withoutwaitingfora001 IsoReq subactiongap. 010 PriReq Prioritybus request.The PHY arbitratesforthebus aftera subactiongap,ignoresthefairprotocol. 011 FairReq Fairbus request.The PHY arbitratesforthebus aftera subactiongap,followsthefairprotocol. 100 RdReg PHY returnsthespecifiedregistercontentsthrougha statustransfer.

101 WrReg Writetothespecifiedregister

110 AccelCtl Enableordisableasynchronousarbitrationacceleration

111 Reserved Reserved

Fora bus request,thelengthoftheLREQ bitstreamis7 or8 bitsas shown inTable14. Table14.Bus Request BIT(s) NAME DESCRIPTION

0 Startbit Indicatesthebeginningofthetransfer(always1)

1-3 Requesttype Indicatesthetypeofbus request(See Table13) Indicatesthespeed atwhichthePHY sends thedataforthisrequest(See Table15 fortheencodingof4-6 Requestspeed thisfield) 7 Stopbit Indicatestheend ofthetransfer(always0).Ifbit6 is0,thenthisbitcan be omitted. Table15 shows the3-bitrequestformatfieldused inbus requests. Table15.Bus Request Speed Encoding LR4-LR6 DATA RATE

000 S100

010 S200

100 S400

The TSB81BA3E acceptsa bus requestwithan invalidspeed code and processesthe bus requestnormally.However, duringpacket transmissionforsuch a request,the TSB81BA3E ignoresany datapresentedby theLLC and transmitsa nullpacket. Fora readregisterrequest,thelengthoftheLREQ bitstreamis9 bitsas shown inTable16.

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www.ti.com SLLS783A –MAY 2009–REVISED MAY 2010 Table16.Read RegisterRequest BIT(s) NAME DESCRIPTION 1-3 Requesttype A 100 indicatesthisisa readregisterrequest. 4-7 Address IdentifiestheaddressofthePHY registertobe read

8 Stopbit Indicatestheend ofthetransfer(always0)

Fora writeregisterrequest,thelengthoftheLREQ bitstreamis17 bitsas shown inTable17. Table17.WriteRegisterRequest BIT(s) NAME DESCRIPTION 1-3 Requesttype A 101 indicatesthisisa writeregisterrequest. 4-7 Address IdentifiestheaddressofthePHY registertobe writtento 8-15 Data Givesthedatathatistobe writtentothespecifiedregisteraddress

16 Stopbit Indicatestheend ofthetransfer(always0)

Foran accelerationcontrolrequest,thelengthoftheLREQ datastreamis6 bitsas shown inTable18. Table18.AccelerationControlRequest BIT(s) NAME DESCRIPTION 1-3 Requesttype A 110 indicatesthisisan accelerationcontrolrequest.

4 Control Asynchronousperiodarbitrationaccelerationisenabledif1 and disabledif0

5 Stopbit Indicatestheend ofthetransfer(always0)

For fairor priorityaccess,the LLC sends the bus request(FairReqor PriReq)at leastone clockafterthe PHY-LLC interfacebecomes idle.IftheCTL terminalsareassertedtothereceivestate(10b)by thePHY, then any pendingfairor priorityrequestislost(cleared).Additionally,thePHY ignoresany fairor priorityrequestsif thereceivestateisassertedwhiletheLLC issendingtherequest.The LLC can thenreissuetherequestone clockafterthenextinterfaceidle. The cyclemaster node uses a prioritybus request(PriReq)to send a cyclestartmessage. Afterreceivingor transmittinga cyclestartmessage, theLLC can issuean isochronousbus request(IsoReq).The PHY clearsan isochronousrequestonlywhen theserialbus has been won. To send an acknowledgepacket,theLLC must issuean immediatebus request(ImmReq) duringthereception ofthepacketaddressedtoit.Thisisrequiredtominimizetheidlegap between theend ofthereceivedpacket and thestartofthetransmittedacknowledgepacket.As soon as thereceivepacketends,thePHY immediately grantscontrolofthebus totheLLC. The LLC sends an acknowledgmenttothesenderunlesstheheaderCRC ofthereceivedpacketiscorrupted.Inthiscase,theLLC does nottransmitan acknowledge,butinsteadcancels thetransmitoperationand immediatelyreleasestheinterface;theLLC must notuse thisgranttosend another typeofpacket.Aftertheinterfaceisreleased,theLLC can proceedwithanotherrequest. The LLC can make onlyone bus requestata time.Once theLLC issuesany requestforbus access(ImmReq, IsoReq,FairReq,or PriReq),itcannotissueanotherbus requestuntilthe PHY indicatesthatthe bus request was lost(bus arbitrationlostand anotherpacketreceived),or won (bus arbitrationwon and the LLC granted control).The PHY ignoresnew bus requestswhilea previousbus requestispending.Allbus requestsare clearedon a bus reset. For writeregisterrequests,thePHY loadsthespecifieddataintotheaddressedregisteras soon as therequest transferiscomplete.For read registerrequests,thePHY returnsthecontentsoftheaddressedregistertothe LLC atthenextopportunitythrougha statustransfer.Ifa receivedpacketinterruptsthestatustransfer,thenthe PHY continuesto attemptthe transferof the requestedregisteruntilitissuccessful.A writeor read register requestcan be made at any time,includingwhilea bus requestispending.Once a read registerrequestis made, thePHY ignoresfurtherread registerrequestsuntiltheregistercontentsare successfullytransferredto theLLC. A bus resetdoes notcleara pendingreadregisterrequest. Copyright© 2009–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLink(s):TSB81BA3E

SLLS783A –MAY 2009–REVISED MAY 2010 www.ti.com The TSB81BA3E includesseveralarbitrationaccelerationenhancements,which allowthePHY toimprovebus performanceand throughputby reducingthe number and lengthof interpacketgaps. These enhancements include autonomous (fly-by)isochronous packet concatenation,autonomous fairand prioritypacket concatenationonto acknowledge packets,and acceleratedfairand priorityrequest arbitrationfollowing acknowledgepackets.The enhancements areenabledwhen theEAA bitinPHY register5 isset. The arbitrationaccelerationenhancements can interferewiththeabilityofthecyclemasternode totransmitthe cyclestartmessage undercertaincircumstances.The accelerationcontrolrequestisthereforeprovidedtoallow theLLC temporarilytoenableordisablethearbitrationaccelerationenhancements oftheTSB81BA3E duringthe asynchronousperiod.The LLC typicallydisablesthe enhancements when itsinternalcyclecounterrollsover, indicatingthata cycle-startmessage isimminent,and then re-enablesthe enhancements when itreceivesa cycle-startmessage. The accelerationcontrolrequestcan be made atany timeand isimmediatelyservicedby thePHY. Additionally,a bus resetorisochronousbus requestcauses theenhancements tobe re-enabled,ifthe EAA bitisset. StatusTransfer A statustransferisinitiatedby thePHY when thereisstatusinformationtobe transferredtotheLLC. The PHY waitsuntiltheinterfaceisidlebeforestartingthetransfer.The transferisinitiatedby thePHY assertingstatus (01b)on theCTL terminals,alongwiththefirsttwo bitsofstatusinformationon theD[0:1]terminals.The PHY maintainsCTL = Statusforthedurationofthestatustransfer.The PHY mightprematurelyend a statustransfer by assertingsomethingotherthanstatuson theCTL terminals.Thisoccursifa packetisreceivedbeforethe statustransfercompletes.The PHY continuestoattempttocompletethetransferuntilallstatusinformationhas been successfullytransmitted.Atleastone idlecycleoccursbetween consecutivestatustransfers. The PHY normallysends justthefirst4 bitsofstatustotheLLC. These bitsarestatusflagsthatareneeded by theLLC statemachines.The PHY sends an entire16-bitstatuspackettotheLLC aftera readregisterrequest, orwhen thePHY has pertinentinformationtosend totheLLC ortransactionlayers.The onlydefinedcondition where thePHY automaticallysends a registertotheLLC isafterself-ID,where thePHY sends thephysical-ID registerthatcontainsthenew node address.Allstatustransfersare either4 or 16 bitsunlessinterruptedby a receivedpacket.The statusflagsare consideredtohave been successfullytransmittedtotheLLC immediately on being sent,even ifa receivedpacket subsequentlyinterruptsthe statustransfer.Registercontentsare consideredtohave been successfullytransmittedonlywhen all8 bitsoftheregisterhave been sent.A status transferisretriedafterbeinginterruptedonlyifany statusflagsremaintobe sent,orifa registertransferhas not yetcompleted. Table19 shows thedefinitionofthebitsinthestatustransfer,and Figure12 shows thetiming. Table19.StatusBits BIT(s) NAME DESCRIPTION Arbitrationreset IndicatesthatthePHY has detectedthatthebus has been idleforan arbitrationresetgap time(as0 gap definedintheIEEE 1394a-2000standard).Thisbitisused by theLLC inthebusy/retrystatemachine. IndicatesthatthePHY has detectedthatthebus has been idlefora subactiongap time(asdefinedin 1 Subactiongap theIEEE 1394a-2000standard).Thisbitisused by theLLC todetectthecompletionofan isochronous cycle.

2 Bus reset IndicatesthatthePHY has enteredthebus resetstate

Indicatesthata PHY interrupteventhas occurred.An interrupteventmightbe a configurationtime-out,3 Interrupt a cable-powervoltagefallingtoolow,a statetime-out,ora portstatuschange. 4-7 Address ThisfieldholdstheaddressofthePHY registerwhose contentsarebeingtransferredtotheLLC. 8-15 Data Thisfieldholdstheregistercontents.

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(a) (b) CTL0, CTL1 SYSCLK TSB81BA3E www.ti.com SLLS783A –MAY 2009–REVISED MAY 2010 Figure12. StatusTransferTiming The sequence ofeventsfora statustransferisas follows: a. Statustransferinitiated.The PHY indicatesa statustransferby assertingstatuson theCTL linesalongwith the statusdata on the D0 and D1 lines(only2 bitsof statusare transferredper cycle).Normally(unless interruptedby a receiveoperation),a statustransferiseither2 or 8 cycleslong.A 2-cycle(4-bit)transfer occurswhen onlystatusinformationistobe sent.An 8-cycle(16-bit)transferoccurswhen registerdataisto be sentinadditiontoany statusinformation. b. Statustransferterminated.The PHY normallyterminatesa statustransferby assertingidleon theCTL lines. The PHY can alsointerrupta statustransferatany cycleby assertingreceiveon theCTL linestobegina receiveoperation.The PHY assertsatleastone idlecyclebetween consecutivestatustransfers. Receive Whenever the PHY detectsthe data-prefixstateon the serialbus,itinitiatesa receiveoperationby asserting receiveon the CTL terminalsand a logic1 on each of the D bus terminals(data-onindication).The PHY indicatesthestartofa packetby placingthespeed code (encodedas shown inTable20) on theD terminals, followedby packetdata.The PHY holdstheCTL terminalsinthereceivestateuntilthelastsymbol ofthepacket has been transferred.The PHY indicatesthe end of packetdata by assertingidleon the CTL terminals.All receivedpacketsaretransferredtotheLLC. Note thatthespeed code ispartofthePHY-LLC protocoland isnot includedinthecalculationofCRC orany otherdataprotectionmechanisms. Itispossibleforthe PHY to receivea nullpacket,which consistsof the data-prefixstateon the serialbus followedby thedata-endstate,withoutany packetdata.A nullpacketistransmittedwhenever thepacketspeed exceeds the capabilityof the receivingPHY, or whenever the LLC immediatelyreleasesthe bus without transmittingany data.Inthiscase,thePHY assertsreceiveon theCTL terminalswiththedata-onindication(all 1s) on the D bus terminals,followedby Idleon the CTL terminals,withoutany speed code or data being transferred.In allcases,in normal operation,the TSB81BA3E sends at leastone data-onindicationbefore sendingthespeed code orterminatingthereceiveoperation. The TSB81BA3E alsotransfersitsown self-IDpacket,transmittedduringtheself-IDphase ofbus initialization,to theLLC. ThispacketistransferredtotheLLC justas any otherreceivedself-IDpacket. Copyright© 2009–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLink(s):TSB81BA3E

(a) (b) FF (data-on)D0–D7 CTL0, CTL1 SYSCLK (c) (d) (e) NOTE A: SPD = Speed code, see NO TAG. d0±dn = Packet data 0010 XX (a) (b) (c) FF (data-on)D0–D7 CTL0, CTL1 SYSCLK TSB81BA3E SLLS783A –MAY 2009–REVISED MAY 2010 www.ti.com A. SPD = Speed code,see Table20 d0-dn= Packetdata Figure13. Normal Packet ReceptionTiming The sequence ofeventsfora normalpacketreceptionisas follows: a. Receive operationinitiated.The PHY indicatesa receiveoperationby assertingreceiveon the CTL lines. Normally,theinterfaceisidlewhen receiveisasserted.However,thereceiveoperationcan interrupta status transferoperationthatisinprogressso thatthe CTL linescan change from statusto receivewithoutan interveningidle. b. Data-onindication.The PHY can assertthedata-onindicationcode on theD linesforone or more cycles precedingthespeed code. c. Speed code.The PHY indicatesthespeed ofthereceivedpacketby assertinga speed code on theD lines forone cycleimmediatelyprecedingpacketdata.The linkdecodes thespeed code on thefirstreceivecycle forwhichtheD linesarenotthedata-oncode.Ifthespeed code isinvalidorindicatesa speed higherthan thatwhichthelinkiscapableofhandling,thenthelinkmust ignorethesubsequentdata. d. Receivedata.Followingthedata-onindication(ifany)and thespeed code,thePHY assertspacketdataon theD lineswithreceiveon theCTL linesfortheremainderofthereceiveoperation. e. Receiveoperationterminated.The PHY terminatesthereceiveoperationby assertingidleon theCTL lines. The PHY assertsatleastone idlecyclefollowinga receiveoperation. Figure14. NullPacket ReceptionTiming The sequence ofeventsfora nullpacketreceptionisas follows: a. Receive operationinitiated.The PHY indicatesa receiveoperationby assertingreceiveon the CTL lines. Normally,theinterfaceisidlewhen receiveisasserted.However,thereceiveoperationcan interrupta status transferoperationthatisinprogressso thatthe CTL linescan change from statusto receivewithoutan interveningidle. b. Data-onindication.The PHY assertsthedata-onindicationcode on theD linesforone ormore cycles. c. Receiveoperationterminated.The PHY terminatesthereceiveoperationby assertingidleon theCTL lines. The PHY assertsatleastone idlecyclefollowinga receiveoperation.

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www.ti.com SLLS783A –MAY 2009–REVISED MAY 2010 Table20.Receive Speed Codes D0-D7 (1) DATA RATE 00XX XXXX S100

0100 XXXX S200

11YY YYYY data-onindication (1) X = Outputas 0 by PHY, ignoredby LLC. Y = Outputas 1 by PHY, ignoredby LLC. Transmit When theLLC issuesa bus requestthroughtheLREQ terminal,thePHY arbitratestogaincontrolofthebus.If thePHY wins arbitrationfortheserialbus,thenthePHY-LLC interfacebus isgrantedtotheLLC by asserting thegrantstate(11b)on theCTL terminalsforone PCLK cycle,followedby idleforone clockcycle.The LLC then takescontrolofthebus by assertingeitheridle(00b),hold(01b)ortransmit(10b)on theCTL terminals.Unless theLLC isimmediatelyreleasingtheinterface,theLLC can asserttheidlestateforatmost one clockbeforeit must asserteitherholdor transmiton theCTL terminals.The holdstateisused by theLLC toretaincontrolof thebus whileitpreparesdatafortransmission.The LLC can assertholdforzeroor more clockcycles(thatis, theLLC need notassertholdbeforetransmit).The PHY assertsdata-prefixon theserialbus duringthistime. When theLLC isreadytosend data,theLLC assertstransmiton theCTL terminalsas wellas sendingthefirst bitsofpacketdataon theD lines.The transmitstateisheldon theCTL terminalsuntilthelastbitsofdatahave been sent.The LLC thenassertseitherholdor idleon theCTL terminalsforone clockcycleand thenasserts idleforone additionalcyclebeforereleasingthe interfacebus and puttingthe CTL and D terminalsin a high-impedancestate.The PHY thenregainscontroloftheinterfacebus. The holdstateassertedattheend-of-packettransmissionindicatestothePHY thattheLLC requeststosend anotherpacket(concatenatedpacket)withoutreleasingtheserialbus.The PHY respondstothisconcatenation requestby waitingthe requiredminimum packet separationtime and then assertinggrantas before.This functioncan be used to send a unifiedresponse aftersending an acknowledge or to send consecutive isochronouspacketsduringa singleisochronousperiod.Unlessmultispeedconcatenationisenabled,allpackets transmittedduringa singlebus ownershipmust be ofthesame speed (becausethespeed ofthepacketisset beforethe firstpacket).Ifmultispeedconcatenationisenabled(when the EMSC bitof PHY register5 isset), thentheLLC must specifythespeed code ofthenextconcatenatedpacketon theD terminalswhen itasserts holdon theCTL terminalsattheend ofa packet.The encodingforthisspeed code isthesame as thespeed code thatprecedesreceivedpacketdataas giveninTable20. Aftersendingthelastpacketforthecurrentbus ownership,theLLC releasesthebus by assertingidleon the CTL terminalsfortwo clockcycles.The PHY beginsassertingidleon theCTL terminalsone clockaftersampling idlefromthelink.Note thatwhenever theD and CTL terminalschange directionbetween thePHY and theLLC, an extraclockperiodisallowedso thatboth sidesof the interfacecan operateon registeredversionsof the interfacesignals. Copyright© 2009–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLink(s):TSB81BA3E

(g)(e)/(f)(d)(c)(b)(a) 000000 000011 dnd0, d1, . . . Link Controls CTL and D PHY High-Impedance CTL and D Outputs D0–D7 CTL0, CTL1 SYSCLK NOTE A: SPD = Speed code, see NO TAG. d0±dn = Packet data 00/SP TSB81BA3E SLLS783A –MAY 2009–REVISED MAY 2010 www.ti.com A. SPD = Speed code,see Table20 d0-dn= Packetdata Figure15. Normal Packet TransmissionTiming The sequence ofeventsfora normalpackettransmissionisas follows: a. Transmitoperationinitiated.The PHY assertsgranton theCTL linesfollowedby idletohand overcontrolof theinterfacetothelinkso thatthelinkcan transmita packet.The PHY releasescontroloftheinterface(that is,itplacesitsCTL and D outputsina high-impedancestate)followingtheidlecycle. b. Optionalidlecycle.The linkcan assertatmost one idlecycleprecedingassertionofeitherholdortransmit. Thisidlecycleisoptional;thelinkisnotrequiredtoassertidleprecedingeitherholdortransmit. c. Optionalholdcycles.The linkcan assertholdforup to47 cyclesprecedingassertionoftransmit.These hold cycle(s)areoptional;thelinkisnotrequiredtoassertholdprecedingtransmit. d. Transmitdata.When dataisreadytobe transmitted,thelinkassertstransmiton theCTL linesalongwiththe dataon theD lines. e. Transmitoperationterminated.The transmitoperationisterminatedby thelinkassertingholdoridleon the CTL lines.The linkassertsholdto indicatethatthe PHY isto retaincontrolof the serialbus inorderto transmita concatenatedpacket.The linkassertsidletoindicatethatpackettransmissioniscompleteand the PHY can releasetheserialbus.The linkthenassertsidleforone more cyclefollowingthisholdoridlecycle beforereleasingtheinterfaceand returningcontroltothePHY. f. Concatenatedpacketspeed code.IfmultispeedconcatenationisenabledinthePHY, thenthelinkassertsa speed code on theD lineswhen itassertsholdtoterminatepackettransmission.Thisspeed code indicates the transmissionspeed forthe concatenatedpacketthatisto follow.The encodingforthisconcatenated packetspeed code isthesame as theencodingforthereceivedpacketspeed code (seeTable20).The link cannotconcatenatean S100 packetontoany higher-speedpacket. g. Afterregainingcontroloftheinterface,thePHY assertsatleastone idlecyclebeforeany subsequentstatus transfer,receiveoperation,ortransmitoperation.

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(e)(d)(c)(b)(a) 000011 D0–D7 CTL0, CTL1 SYSCLK Link Controls CTL and D PHY High-Impedance CTL and D Outputs TSB81BA3E www.ti.com SLLS783A –MAY 2009–REVISED MAY 2010 Figure16. Cancelled/NullPacket Transmission The sequence ofeventsfora cancelled/nullpackettransmissionisas follows: a. Transmitoperationinitiated.PHY assertsgranton theCTL linesfollowedby idletohand overcontrolofthe interfacetothelink. b. Optionalidlecycle.The linkcan assertatmost one idlecycleprecedingassertionofhold.Thisidlecycleis optional;thelinkisnotrequiredtoassertidleprecedinghold. c. Optionalholdcycles.The linkcan assertholdforup to 47 cyclesprecedingassertionof idle.These hold cycle(s)areoptional;thelinkisnotrequiredtoassertholdprecedingidle. d. Nulltransmittermination.The nulltransmitoperationisterminatedby thelinkassertingtwo cyclesofidleon theCTL linesand thenreleasingtheinterfaceand returningcontroltothePHY. Note thatthelinkcan assert idlefora totalofthreeconsecutivecyclesifitassertstheoptionalfirstidlecyclebutdoes notasserthold.It isrecommended thatthelinkassertthreecyclesofidletocancela packettransmissionifno holdcyclesare asserted.ThisensuresthateitherthelinkorPHY controlstheinterfaceinallcycles. e. Afterregainingcontroloftheinterface,thePHY assertsatleastone idlecyclebeforeany subsequentstatus transfer,receiveoperation,ortransmitoperation. InterfaceReset and Disable The LLC controlsthestateofthePHY-LLC interfaceusingtheLPS signal.The interfacecan be placedintoa resetstate,a disabledstate,orbe made toinitializeand thenreturntonormaloperation.When theinterfaceis notoperational(whetherreset,disabled,orintheprocessofinitialization),thePHY cancelsany outstandingbus requestor registerread request,and ignoresany requestsmade viathe LREQ line.Additionally,any status informationgeneratedby the PHY isnot queued and does not cause a statustransferon restorationof the interfacetonormaloperation. The LPS signalcan be eithera levelsignalora pulsedsignal,dependingon whetherthePHY-LLC interfaceisa directconnectionor ismade acrossan isolationbarrier.When an isolationbarrierexistsbetween thePHY and LLC, the LPS signalmust be pulsed.In a directconnection,the LPS signalcan be eithera pulsedor a level signal.TimingparametersfortheLPS signalaregiveninTable21. Table21.LPS Timing Parameters SYMBOL DESCRIPTION MIN MAX UNIT tLPSL LPS lowtime(when pulsed)(1) 0.09 2.6 ms tLPSH LPS hightime(when pulsed)(1) 0.021 2.6 ms tLPS_DUTY PS dutycycle(when pulsed)(2) 20% 60% tLPS_RESET Time forPHY torecognizeLPS deassertedand resettheinterface 2.6 2.68 ms (1) The specifiedtLPSL and tLPSH timesareworst-casevaluesappropriateforoperationwiththeTSB81BA3E. These valuesarebroader thanthosespecifiedforthesame parametersinthe1394a-2000Supplement(thatis,an implementationofLPS thatmeets the requirementsof1394a-2000operatescorrectlywiththeTSB81BA3E). (2) A pulsedLPS signalmust have a dutycycle(ratiooftLPSH tocycleperiod)inthespecifiedrangetoensureproperoperationwhen using an isolationbarrieron theLPS signal(forexample,as shown inFigure8). Copyright© 2009–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLink(s):TSB81BA3E

(a) (c) (b) CTL0, CTL1 D0±D7 LREQ LPS (d) tLPS_RESET tRESTORE TSB81BA3E SLLS783A –MAY 2009–REVISED MAY 2010 www.ti.com Table21.LPS Timing Parameters (continued) SYMBOL DESCRIPTION MIN MAX UNIT tLPS_DISABLE Time forPHY torecognizeLPS deassertedand disabletheinterface 26.03 26.11 ms tRESTORE Time topermitoptionalisolationcircuitstorestoreduringan interfacereset 15 23(3) ms PHY notinlow-powerstate 60 ns tCLK_ACTIVATE Time forPCLK tobe activatedfromreassertionofLPS PHY inlow-powerstate 5.3 7.3 ms (3) The maximum valuefortRESTORE does notapplywhen thePHY-LLC interfaceisdisabled,inwhichcase an indefinitetimecan elapse beforeLPS isreasserted.Otherwise,inordertoresetbutnotdisabletheinterface,itisnecessarythattheLLC ensurethatLPS is deassertedforlessthantLPS_DISABLE . The LLC requeststhattheinterfacebe resetby deassertingtheLPS signaland terminatingallbus and request activity.When thePHY observesthatLPS has been deassertedfortLPS_RESET ,itresetstheinterface.When the interfaceisintheresetstate,thePHY setsitsCTL and D outputsinthelogic0 stateand ignoresany activityon theLREQ signal.Figure17 shows thetimingforinterfacereset. Figure17. InterfaceReset The sequence ofeventsforresettingthePHY-LLC interfaceisas follows: a. Normal operation.Interfaceisoperatingnormally,withLPS asserted,PCLK active,statusand packetdata receptionand transmissionviatheCTL and D lines,and requestactivityviatheLREQ line.InFigure17,the LPS signalisshown as a nonpulsedlevelsignal.However,itispermissibletouse a pulsedsignalforLPS in a directconnectionbetween thePHY and LLC; a pulsedsignalisrequiredwhen usingan isolationbarrier. b. LPS deasserted.The LLC deassertstheLPS signaland,within1 ms,terminatesany requestorinterfacebus activity,placesitsCTL and D outputsintothehigh-impedancestate,and drivesitsLREQ outputlow. c. Interfacereset.AftertLPS_RESET time,thePHY determinesthatLPS isinactive,terminatesany interfacebus activity,and drivesitsCTL and D outputslow.The PHY-LLC interfaceisnow intheresetstate. d. Interfacerestored.Afterthe minimum tRESTORE time,the LLC can againassertLPS active.When LPS is asserted,theinterfaceisinitializedas describedinthefollowingparagraph. IftheLLC continuestokeep theLPS signaldeasserted,itthenrequeststhattheinterfacebe disabled.The PHY disablesthe interfacewhen itobservesthatLPS has been deassertedfortLPS_DISABLE . When the interfaceis disabled,the PHY setsitsCTL and D outputsas previouslystatedforinterfacereset,but alsostopsPCLK activity.The interfaceisalsoplacedintothedisabledconditionon a hardwareresetofthePHY. Figure18 shows thetimingfortheinterfacedisable.

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(a) (c) (b) CTL0, CTL1 D0±D7 LREQ LPS tLPS_RESET (d) tLPS_DISABLE TSB81BA3E www.ti.com SLLS783A –MAY 2009–REVISED MAY 2010 When theinterfaceisdisabled,thePHY entersa low-powerstateifnone ofitsportsareactive. Figure18. InterfaceDisable The sequence ofeventsfordisablingthePHY-LLC isas follows: a. Normal operation.Interfaceisoperatingnormally,withLPS active,PCLK active,statusand packetdata receptionand transmissionviatheCTL and D lines,and requestactivityviatheLREQ line. b. LPS deasserted.The LLC deassertstheLPS signaland,within1 s,terminatesany requestorinterfacebus activity,placesitsCTL and D outputsintoa high-impedancestate,and drivesitsLREQ outputlow. c. Interfacereset.AftertLPS_RESET time,thePHY determinesthatLPS isinactive,terminatesany interfacebus activity,and drivesitsCTL and D outputslow.The PHY-LLC interfaceisnow intheresetstate. d. Interfacedisabled.Ifthe LPS signalremainsinactivefortLPS_DISABLE time,then the PHY terminatesPCLK activityby drivingthePCLK outputlow.The PHY-LLC interfaceisnow inthedisabledstate. Aftertheinterfacehas been reset,or resetand thendisabled,theinterfaceisinitializedand restoredtonormal operationwhen LPS isreassertedby theLLC. Figure19 shows thetimingforinterfaceinitialization. Copyright© 2009–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 39 ProductFolderLink(s):TSB81BA3E

ISO (high) (a) (c)(b) CTL0 D0±D7 LREQ LPS (d) tCLK_ACTIVATE CTL1

7 Cycles

SLLS783A –MAY 2009–REVISED MAY 2010 www.ti.com Figure19. InterfaceInitialization The sequence ofeventsforinitializationofthePHY-LLC isas follows: a. LPS reasserted.Aftertheinterfacehas been intheresetordisabledstateforatleasttheminimum tRESTORE time,theLLC causes theinterfacetobe initializedand restoredtonormaloperationby reassertingtheLPS signal.(InFigure19,theinterfaceisshown inthedisabledstatewithPCLK inactive.However,theinterface initializationsequence describedhereisalsoexecutediftheinterfaceismerelyresetbutnotyetdisabled.) b. PCLK activated.Iftheinterfaceisdisabled,thenthePHY reactivatesitsPCLK outputwhen itdetectsthat LPS has been reasserted.IfthePHY has entereda low-powerstate,thenittakesbetween 5.3ms and 7.3 ms forPCLK tobe restored;ifthePHY isnotina low-powerstate,thenthePCLK isrestoredwithin60 ns. The PCLK outputisa 50% dutycyclesquarewave witha frequencyof49.152MHz ±100 ppm (periodof 20.345ns).Duringthefirst7 cyclesofPCLK, thePHY continuestodrivetheCTL and D terminalslow.The LLC isalsorequiredtodriveitsCTL and D outputslow forone ofthefirst6 cyclesofPCLK butotherwiseto placeitsCTL and D outputsinthehigh-impedancestate.The LLC continuestodriveitsLREQ outputlow duringthistime. c. Receiveindicated.On theeighthPCLK cyclefollowingreassertionofLPS, thePHY assertsthereceivestate on theCTL linesand thedata-onindication(all1s)on theD linesforone ormore cycles. d. Initializationcomplete.The PHY assertsthe idlestateon the CTL linesand logic0 on the D lines.This indicatesthatthe PHY-LLC interfaceinitializationiscompleteand normal operationcan commence. The PHY now acceptsrequestsfromtheLLC viatheLREQ line. The TSB81BA3E isdesignedto operatewithan LLC such as the Texas InstrumentsTSB82AA2 when the BMODE terminalistiedhigh.Detailsof operationforthe Texas InstrumentsLLC devicesare found in the respectiveLLC data sheets.The followingparagraphsdescribethe operationof the PHY-LLC interface.This interfaceisformallyspecifiedintheIEEE 1394b-2002standard. The interfaceto the LLC consistsof the PCLK, LCLK_PMC, CTL0-CTL1, D0-D7, LREQ, PINT, LPS, and LKON/DS2 terminalson theTSB81BA3E, as shown inFigure20.

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S5_LKON LPS PCLK LREQ D0–D7 CTL0–CTL1 Link-Layer Controller TSB41BA3B LCLK_PMC PINT TSB81BA3E www.ti.com SLLS783A –MAY 2009–REVISED MAY 2010 Figure20. PHY-LLC Interface The LCLK terminalprovidesa clocksignaltothePHY. The LLC derivesthisclockfromthePCLK signaland is phase-lockedtothePCLK signal.AllLLC toPHY transfersaresynchronoustoLCLK. The PCLK terminalprovidesa 98.304-MHz interfacesystem clock.Allcontrol,data,and PHY interruptsignals aresynchronizedtotherisingedge ofPCLK. The CTL0 and CTL1 terminalsform a bidirectionalcontrolbus,which controlstheflowofinformationand data between theTSB81BA3E and LLC. The D0 −D7 terminalsform a bidirectionaldata bus,which transfersstatusinformation,controlinformation,or packetdatabetween thedevices.The TSB81BA3E supportsS400B and S800 datatransfersovertheD0 −D7 databus.InS400B and S800 operationallDn terminalsareused. The LREQ terminaliscontrolledby theLLC tosend serialservicerequeststothePHY torequestaccesstothe serial-busforpackettransmission,read or writePHY registers,or controlarbitrationacceleration.Alldata on LREQ issynchronoustoLCLK. The LPS and LKON/DS2 terminalsare used forpower management of the PHY and LLC. The LPS terminal indicatesthepower statusoftheLLC, and may be used toresetthePHY-LLC interfaceortodisablePCLK. The LKON/DS2 terminalsends a wake-up notificationtotheLLC and indicatesan interrupttotheLLC when either LPS isinactiveorthePHY registerL bitis0. The PINT terminalisused by thePHY fortheserialtransferofstatus,interrupt,and otherinformationtotheLLC. The TSB81BA3E normallycontrolstheCTL0-CTL1 and D0-D7 bidirectionalbuses.The LLC isallowedtodrive thesebuses onlyaftertheLLC has been grantedpermissiontodo so by thePHY. There are fouroperationsthatmay occuron thePHY-LLC interface:linkservicerequest,statustransfer,data transmit,and datareceive.The LLC issuesa servicerequesttoread or writea PHY registeror torequestthe PHY togaincontroloftheserial-businordertotransmita packet. The PHY may initiatea statustransfereitherautonomouslyor inresponsetoa registerread requestfrom the LLC. The PHY initiatesa receiveoperationwhen a packetisreceivedfromtheserial-bus. The PHY initiatesa transmitoperationafterwinningcontroloftheserial-busfollowinga bus-requestby theLLC. The transmitoperationisinitiatedwhen thePHY grantscontroloftheinterfacetotheLLC. Table22 and Table23 show theencodingoftheCTL0-CTL1 bus. Copyright© 2009–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 41 ProductFolderLink(s):TSB81BA3E

Each cell represents one clock sample period, and n is the number of bits in the request stream. LR1 LR2 LR3 LR (n-2)LR0 LR (n-1) TSB81BA3E SLLS783A –MAY 2009–REVISED MAY 2010 www.ti.com Table22.CTL Encoding When PHY Has ControloftheBus CTL0 CTL1 NAME DESCRIPTION 0 0 Idle No activity(thisisthedefaultmode) 0 1 Status StatusinformationisbeingsentfromthePHY totheLLC. 1 0 Receive An incomingpacketisbeingsentfromthePHY totheLLC. 1 1 Grant The LLC has been givencontrolofthebus tosend an outgoingpacket. Table23.CTL Encoding When LLC Has ControloftheBus CTL0 CTL1 NAME DESCRIPTION 0 0 Idle The LLC releasesthebus (transmissionhas been completed). 0 1 Transmit An outgoingpacketisbeingsentfromtheLLC tothePHY. 1 0 Reserved Reserved The LLC isholdingthebus whiledataisbeingpreparedfortransmission,ortheLLC issendinga 1 1 Holation requesttoarbitrateforaccesstothebus,ortheLLC isidentifyingtheend ofa subactiongap to thePHY. LLC ServiceRequest To requestaccess to the bus,to read or writea PHY register,or to send a linknotificationto PHY, the LLC sends a serialbitstreamon theLREQ terminalas shown inFigure21. Figure21. LREQ Request Stream The lengthofthestreamvariesdependingon thetypeofrequestas shown inTable24. Table24.Request Stream BitLength REQUEST TYPE NUMBER OF BITS Bus request 11 Read registerrequest 10 Writeregisterrequest 18 Linknotificationrequest 6 PHY-linkinterfaceresetrequest 6 Regardlessofthetypeofrequest,a startbitof1 isrequiredatthebeginningofthestreamand a stopbitof0 is requiredattheend ofthestream.The second throughfifthbitsoftherequeststreamindicatethetypeofthe request.InthedescriptionsinTable25,bitLR1 isthemost significantand istransmittedfirstintherequestbit stream.The LREQ terminalisnormallylow. Table25 shows theencodingfortherequesttype. Table25.Request Type Encoding LR1-LR4 NAME DESCRIPTION 0001 Immed_Req Immediaterequest.On detectionofidle,thePHY arbitratesforthebus. Nexteven request.The PHY arbitratesforthebus tosend an asynchronouspacketintheeven0010 Next_Even fairnessintervalphase. Nextodd request.The PHY arbitratesforthebus tosend an asynchronouspacketintheodd fairness0011 Next_Odd intervalphase.

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www.ti.com SLLS783A –MAY 2009–REVISED MAY 2010 Table25.Request Type Encoding (continued) LR1-LR4 NAME DESCRIPTION Currentrequest.The PHY arbitratesforthebus tosend an asynchronouspacketinthecurrent0100 Current fairnessinterval.

0101 Reserved Reserved

Isochronouseven request.The PHY arbitratesforthebus tosend an isochronouspacketintheeven0110 Isoch_Req_Even isochronousperiod. Isochronousodd request.The PHY arbitratesforthebus tosend an isochronouspacketintheodd0111 Isoch_Req_Odd isochronousperiod. 1000 Cyc_Start_Req Cyclestartrequest.The PHY arbitratesforthebus tosend a cyclestartpacket.

1001 Reserved Reserved

1010 Reg_Read Registerreadrequest.The PHY returnsthespecifiedregistercontentsthrougha statustransfer. 1011 Reg_Write Registerwriterequest.WritetothespecifiedregisterinthePHY. Isochronousphase even notification.The linkreportstothePHY that: 1100 Isoch_Phase_Even 1)A cyclestartpackethas been received. 2)The linkhas settheisochronousphase toeven. Isochronousphase odd notification.The linkreportstothePHY that: 1101 Isoch_Phase_Odd 1)A cyclestartpackethas been received. 2)The linkhas settheisochronousphase toodd. 1110 Cycle_Start_Due Cyclestartdue notification.The linkreportstothePHY thata cyclestartpacketisdue forreception.

1111 Reserved Reserved

Fora bus request,thelengthoftheLREQ bitstreamis11 bitsas shown inTable26. Table26.Bus Request BIT(s) NAME DESCRIPTION 1–4 Requesttype Indicatesthetypeofbus request(See Table25)

5 Requestformat Indicatesthepacketformattobe used forpackettransmission(See Table27)

Indicatesthespeed atwhichthelinksends thedatatothePHY (See Table28 fortheencodingofthis6–9 Requestspeed field) 10 Stopbit Indicatestheend ofthetransfer(always0).Ifbit6 is0,thenthisbitcan be omitted. Table27 shows the1-bitrequestformatfieldused inbus requests. Table27.Bus Request Format Encoding LR5 DATA RATE

0 Linkdoes notrequesteitherBetaorlegacypacketformatforbus transmission

1 LinkrequestsBetapacketformatforbus transmission

Table28 shows the4-bitrequestspeed fieldused inbus requests. Table28.TBus Request Speed Encoding LR6-LR9 DATA RATE

0000 S100

0010 S200

0011 Reserved

0100 S400

0101 Reserved

0110 S800

SLLS783A –MAY 2009–REVISED MAY 2010 www.ti.com NOTE The TSB81BA3E acceptsa bus requestwithan invalidspeed code and processesthe bus requestnormally.However, duringpacket transmissionforsuch a request,the TSB81BA3E ignoresany datapresentedby theLLC and transmitsa nullpacket. Fora readregisterrequest,thelengthoftheLREQ bitstreamis10 bitsas shown inTable29. Table29.Read RegisterRequest BIT(s) NAME DESCRIPTION 1–4 Requesttype A 1010 indicatesthisisa readregisterrequest. 5–8 Address IdentifiestheaddressofthePHY registertobe read

9 Stopbit Indicatestheend ofthetransfer(always0)

Fora writeregisterrequest,thelengthoftheLREQ bitstreamis18 bitsas shown inTable30. Table30.WriteRegisterRequest BIT(s) NAME DESCRIPTION 1–4 Requesttype A 1010 indicatesthisisa writeregisterrequest. 5–8 Address IdentifiestheaddressofthePHY registertobe writer 9–16 Data Givesthedatathatistobe writtentothespecifiedregisteraddress

17 Stopbit Indicatestheend ofthetransfer(always0)

Fora linknotificationrequest,thelengthoftheLREQ bitstreamis6 bitsas shown inTable31. Table31.LinkNotificationRequest BIT(s) NAME DESCRIPTION 1–4 Requesttype A 1100,1101,or1110 indicatesthisisa linknotificationrequest. For fairorpriorityaccess,theLLC sends a bus requestatleastone clockafterthePHY-LLC interfacebecomes idle.The PHY queues allbus requestsand can queue one requestofeach type.IftheLLC issuesa different requestofthesame type,thenthenew requestoverwritesany nonservicedrequestofthattype.On thereceipt (CTL terminalsareassertedtothereceivestate,10b)ofa packet,queued requestsarenotclearedby thePHY. The cyclemasternode uses a cyclestartrequest(Cyc_Start_Req)tosend a cyclestartmessage. Afterreceiving ortransmittinga cyclestartmessage, theLLC can issuean isochronousbus request(IsoReq).The PHY clears an isochronousrequestonlywhen theserialbus has been won. To send an acknowledge packet,the LLC must issuean immediate bus request(Immed_Req) duringthe receptionofthepacketaddressedtoit.Thisisrequiredtominimizetheidlegap between theend ofthereceived packetand the startof the transmittedacknowledge packet.As soon as the receivedpacketends,the PHY immediatelygrantscontrolofthebus totheLLC. The LLC sends an acknowledgmenttothesenderunlessthe header CRC ofthereceivedpacketiscorrupted.Inthiscase,theLLC does nottransmitan acknowledge,but insteadcancelsthetransmitoperationand releasestheinterfaceimmediately;theLLC must notuse thisgrantto send anothertypeofpacket.AftertheinterfaceisreleasedtheLLC can proceedwithanotherrequest. For writeregisterrequests,thePHY loadsthespecifieddataintotheaddressedregisteras soon as therequest transferiscomplete.For read registerrequests,thePHY returnsthecontentsoftheaddressedregistertothe LLC atthenextopportunitythrougha PHY statustransfer.A writeorreadregisterrequestcan be made atany time,includingwhilea bus requestispending.Once a read registerrequestismade, thePHY ignoresfurther read registerrequestsuntiltheregistercontentsare successfullytransferredtotheLLC. A bus resetdoes not cleara pendingreadregisterrequest.

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D[0:7] XX ST XX CTL[0:1] XX 01 XX Status Bits TSB81BA3E www.ti.com SLLS783A –MAY 2009–REVISED MAY 2010 StatusTransfer A statustransferisinitiatedby thePHY when statusinformationistobe transferredtotheLLC. Two typesof statustransferscan occur:bus statustransferand PHY statustransfer.Bus statustransferssend thefollowing statusinformation:bus resetindications,subactionand arbitrationresetgap indications,cyclestartindications, and PHY interfaceresetindications.PHY statustransferssend the followinginformation:PHY interrupt indications,unsolicitedand solicitedPHY registerdata,bus initializationindications,and PHY-linkinterfaceerror indications.The PHY uses a differentmechanism tosend thebus statustransferand thePHY statustransfer. Bus statustransfersuse theCTL0-CTL1 and D0-D7 terminalstotransferstatusinformation.Bus statustransfers can occurduringidleperiodson the PHY-linkinterfaceor duringpacketreception.When the statustransfer occurs,a singlePCLK cycleof statusinformationissentto the LLC. The informationissentsuch thateach individualDn terminalconveys a differentbus statustransferevent.Duringany bus statustransfer,onlyone statusbitisset.IfthePHY-linkinterfaceisinactive,thenthestatusinformationisnotsent.When a bus reseton theserialbus occurs,thePHY sends a bus resetindication(viatheCTLn and Dn terminals),cancelsallpacket transferrequests,setsasynchronousand isochronousphases toeven,forwardsself-IDpacketstothelink,and sends an unsolicitedPHY register0 statustransfer(viathe PINT terminal)to the LLC. In the case of a PHY interfaceresetoperation,thePHY-linkinterfaceisreseton thefollowingPCLK cycle. Table32 shows thedefinitionofthebitsduringthebus statustransferand Figure22 shows thetiming. Table32.StatusBits STATUS BIT DESCRIPTION D0 Bus reset D1 Arbitrationresetgap – odd D2 Arbitrationresetgap – even D3 Cyclestart– odd D4 Cyclestart– even D5 Subactiongap D6 PHY interfacereset D7 Reserved Figure22. Bus StatusTransferTiming PHY statustransfersuse thePINT terminaltosend statusinformationseriallytotheLLC as shown inFigure23. PHY statustransfers(see Table 33) can occur at any time duringnormal operation.The PHY uses the PHY_INTERRUPT PHY statustransferwhen requiredto interruptthe LLC due to a configurationtime-out,a cable-powerfailure,a portinterrupt,oran arbitrationtime-out.When transferringPHY registercontents,thePHY uses eitherthesolicitedor theunsolicitedregisterread statustransfer.The unsolicitedregister0 contentsare passed totheLLC onlyduringinitializationoftheserialbus.Afterany PHY-linkinterfaceinitialization,thePHY sends a PHY statustransferindicatingwhetheror not a bus resetoccurredduringthe inactiveperiodof the PHY-link interface.If the PHY receivesan illegalrequest from the LLC, then the PHY issues an INTERFACE_ERROR PHY statustransfer. Copyright© 2009–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 45 ProductFolderLink(s):TSB81BA3E

000 NOP No statusindication 5

Interruptindication:configurationtime-out,cable-powerfailure,001 PHY_INTERRUPT 5porteventinterrupt,orarbitrationstatemachine time-out.

010 PHY_REGISTER_SOL SolicitedPHY registerread 17

011 PHY_REGISTER_UNSOL UnsolicitedPHY registerread 17

100 PH_RESTORE_NO_RESET PHY-linkinterfaceinitialized;no bus resetsoccurred. 5 101 PH_RESTORE_RESET PHY-linkinterfaceinitialized;a bus resetoccurred. 5 110 INTERFACE_ERROR PHY receivedillegalrequest. 5

111 Reserved Reserved Reserved

Most PHY statustransfersare 5 bitslong.The transferconsistsofa startbit(always1),followedby a request type(seeTable33),and lastlyfollowedby a stopbit(always0).The onlyexceptioniswhen thetransferofa registercontentsoccurs.Solicitedand unsolicitedPHY registerread transfersare 17 bitslongand includethe additionalinformationoftheregisteraddressand thedatacontentsoftheregister(seeTable34). Table34.RegisterRead (Solicitedand Unsolicited)PHY StatusTransferEncoding BIT(s) NAME DESCRIPTION 1–3 Requesttype A 010 ora 011 indicatesa solicitedorunsolicitedregistercontentstransfer. 4–7 Address IdentifiestheaddressofthePHY registerwhose contentsarebeingtransferred 8–15 Data The contentsoftheregisterspecifiedinbits4 through7 When thePHY detectsthedata-prefixstateon theserialbus,itinitiatesa receiveoperationby assertingreceive on theCTL terminalsand a logic1 on each oftheD terminals(data-onindication).The PHY indicatesthestartof a packetby placingthespeed code (encodedas shown inTable35)on theD terminals,followedby packetdata. The PHY holdstheCTL terminalsinthereceivestateuntilthelastsymbol ofthepackethas been transferred. The PHY indicatesthe end of packetdata by assertingidleon the CTL terminals.Allreceivedpacketsare transferredto the LLC. Note thatthe speed code ispartof the PHY-LLC protocoland isnot includedinthe calculationofCRC orany otherdataprotectionmechanisms. The PHY can optionallysend statusinformationtotheLLC atanytimeduringthedata-onindication.Only bus statustransferinformationcan be sentduringa data-onindication.The PHY holdsthe CTL terminalsinthe statusstatefor1 PCLK cycleand modifiesthe D terminalsto the correctstatusstate.Note thatthe status transferduringthedata-onindicationdoes notneed tobe precededorfollowedby a data-onindication. Itispossibleforthe PHY to receivea nullpacket,which consistsof the data-prefixstateon the serialbus followedby thedata-endstate,withoutany packetdata.A nullpacketistransmittedwhenever thepacketspeed exceeds the capabilityof the receivingPHY, or whenever the LLC immediatelyreleasesthe bus without transmittingany data.Inthiscase,thePHY assertsreceiveon theCTL terminalswiththedata-onindication(all 1s)on theD terminals,followedby idleon theCTL terminals,withoutany speed code ordatabeingtransferred. In allcases,in normal operation,the TSB81BA3E sends at leastone data-onindicationbeforesendingthe speed code orterminatingthereceiveoperation.

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(a) (b) FF (data-on)D0–D7 CTL0, CTL1 PCLK (c) (d) (e) NOTE A: SPD = speed code, see NO TAG. d0±dn = packet data NOTE A: SPD = speed code, see NO TAG. d0±dn = packet data. STATUS = status bits, see NO TAG. 0010 XX dnd0SPD (a) (b) FF (data-on)D0–D7 CTL0, CTL1 PCLK (c) (d) (e) STATUS FF (data-on) TSB81BA3E www.ti.com SLLS783A –MAY 2009–REVISED MAY 2010 The TSB81BA3E alsotransfersitsown self-IDpacket,transmittedduringtheself-IDphase ofbus initialization,to theLLC. ThispacketittransferredtotheLLC justas any otherreceivedself-IDpacket. A. SPD = speed code,see Table35.d0-dn= packetdata Figure24. Normal Packet ReceptionTiming A. SPD = speed code,see Table35.d0-dn= packetdata.STATUS = statusbits,see Table32. Figure25. Normal Packet ReceptionTiming With OptionalBus StatusTransfer The sequence ofeventsfora normalpacketreceptionisas follows: a. Receive operationinitiated.The PHY indicatesa receiveoperationby assertingreceiveon the CTL lines. Normally,theinterfaceisidlewhen receiveisasserted.However,thereceiveoperationcan interrupta status transferoperationthatisinprogressso thatthe CTL linescan change from statusto receivewithoutan interveningidle. b. Data-onindication.The PHY can assertthedata-onindicationcode on theD linesforone or more cycles precedingthespeed code.The PHY can optionallysend a bus statustransferduringthedata-onindication forone PCLK cycle.Duringthiscycle,thePHY assertsstatus(01b)on theCTL lineswhilesendingstatus informationon theD lines. c. Speed code.The PHY indicatesthespeed ofthereceivedpacketby assertinga speed code on theD lines forone cycleimmediatelyprecedingpacketdata.The linkdecodes thespeed code on thefirstreceivecycle forwhichtheD linesarenotthedata-oncode.Ifthespeed code isinvalidorindicatesa speed higherthan thatwhichthelinkiscapableofhandling,thenthelinkmust ignorethesubsequentdata. d. Receivedata.Followingthedata-onindication(ifany)and thespeed code,thePHY assertspacketdataon theD lineswithreceiveon theCTL linesfortheremainderofthereceiveoperation. e. Receiveoperationterminated.The PHY terminatesthereceiveoperationby assertingidleon theCTL lines. The PHY assertsatleastone idlecyclefollowinga receiveoperation. Copyright© 2009–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 47 ProductFolderLink(s):TSB81BA3E

(a) (b) (c) FF (data-on)D0–D7 CTL0, CTL1 PCLK TSB81BA3E SLLS783A –MAY 2009–REVISED MAY 2010 www.ti.com Figure26. NullPacket ReceptionTiming The sequence ofeventsfora nullpacketreceptionisas follows: a. Receive operationinitiated.The PHY indicatesa receiveoperationby assertingreceiveon the CTL lines. Normally,theinterfaceisidlewhen receiveisasserted.However,thereceiveoperationcan interrupta status transferoperationthatisinprogressso thatthe CTL linescan change from statusto receivewithoutan interveningidle. b. Data-onindication.The PHY assertsthedata-onindicationcode on theD linesforone ormore cycles. c. Receiveoperationterminated.The PHY terminatesthereceiveoperationby assertingidleon theCTL lines. The PHY assertsatleastone idlecyclefollowinga receiveoperation. Table35.Receive Speed Codes and Format D0-D7 (1) DATA RATE AND FORMAT 0000 0000 S100 legacy 0000 0001 S100 Beta 0000 0100 S200 legacy 0000 0101 S200 Beta 0000 1000 S400 legacy 0000 1001 S400 Beta 0000 1101 S800 Beta 1111 1111 Data-onindication Allothers Reserved (1) Y = Outputas 1 by PHY, ignoredby LLC. X = Outputas 0 by PHY, ignoredby LLC Transmit When theLLC issuesa bus requestthroughtheLREQ terminal,thePHY arbitratestogaincontrolofthebus.If thePHY wins arbitrationfortheserialbus,thenthePHY-LLC interfacebus isgrantedtotheLLC by asserting thegrantstate(11b)on theCTL terminalsand thegranttypeon theD terminalsforone PCLK cycle,followedby idleforone clockcycle.The LLC then takescontrolof the bus by assertingeitheridle(00b),hold(11b),or transmit(01b)on theCTL terminals.IfthePHY does notdetecta holdortransmitstatewithineightPCLK cycles, thenthePHY takescontrolofthePHY-linkinterface.The holdstateisused by theLLC toretaincontrolofthe bus whileitpreparesdatafortransmission.The LLC can assertholdforzeroor more clockcycles(thatis,the LLC need notassertholdbeforetransmit).Duringtheholdstate,theLLC isexpectedtodrivetheD linesto0. The PHY assertsdata-prefixon theserialbus duringthistime. When theLLC isreadytosend data,theLLC assertstransmiton theCTL terminalsas wellas sendingthefirst bitsofpacketdataon theD lines.The transmitstateisheldon theCTL terminalsuntilthelastbitsofdatahave been sent.The LLC then assertseitherholdor idleon the CTL terminalsforone clockcycle.Ifthe holdis asserted,thentheholdisimmediatelyfollowedby one clockcycleofidle.The linkthenreleasesthePHY-link interfaceby puttingthe CTL and D terminalsina high-impedancestate.The PHY then regainscontrolof the PHY-linkinterface.

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GT = grant type LR = link request type d0−dn = packet data PHY D[0:7] PHY CTL[0:1] 00 11 00 ZZ ZZ ZZ ZZ ZZZZ

00 GT 00 ZZ ZZ ZZ ZZ ZZZZ

LLC D[0:7] LLC CTL[0:1] ZZ ZZ ZZ ZZ ZZ 11 01 0111 ZZ ZZ ZZ ZZ ZZ 00 d0 d100 PHY D[0:7] PHY CTL[0:1] ZZ ZZ ZZ ZZ ZZ 00 0000 LLC D[0:7] LLC CTL[0:1] ZZ ZZ ZZ ZZ ZZ ZZ 00 0000ZZ 01 01 11 00 ZZ ZZ ZZZZZZ dn−1 dn LR 00 ZZ ZZ ZZZZZZ TSB81BA3E www.ti.com SLLS783A –MAY 2009–REVISED MAY 2010 Figure27. TransmitPacket Timing With OptionalLinkRequest The holdstateassertedattheend ofpackettransmissionallowstheLLC tomake an additionallinkrequestfor packettransmissionand/ortonotifythePHY thatthepacketmarks theend ofa subaction.The linkrequests allowedafterpackettransmissionare listedinTable 36 (notethatthe linkrequesttypesallowedduringthis periodarea subsetofalloftheallowedtypesoflinkrequests— see Table25).The associatedspeed codes and packetformatarelistedinTable36 and Table37,respectively.IftheLLC requeststosend an additionalpacket, thenthePHY does notnecessarilyhave togranttherequest.IftheLLC isnotifyingthePHY oftheend ofa subaction,thentheLLC setsD4 duringtheholdstateattheend ofpackettransmission. Table36.LinkRequest Type Encoding During Packet Transmission D1D3 REQUEST TYPE

000 No request

001 Isoch_Req_Odd

010 Isoch_Req_Even

011 Current

100 Next_Even

101 Next_Odd

110 Cyc_Start_Req

111 Reserved

SLLS783A –MAY 2009–REVISED MAY 2010 www.ti.com Table37.inkRequest Speed Code Encoding During Packet Transmission D5D6 DATA RATE

00 S100

01 S200

10 S400

11 S800

Table38.LinkRequest Format Encoding During Packet Transmission D0 FORMAT 0 Linkdoes notrequesteitherBetaorlegacypacketformatforbus transmission. 1 LinkrequestsBetapacketformatforbus transmission. Table39.SubactionEnd NotificationEncoding During Packet Transmission D4 DESCRIPTION 0 Transmittedpacketdoes notrepresentend ofa subaction. 1 Transmittedpacketmarks theend ofa subaction. The PHY indicatesto the linkduringthe GRANT cyclewhich type of grantisbeing issued.This indication includesthe granttypeas wellas the grantspeed.The linkuses the bus grantfortransmittingthe granted packettype.The linktransmitsa grantedpackettypeonlyifitsrequesttypeexactlymatches thegrantedspeed and thegrantedformat. Table40.Format Type During Grant Cycle D0 VALUE DURING FORMATGRANT CYCLE

0 Unspecified

1 Betaformat

Table41.Grant Type Values During Grant Cycle [D1-D3]VALUE DURING REQUEST TYPEGRANT CYCLE

000 Reserved

001 Reserved

010 Isochronousgrant

011 Reserved

100 Reserved

101 Asynchronousgrant

110 Cyclestartgrant

111 Immediategrant

Table42.Speed Type Values During Grant Cycle [D5-D6]VALUE DURING SPEED TYPEGRANT CYCLE

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www.ti.com 15-Jan-2011 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TSB81BA3EIPFP ACTIVE HTQFP PFP 80 96 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Request Free Samples TSB81BA3EIZAJ ACTIVE NFBGA ZAJ 168 260 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR Request Free Samples TSB81BA3EPFP ACTIVE HTQFP PFP 80 96 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Request Free Samples TSB81BA3EZAJ ACTIVE NFBGA ZAJ 168 260 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR Request Free Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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Click to View Pricing, Inventory, Delivery & Lifecycle Information: Texas Instruments: TSB81BA3EPFP TSB81BA3EIZAJ TSB81BA3EZAJ TSB81BA3EIPFP

Product Information

TSB81BA3EIPFP specifications and overview.

Summary

IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER

Description

IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER

Source title TSB81BA3EIPFP Datasheet(PDF) - Texas Instruments

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