TSB81BA3

TSB81BA3 TI | Alldatasheet

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Technical content

Features

/C0068Data Interface to Link-Layer Controller Pin Selectable From 1394a−2000 Mode (2/4/8 Parallel Bits at 49.152 MHz) or 1394b Mode (8 Parallel Bits at 98.304 MHz) /C0068Interface to Link-Layer Controller Supports Low Cost TI Bus-Holder Isolation /C0068Interoperable With Link-Layer Controllers Using 3.3-V Supplies /C0068Interoperable With Other 1394 Physical Layers (PHYs) Using 1.8-V, 3.3-V, and 5-V Supplies /C0068Low Jitter, External Crystal Oscillator Provides Transmit and Receive Data at 100/200/400/800 Mbits/s, and Link-Layer Controller Clock at 49.152 MHz and

98.304 MHz

/C0068Separate Bias (TPBIAS) for Each Port /C0068Low Cost, High Performance 80-Pin TQFP (PFP) Thermally Enhanced Package /C0068Software Device Reset (SWR) /C0068Fail-Safe Circuitry Senses Sudden Loss of Power to the Device and Disables the Ports to Ensure That the TSB81BA3 Does Not Load the TPBIAS of Any Connected Device and Blocks any Leakage From the Port Back to Power Plane /C0068The TSB81BA3 Has a 1394a−2000 Compliant Common-Mode Noise Filter on the Incoming Bias Detect Circuit to Filter Out Cross-Talk Noise /C0068The TSB81BA3 Is Port Programmable to Force 1394a Mode to Allow Use of 1394a Connectors (1394b Signalling Must Not Be Put Across 1394a Connectors or Cables) Copyright  2002 − 2003, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited. i.LINK is a trademark of Sony Corporation. FireWire is a trademark of Apple Computer Incorporated.

/C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0044 /C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0073 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS559B − DECEMBER 2002 − REVISED OCTOBER 2003

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description

The TSB81BA3 provides the digital and analog transceiver functions needed to implement a three-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB81BA3 is designed to interface with a link-layer controller (LLC), such as the TSB82AA2, TSB12LV21, TSB12LV26, TSB12LV32, TSB42AA4, TSB42AB4, TSB12LV01B, or TSB12LV01C. It may also be connected cable port to cable port to an integrated 1394 Link + PHY layer such as the TSB43AB2. The TSB81BA3 is powered by dual supplies, a 3.3-V supply for I/O and a core voltage supply. The core voltage supply is supplied to the PLLVDD-1.8 and DVDD-1.8 terminals to the requirements in the recommended operating conditions. The PLLVDD-1.8 terminals must be separated from the DVDD-1.8 terminals, the PLLVDD-1.8 terminals are decoupled with 1 µF and smaller decoupling capacitors, and the DVDD-1.8 terminals separately decoupled with a 1 µF and smaller decoupling capacitors. The separation between DVDD-1.8 and PLLVDD-1.8 may be implemented by separate power supply rails, or by a single power supply rail, where the DVDD-1.8 and PLLVDD-1.8 are separated by a filter network to keep noise from the PLLVDD-1.8 supply. The TSB81BA3 requires an external 98.304-MHz crystal oscillator to generate a reference clock. The external clock drives an internal phase-locked loop (PLL), which generates the required reference signal. This reference signal provides the clock signals that control transmission of the outbound encoded information. A 49.152-MHz clock signal is supplied to the associated LLC for synchronization of the two devices and is used for resynchronization of the received data when operating the PHY-link interface in compliance with the IEEE 1394a−2000 standard. A 98.304-MHz clock signal is supplied to the associated LLC for synchronization of the two devices when operating the PHY-link interface in compliance with the IEEE P1394b standard. The power down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL. Data bits to be transmitted through the cable ports are received from the LLC on 2, 4, or 8 parallel paths (depending on the requested transmission speed and PHY-link interface mode of operation). They are latched (referred to as S100, S200, S400, S400B, or S800 speed, respectively) as the outbound information stream. The PHY-link interface can follow either the IEEE 1394a−2000 protocol or the IEEE 1394b−2002 protocol. When using a 1394a−2000 LLC such as the TSB12LV26, the BMODE terminal must be deasserted. The PHY-link interface then operates in accordance with the legacy 1394a−2000 standard. When using a 1394b LLC such as the TSB82AA2, the BMODE terminal must be asserted. The PHY-link interface then conforms to the P1394b standard. The cable interface can follow either the IEEE 1394a−2000 protocol or the 1394b protocol on all ports. The mode of operation is determined by the interface capabilities of the ports being connected. When any of the three ports is connected to a 1394a−2000 compliant device, the cable interface on that port operates in the 1394a−2000 data-strobe mode at a compatible S100, S200, or S400 speed. When a bilingual port is connected to a 1394b compliant node, the cable interface on that port operates per the P1394b standard at S400B or S800 speed. The TSB81BA3 automatically determines the correct cable interface connection method for the bilingual ports. NOTE: The BMODE terminal does not select the cable interface mode of operation. The BMODE terminal selects the PHY-link interface mode of operation and affects the arbitration modes on the cable. When the BMODE terminal is deasserted, BOSS arbitration is disabled. During packet reception the serial data bits are split into two-, four-, or eight-bit parallel streams (depending upon the indicated receive speed and the PHY-link interface mode of operation), resynchronized to the local system clock and sent to the associated LLC. The received data is also transmitted (repeated) on the other connected and active cable ports.

/C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0044 /C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0073 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS559B − DECEMBER 2002 − REVISED OCTOBER 2003 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description (continued) Both the twisted pair A (TPA) and the twisted pair B (TPB) cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration when connected to a 1394a−2000 compliant device. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during 1394a-mode arbitration and sets the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied twisted pair bias (TPBIAS) voltage. When connected to a 1394a−2000 compliant node, the TSB81BA3 provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. The PHY contains three independent TPBIAS circuits (one for each port). This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter capacitor of 1 µF. The line drivers in the TSB81BA3, are designed to work with external 112-Ω termination resistor networks in order to match the 110-Ω cable impedance. One termination network is required at each end of a twisted-pair cable. Each network is composed of a pair of series-connected ~56-Ω resistors. The midpoint of the pair of resistors that are connected to the TPA terminals is connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that are directly connected to the TPB terminals is coupled to ground through a parallel RC network with recommended values of 5 kΩ and 270 pF. The values of the external line-termination resistors are designed to meet the standard specifications when connected in parallel with the internal receiver circuits. A precision external resistor connected between the R0 and R1 terminals sets the driver output current, along with other internal operating currents. When the power supply of the TSB81BA3 is off while the twisted-pair cables are connected, the TSB81BA3 transmitter and receiver circuitry present a high-impedance signal to the cable that does not load the device at the other end of the cable. When the TSB81BA3 is used without one or more of the ports brought out to a connector, the twisted-pair terminals of the unused ports must be terminated for reliable operation. For each unused port, the port must be forced to the 1394a-only mode (Data-Strobe-only mode), then the TPB+ and TPB− terminals can be tied together and then pulled to ground; or the TPB+ and TPB− terminals can be connected to the suggested normal termination network. The TPA+ and TPA− terminals of an unused port can be left unconnected. The TPBIAS terminal can be connected to a 1-µF capacitor to ground or left unconnected. To operate a port as a 1394b bilingual port, the force data-strobe-only terminal for the port (DS0, DS1, or DS2) needs to be pulled to ground through a 1-kΩ resistor. The port must be operated in the 1394b bilingual mode whenever a 1394b bilingual or a 1394b beta-only connector is connected to the port. To operate the port as a 1394a-only port, the force data-strobe-only terminal (DS0, DS1, or DS2) needs to be pulled to 3.3 V V CC through a 1-kΩ resistor. The only time the port must be forced to the data-strobe-only mode is if the port is connected to a 1394a connector (either 6-pin, which is recommended, or 4-pin). This mode is provided to ensure that 1394b signalling is never sent across a 1394a cable. The TESTM, TESTW, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, the TESTM and TESTW terminals must be connected to VDD through a 1-kΩ resistor. The SE and SM terminals must be tied to ground through a 1-kΩ resistor. Three package terminals are used as inputs to set the default value for three configuration status bits in the self-ID packet. They may be pulled high through a 1-kΩ resistor or hardwired low as a function of the equipment design. The PC0, PC1, and PC2 terminals indicate the default power class status for the node (the need for power from the cable or the ability to supply power to the cable). The contender bit in the PHY register set indicates that the node is a contender either for the isochronous resource manager (IRM) or for the bus manager (BM). On the TSB81BA3, this bit may only be set by a write to the PHY register set. If a node desires to be a contender for IRM or BM, then the node software must set this bit in the PHY register set.

/C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0044 /C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0073 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS559B − DECEMBER 2002 − REVISED OCTOBER 2003

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description (continued) The LPS (link power status) terminal works with the LKON/DS2 terminal to manage the power usage in the node. The LPS signal from the LLC is used in conjunction with the LCtrl bit (see Table 1 and Table 2 in the APPLICATION INFORMATION section) to indicate the active/power status of the LLC. The LPS signal also resets, disables, and initializes the PHY-LLC interface (the state of the PHY-LCC interface is controlled solely by the LPS input regardless of the state of the LCtrl bit). The LPS input is considered inactive if it remains low for more than the LPS_RESET time (see the LPS terminal definition) and is considered active otherwise. When the TSB81BA3 detects that the LPS input is inactive, the PHY-LLC interface is placed into a low-power reset state in which the CTL and D outputs are held in the logic 0 state and the LREQ input is ignored; however, the PCLK output remains active. If the LPS input remains low for more than the LPS_DISABLE time (see the LPS terminal definition), then the PHY-LLC interface is put into a low-power disabled state in which the PCLK output is also held inactive. The TSB81BA3 continues the necessary repeater functions required for normal network operation regardless of the state of the PHY-LLC interface. When the interface is in the reset or disabled state and the LPS input is again observed active, the PHY initializes the interface and returns to normal operation. The PHY-LLC interface is also held in the disabled state during hardware reset. When the LPS terminal is returned to an active state after being sensed as having entered the LPS_DISABLE time, the TSB81BA3 issues a bus reset. This broadcasts the node self-ID packet, which contains the updated L bit state (the PHY LLC now being accessible). The PHY uses the LKON/DS2 terminal to notify the LLC to power up and become active. When activated, the output LKON/DS2 signal is a square wave. The PHY activates the LKON/DS2 output when the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet addressed to this node is received, or conditionally when a PHY interrupt occurs. The PHY deasserts the LKON/DS2 output when the LLC becomes active (both LPS sensed as active and the LCtrl bit set to 1). The PHY also deasserts the LKON/DS2 output when a bus reset occurs, unless a PHY interrupt condition exists which would otherwise cause LKON/DS2 to be active. If the PHY is power cycled and the power class is 0 through 4, then the PHY asserts LKON/DS2 for approximately 167 µs or until both the LPS is active and the LCtrl bit is 1.

/C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0044 /C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0073 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS559B − DECEMBER 2002 − REVISED OCTOBER 2003 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 pin assignments AGND AVDD−3.3 DGND DVDD−1.8 SM SE CPS DS0 DS1 PLLVDD−3.3 PLLVDD−1.8 PLLVDD−1.8 PLLGND XI RSVD PLLGND AVDD−3.3 AGND AGND AGND AVDD−3.3 DGND DVDD−1.8 PC0 PC1 PC2 DVDD−3.3 DVDD−3.3 DVDD−1.8 DGND TESTW BMODE RESETz DGND PD TESTM CNA LPS 5678 PFP PACKAGE (TOP VIEW) TPB1+ 59 58 57 56 5560 54 TPA2+ TPA2− TPB2+ TPB2− TPBIAS1 TPA1+ LREQ DGND PCLK DVDD−3.3 LCLK DVDD−1.8 52 51 5053 9 10 11 12 13 49 48 1PINT TPBIAS0 47 46 45 44 14 15 16 17 DGND TPA0+ TPA0− TPBIAS2 DVDD−3.3 18 19 20 TPB0+ TPB0− 43 42 41 TPA1− TPB1− AGND CTL1 LKON/DS2 AVDD−3.3 TSB81BA3 CTL0 AVDD−3.3 AVDD−3.3 AGND

/C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0044 /C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0073 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS559B − DECEMBER 2002 − REVISED OCTOBER 2003

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TPA2− TPB2+ TPB2− TPA1+ TPA1− TPB1+ TPB1− TPB0+ TPB0− Bilingual Cable Port 0 Bilingual Cable Port 1 Bilingual Cable Port 2 CPS LPS CNA PINT LCLK LREQ CTL0 CTL1 RESETz LKON/DS2 PD BMODE Link Interface I/O Received Data Decoder/Retimer Arbitration and Control State Machine Logic Transmit Data Encoder Crystal Oscillator, PLL System, and Transmit Clock Generator PCLK PC0 PC1 PC2 SE SM DS0 DS1 TESTM TESTW Voltage Regulator XI TPA0+ TPA0− Bias Voltage and Current Generator TPBIAS0 TPBIAS1 TPBIAS2

/C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0044 /C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0073 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS559B − DECEMBER 2002 − REVISED OCTOBER 2003 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL I/O DESCRIPTIONNAME TYPE NO. I/O DESCRIPTION AGND Supply 21, 40, 43, 50, 61, 62 − Analog circuit ground terminals. These terminals must be tied together to the low-impedance circuit board ground plane. AVDD−3.3 Supply 24, 39, 44, 51, 57, 63 − Analog circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal are suggested, such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering capacitors are also recommended. These supply terminals are separated from the PLLVDD-1.8, PLLVDD-3.3, DVDD-1.8, and DVDD-3.3 terminals internal to the device to provide noise isolation. The PLLVDD-3.3, AVDD-3.3, and DVDD-3.3 terminals must be tied together with a low dc impedance connection on the circuit board. BMODE CMOS 74 I Beta-mode input. This terminal determines the PHY-link interface connection protocol. When logic high (asserted), the PHY-link interface complies with the P1394b revision 1.33 standard B PHY-link interface. When logic low (deassered), the PHY-link interface complies with the legacy 1394a−2000 standard. When using a LLC such as the 1394b TSB82AA2, this terminal must be pulled high. When using a LLC such as the 1394a−2000 TSB12LV26, this terminal must be tied low. NOTE: The PHY-link interface cannot be changed between the different protocols during operation. CNA CMOS 79 O Cable not active output. This terminal is asserted high when there are no ports receiving incoming bias voltage. When any port receives bias, this terminal goes low. CPS CMOS 34 I Cable power status input. This terminal is normally connected to cable power through a 400-kΩ resistor. This circuit drives an internal comparator that detects the presence of cable power. This transition from cable power sensed to cable power not sensed may be used to generate an interrupt to the LLC. CTL0 CTL1 CMOS 9 I/O Control I/Os. These bidirectional signals control communication between the TSB81BA3 and the LLC. Bus holders are built into these terminals. D0−D7 CMOS 11, 12, 13, 15, 16, 17, 19, 20 I/O Data I/Os. These are bidirectional data signals between the TSB82BA3 and the LLC. Bus holders are built into these terminals. DGND Supply 4, 14, 38, 64, 72, 76 Digital circuit ground terminals. These terminals must be tied together to the low-impedance circuit board ground plane. DS0 CMOS 33 I Data-strobe-only mode for port 0. 1394a-only port 0 enable programming terminal. On hardware reset, this terminal allows the user to select whether port 0 acts like a 1394b bilingual port (terminal at logic 0) or as a 1394a−2000-only port (terminal at logic 1). Programming is accomplished by tying the terminal low through a 1-kΩ or less resistor (to enable 1394b bilingual mode) or high through a 1-kΩ or less resistor (to enable 1394a−2000-only mode). A bus holder is built into this terminal. DS1 CMOS 32 I Data-strobe-only mode for port 1. 1394a-only port 1 enable programming terminal. On hardware reset, this terminal allows the user to select whether port 1 acts like a 1394b bilingual port (terminal at logic 0) or as a 1394a−2000-only port (terminal at logic 1). Programming is accomplished by tying the terminal low through a 1-kΩ or less resistor (to enable 1394b bilingual mode) or high through a 1-kΩ or less resistor (to enable 1394a−2000-only mode). A bus holder is built into this terminal. DVDD-1.8 Supply 8, 37, 65, − Digital 1.8-V circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal are suggested, such as paralleled 0.1 µF and 0.001 µF. An additional 1-µF capacitor is required for voltage regulation. These supply terminals are separated from the DVDD-3.3, PLLVDD-1.8, PLLVDD-3.3, and AVDD-3.3 terminals internal to the device to provide noise isolation. DVDD-3.3 Supply 6, 18, 69, − Digital 3.3-V circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal are suggested, such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering capacitors are also recommended. The DVDD-3.3 terminals must be tied together at a low-impedance point on the circuit board. These supply terminals are separated from the PLLVDD-1.8, PLLVDD-3.3, DVDD-1.8, and AVDD-3.3 terminals internal to the device to provide noise isolation. The PLLVDD-3.3, AVDD-3.3, and DVDD-3.3 terminals must be tied together with a low dc impedance connection on the circuit board. LCLK CMOS 7 I Link clock. Link-provided 98.304-MHz clock signal to synchronize data transfers from link to the PHY when the PHY-link interface is in the 1394b mode. A bus holder is built into this terminal.

/C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0044 /C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0073 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS559B − DECEMBER 2002 − REVISED OCTOBER 2003

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions (Continued) TERMINAL I/O DESCRIPTIONNAME TYPE NO. I/O DESCRIPTION LKON/DS2 CMOS 2 I/O Link-on output/Data-strobe-only input for port 2. This terminal may be connected to the link-on input terminal of the LLC through a 1-kΩ resistor if the link-on input is available on the link layer. Data-strobe-only mode for port 2. 1394a-only port 0 enable programming terminal. On hardware re- set, this terminal allows the user to select whether port 2 acts like a 1394b bilingual port (terminal at logic 0) or as a 1394a−2000-only port (terminal at logic 1). Programming is accomplished by tying the terminal low through a 1-kΩ or less resistor to enable 1394b bilingual mode or high through a 1-kΩ or less resistor to enable 1394a−2000-only mode. A bus holder is built into this terminal After hardware reset, this terminal is the link-on output, which notifies the LLC or other power-up logic to power up and become active. The link-on output is a square wave signal with a period of approxi- mately 163 ns (8 PCLK cycles) when active. The link-on output is otherwise driven low, except during hardware reset when it is high impedance. The link-on output is activated if the LLC is inactive (the LPS input inactive or the LCtrl bit cleared) and when one: a) The PHY receives a link-on PHY packet addressed to this node b) The PEI (port-event interrupt) register bit is 1, or c) Any of the CTOI (configuration-timeout interrupt), CPSI (cable-power-status interrupt), or STOI (state-timeout interrupt) register bits are 1 and the RPIE (resuming-port interrupt enable) register bit is also 1. d) The PHY is power cycled and the power class is 0 through 4 Once activated, the link-on output is active until the LLC becomes active (both the LPS input active and the LCtrl bit set). The PHY also deasserts the link-on output when a bus-reset occurs unless the link-on output is otherwise active because one of the interrupt bits is set (that is, the link-on output is active due solely to the reception of a link-on PHY packet). In the case of power cycling the PHY, the LKON signal must stop after 167 µs if the above conditions have not been met. NOTE: If an interrupt condition exists which otherwise causes the link-on output to be activated if the LLC were inactive, then the link-on output is activated when the LLC subsequently becomes inactive. LPS CMOS 80 I Link power status input. This terminal monitors the active/power status of the link-layer controller (LLC) and controls the state of the PHY-LLC interface. This terminal must be connected to either the VDD supplying the LLC through an approximately 1-kΩ resistor or to a pulsed output which is active when the LLC is powered. A pulsed signal must be used when an isolation barrier exists between the LLC and PHY (see Figure 8). The LPS input is considered inactive if it is sampled low by the PHY for more than a LPS_RESET time (~2.6 µs), and is considered active otherwise (that is, asserted steady high or an oscillating signal with a low time less than 2.6 µs). The LPS input must be high for at least 22 ns to be guaranteed to be observed as high by the PHY. When the TSB81BA3 detects that the LPS input is inactive, it places the PHY-LLC interface into a low-power reset state. In the reset state, the CTL (CTL0 and CTL1) and D (D0 to D7) outputs are held in the logic 0 state and the LREQ input is ignored; however, the PCLK output remains active. If the LPS input remains low for more than a LPS_DISABLE time (~26 µs), then the PHY-LLC interface is put into a low-power disabled state in which the PCLK output is also held inactive. The PHY-LLC interface is placed into the disabled state upon hardware reset. The LLC state that is communicated in the self-ID packet is considered active only if both the LPS input is active and the LCtrl register bit is set to 1. The LLC state that is communicated in the self-ID packet is considered inactive if either the LPS input is inactive or the LCtrl register bit is cleared to 0. LREQ CMOS 3 I LLC request input. The LLC uses this input to initiate a service request to the TSB81BA3. A bus holder is built into this terminal. PC0 PC1 PC2 CMOS 66 I Power class programming inputs. On hardware reset, these inputs set the default value of the power class indicated during self-ID. Programming is done by tying the terminals high through a 1-kΩ or smaller resistor or by tying directly to ground through a 1-kΩ or smaller resistor. Bus holders are built into these terminals.

/C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0044 /C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0073 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS559B − DECEMBER 2002 − REVISED OCTOBER 2003 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) TERMINAL I/O DESCRIPTIONNAME TYPE NO. I/O DESCRIPTION PCLK CMOS 5 O PHY clock. Provides a 98.304-MHz clock signal, synchronized with data transfers, to the LLC when the PHY-link interface is operating in the 1394b mode (BMODE asserted). PCLK output provides a 49.152-MHz clock signal, synchronized with data transfers, to the LLC when the PHY-link interface is in legacy 1394a−2000 (BMODE input deasserted). PD CMOS 77 I Power-down input. A high on this terminal turns off all internal circuitry except the cable-active monitor circuits, which control the CNA output. Asserting the PD input high also activates an internal pulldown on the RESETz terminal to force a reset of the internal control logic. PINT CMOS 1 O PHY Interrupt. The PHY uses this output to serially transfer status and interrupt information to the link when PHY-link interface is in the 1394b mode. A bus holder is built into this terminal. PLLGND Supply 25, − PLL circuit ground terminals. These terminals must be tied together to the low-impedance circuit board ground plane. PLLVDD-1.8 Supply 29, − PLL 1.8-V circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal are suggested, such as paralleled 0.1 µF and 0.001 µF. An additional 1-µF capacitor is required for voltage regulation, and the PLLVDD-1.8 terminals must be separate from the DVDD-1.8 terminals. These supply terminals are separated from the DVDD-1.8, DVDD-3.3, PLLVDD-3.3 and AVDD-3.3 terminals internal to the device to provide noise isolation. PLLVDD-3.3 Supply 31 − PLL 3.3-V circuit power terminal. A combination of high-frequency decoupling capacitors near the terminal are suggested, such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering capacitors are also recommended. This supply terminal is separated from the DVDD-1.8, DVDD-3.3, PLLVDD-1.8, and AVDD-3.3 terminals internal to the device to provide noise isolation. The DVDD-3.3 terminals must be tied together at a low-impedance point on the circuit board. The PLLVDD-3.3, AVDD-3.3, and DVDD-3.3 terminals must be tied together with a low dc impedance connection. RESETz CMOS 75 I Logic reset input. Asserting this terminal low resets the internal logic. An internal pullup resistor to VDD is provided so only an external delay capacitor is required for proper power-up operation (see power-up reset in the APPLICATIONS INFORMATION section). The RESETz terminal also incorporates an internal pulldown which is activated when the PD input is asserted high. This input is otherwise a standard logic input, and can also be driven by an open-drain type driver. RSVD 26 O This terminal must normally be left unconnected. When this terminal is probed, the terminal will show a 98.304-MHz signal. If this is perceived as an EMI problem, then the terminal may be pulled to ground through a 10-kΩ resistor. However, this causes an increase of up to 340 µA in device current consumption. Bias 23 − Current setting resistor terminals. These terminals are connected to a precision external resistance to set the internal operating currents and cable driver output currents. A resistance of 6.34 kΩ ±1% is required to meet the IEEE Std 1394−1995 output voltage limits. SE CMOS 35 I Test control input. This input is used in the manufacturing test of the TSB81BA3. For normal use this terminal must be pulled low either through a 1-kΩ resistor to GND or directly to GND. SM CMOS 36 I Test control input. This input is used in the manufacturing test of the TSB81BA3. For normal use this terminal must be pulled low either through a 1-kΩ resistor to GND or directly to GND. TESTM CMOS 78 I Test control input. This input is used in the manufacturing test of the TSB81BA3. For normal use this terminal must be pulled high through a 1-kΩ resistor to VDD . TESTW CMOS 73 I Test control input. This input is used in the manufacturing test of the TSB81BA3. For normal use this terminal must be pulled high through a 1-kΩ resistor to VDD . TPA0− TPA0+ TPB0− TPB0+ Cable 45, 46, 41, I/O Port 0 twisted-pair differential-signal terminals. Board traces from each pair of positive and negative differential signal terminals must be kept matched and as short as possible to the external load resistors and to the cable connector. Please request the S800 1394b layout recommendations document from your TI representative. TPA1− TPA1+ TPB1− TPB1+ Cable 52 I/O Port 1 twisted-pair differential-signal terminals. Board traces from each pair of positive and negative differential signal terminals must be kept matched and as short as possible to the external load resistors and to the cable connector. Please request the S800 1394b layout recommendations document from your TI representative.

/C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0044 /C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0073 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS559B − DECEMBER 2002 − REVISED OCTOBER 2003

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions (Continued) TERMINAL I/O DESCRIPTIONNAME TYPE NO. I/O DESCRIPTION TPA2− TPA2+ TPB2− TPB2+ Cable 58 I/O Port 2 twisted-pair differential-signal terminals. Board traces from each pair of positive and negative differential signal terminals must be kept matched and as short as possible to the external load resistors and to the cable connector. Please request the S800 1394b layout recommendations document from your TI representative. TPBIAS0 TPBIAS1 TPBIAS2 Cable 47 I/O Twisted-pair bias output. This provides the 1.86-V nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receivers, and for signaling to the remote nodes that there is an active cable connection in 1394a−2000 mode. Each of these terminals, except for an unused port, must be decoupled with a 1.0-µF capacitor to ground. For the unused port, this terminal can be left unconnected. Please request the S800 1394b layout recommendations document from your TI representative. XI Osc In 27 − Oscillator input. This terminal connects to a 98.304-MHz low jitter external oscillator. The XI terminal is a 1.8-V CMOS input. Oscillator jitter must be 5 ps RMS or better. If only 3.3-V oscillators can be acquired, then great care must be taken to not introduce significant jitter by the means used to level shift from 3.3 V to 1.8 V. If a resistor divider is used, then a high current oscillator and low-value resistors must be used to minimize RC time constants. If a level-shifting circuit is used, then it must introduce very little jitter. Please see layout recommendations document. absolute maximum ratings over operating free-air temperature (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values, except differential I/O bus voltages, are with respect to network ground. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ‡ ABOVE T A = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING PFP § 5.05 W 52.5 mW/°C 2.69 W 1.9 W PFP ¶ 3.05 W 31.7 mW/°C 1.62 W 1.15 W PFP # 2.01 W 20.3 mW/°C 1.1 W 792 mW ‡ This is the inverse of the traditional junction-to-ambient thermal resistance (RθJA). § 2 oz. trace and copper pad with solder. ¶ 2 oz. trace and copper pad without solder. # For more information, refer to TI application note PowerPAD  Thermally Enhanced Package, (SLMA002). PowerPAD is a trademark of Texas Instruments.

/C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0044 /C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0073 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS559B − DECEMBER 2002 − REVISED OCTOBER 2003 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions MIN TYP † MAX UNIT Supply voltage, 3.3 VDD Source power node 3.0 3.3 3.6 VSupply voltage, 3.3 VDD Nonsource power node 3.0‡ 3.3 3.6 V Supply voltage, 1.8 VDD 1.85 1.95 2.05 V LREQ, CTL0, CTL1, D0−D7, LCLK 2.6 High-level input voltage, VIH LKON/DS2, PC0, PC1, PC2, PD, BMODE 0.7×VDD VHigh-level input voltage, VIH RESETz 0.6×VDD V LREQ, CTL0, CTL1, D0−D7, LCLK 1.2 V Low-level input voltage, VIL LKON/DS2, PC0, PC1, PC2, PD, BMODE 0.2×VDDLow-level input voltage, VIL RESETz 0.3×VDD Output current, IOL/OH CTL0, CTL1, D0−D7, CNA, LKON/DS2, PINT, and PCLK −4 4 mA Output current, IO TPBIAS outputs −5.6 1.3 mA R JA = 19°C/W TA = 70°C 84.1 Maximum junction temperature, T R θJA = 19°C/W TA = 85°C 99.1 Maximum junction temperature, TJ (see RθJA values listed in thermal R JA = 31.5 /C0095C/W TA = 70°C 93.3 J (see RθJA values listed in thermal characteristics table) R θJA = 31.5 /C0095C/W TA = 85°C 108.4 °C characteristics table) R JA = 49.2 /C0095C/W TA = 70°C 106.4 R θJA = 49.2 /C0095C/W TA = 85°C 121.5 1394b Differential input voltage, VID Cable inputs, during data reception 200 800 mV 1394a Differential input voltage, VID Cable inputs, during data reception 118 260 mV1394a Differential input voltage, VID Cable inputs, during arbitration 168 265 mV 1394a Common-mode input voltage, VIC TPB cable inputs, source power node 0.4706 2.515 V1394a Common-mode input voltage, VIC TPB cable inputs, nonsource power node 0.4706 2.015‡ V Power-up reset time, tpu RESETz input 2§ ms TPA, TPB cable inputs, S100 operation ±1.08 Receive input jitter TPA, TPB cable inputs, S200 operation ±0.5 nsReceive input jitter TPA, TPB cable inputs, S400 operation ±0.315 ns Between TPA and TPB cable inputs, S100 operation ±0.8 Receive input skew Between TPA and TPB cable inputs, S200 operation ±0.55 nsReceive input skew Between TPA and TPB cable inputs, S400 operation ±0.5 ns † All typical values are at VDD = 3.3 V and TA = 25°C. ‡ For a node that does not source power; see Section 4.2.2.2 in IEEE 1394a−2000. § Time after valid clock received at PHY XI input terminal.

/C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0044 /C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0073 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS559B − DECEMBER 2002 − REVISED OCTOBER 2003

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of operating conditions (unless otherwise noted) driver PARAMETER TEST CONDITION MIN TYP MAX UNIT VOD Differential output voltage 56 Ω, See Figure 1 172 265 mV IDIFF Driver difference current, TPA+, TPA−, TPB+, TPB−Drivers enabled, speed signaling off−1.05† 1.05† mA ISP200 Common-mode speed signaling current, TPB+, TPB−S200 speed signaling enabled −4.84‡ −2.53‡ mA ISP400 Common-mode speed signaling current, TPB+, TPB−S400 speed signaling enabled −12.4‡ −8.10‡ mA VOFF Off state differential voltage Drivers disabled, See Figure 1 20 mV † Limits defined as algebraic sum of TPA+ and TPA− driver currents. Limits also apply to TPB+ and TPB− algebraic sum of driver currents. ‡ Limits defined as absolute limit of each of TPB+ and TPB− driver currents. receiver PARAMETER TEST CONDITION MIN TYP MAX UNIT ZID Differential impedance Drivers disabled 4 7 kΩ ZID Differential impedance Drivers disabled 4 pF ZIC Common-mode impedance Drivers disabled 20 kΩ ZIC Common-mode impedance Drivers disabled 24 pF VTH−R Receiver input threshold voltage Drivers disabled −30 30 mV VTH−CB Cable bias detect threshold, TPBx cable inputsDrivers disabled 0.6 1.0 V VTH + Positive arbitration comparator threshold voltageDrivers disabled 89 168 mV VTH − Negative arbitration comparator threshold voltageDrivers disabled −168 −89 mV VTH−SP200 Speed signal threshold TPBIAS−TPA common mode voltage, drivers disabled 49 131 mV VTH−SP400 Speed signal threshold TPBIAS−TPA common mode voltage, drivers disabled 314 396 mV device PARAMETER TEST CONDITION MIN TYP MAX UNIT IDD Supply current 3.3 VDD See Note 2 120 mAIDD Supply current 1.8 VDD See Note 2 79 mA VTH Power status threshold, CPS input† 400-kΩ resistor† 4.7 7.5 V VOH High-level output voltage, CTL0, CTL1, D0−D7, CNA, LKON/DS2, PCLK outputs VDD = 3 to 3.6 V, IOH = −4 mA 2.8 V VOL Low-level output voltage, CTL0, CTL1, D0−D7, CNA, LKON/DS2, PCLK outputs IOL = 4 mA 0.4 V IBH+ Positive peak bus holder current, D0−D7, CTL0−CTL1, LREQVDD = 3.6 V, VI = 0 V to VDD 0.05 1 mA IBH− Negative peak bus holder current, D0−D7, CTL0−CTL1, LREQVDD = 3.6 V, VI = 0 V to VDD −1.0 −0.05 mA IOZ Off-state output current, CTL0, CTL1, D0−D7, LKON/DS2 I/OsVO = VDD or 0 V ±5 µA IIRST Pullup current, RESETz input VI = 1.5 V or 0 V −90 −20 µA VO TPBIAS output voltage At rated IO current 1.665 2.015 V † Measured at cable power side of resistor. ‡ This parameter applicable only when ISO low. NOTE 2: Repeat Max Packet (1 port receiving maximum size isochronous packet—8192 bytes, sent on every isochronous interval, s800, data value of 0xCCCCCCCCh; 2 ports repeating; all ports with beta-mode connection), VDD3.3 = 3.3 V, VDD1.8 = 1.95 V, TA = 25/C0095C

or grease thermal connection to thermal land with 2 oz. Figure 1. Test Load Diagram

/C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0044 /C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0073 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS559B − DECEMBER 2002 − REVISED OCTOBER 2003

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION thtsu D, CTL, LREQ xCLK Figure 2. Dx, CTLx, LREQ Input Setup and Hold Time Waveforms Figure 3. Dx and CTLx Output Delay Relative to xCLK Waveforms

APPLICATION INFORMATION

Please obtain from the TI website or your local TI representative the reference schematics, reference layouts, debug documents, and software recommendations for the TSB81BA3. internal register configuration There are 16 accessible internal registers in the TSB81BA3. The configuration of the registers at addresses 0h through 7h (the base registers) is fixed, while the configuration of the registers at addresses 8h through Fh (the paged registers) is dependent upon which 1 of 8 pages, numbered 0h through 7h, is currently selected. The selected page is set in base register 7h. Note that while this register set is compatible with 1394a−2000 register sets, some fields have been redefined and this register set contains additional fields. Table 1 shows the configuration of the base registers, and Table 2 gives the corresponding field descriptions. The base register field definitions are unaffected by the selected page number. A reserved register or register field (marked as Reserved or Rsvd in the following register configuration tables) is read as 0, but is subject to future usage. All registers in address pages 2 through 6 are reserved.

/C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0044 /C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0073 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS559B − DECEMBER 2002 − REVISED OCTOBER 2003 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Table 1. Base Register Configuration

0000 Physical ID R CPS

0001 RHB IBR Gap_Count

0010 Extended (111b) Num_Ports (0011b)

0011 PHY_Speed (111b) Rsvd Delay (0000b)

0100 LCtrl C Jitter (000b) Pwr_Class

0101 WDIE ISBR CTOI CPSI STOI PEI EAA EMC

0110 Max Legacy SPD BLINK Bridge Rsvd

0111 Page_Select Rsvd Port_Select

Table 2. Base Register Field Descriptions tree-ID if this node becomes root. dropped below its threshold for ensured reliable operation. written using a PHY configuration packet. be changed using PHY configuration packets. PHYs must be checked on a port-by-port basis. 144+(delay × 20) ns. For the TSB81BA3 this field is 0.

/C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0044 /C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0073 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS559B − DECEMBER 2002 − REVISED OCTOBER 2003

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Table 2. Base Register Field Descriptions (Continued) LCtrl 1 Rd/Wr Link-active status control. This bit controls the indicated active status of the LLC reported in the self-ID packet. LLC bit in the node self-ID packet is set active only if both the LPS input is active and the LCtrl bit is set. The LCtrl bit is set to 1 by hardware reset and is unaffected by bus-reset. LREQ input are processed, even if the LCtrl bit is cleared to 0. C 1 Rd/Wr Contender status. This bit indicates that this node is a contender for the bus or isochronous resource manager. hardware reset, this bit may only be set via a software register write. This bit is unaffected by a bus reset. delay, expressed as (jitter+1) × 20 ns. For the TSB81BA3, this field is 0. PC0−PC2 input terminals upon a hardware reset, and is unaffected by a bus reset. See Table 9. interface is nonoperational. This bit is reset to 0 by hardware reset and is unaffected by bus reset. disturbance to an audio stream. NOTE: Legacy IEEE Std 1394−1995 compliant PHYs are not capable of performing short bus resets. LKON/DS2 output to notify the LLC to service the interrupt. includes 1394a nodes; otherwise, 1394b loop healing prevents loops from being formed in the topology. by writing a 1 to this register bit. LKON/DS2 output to notify the LLC to service the interrupt. occur). This bit is reset to 0 by hardware reset, or by writing a 1 to this register bit. LKON/DS2 output to notify the LLC to service the interrupt. reset, or by writing a 1 to this register bit.

/C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0044 /C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0073 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS559B − DECEMBER 2002 − REVISED OCTOBER 2003 17POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 bit has no effect when the device is operating in 1394b mode. isochronous traffic by excessively delaying the transmission of cycle-start packets. reset and is unaffected by bus reset. This bit has no effect when the device is operating in 1394b mode. same as for the PHY_SPEED field (but limited to S400 maximum). BMODE input terminal on the TSB81BA3. when to set these bits are specified in the IEEE 1394.1 bridging specification. field is reset to 0 by a hardware reset and is unaffected by bus-reset. hardware-reset and is unaffected by bus-reset. Table 3. Page 0 (Port Status) Register Configuration

1000 Astat BStat Ch Con RXOK Dis

1001 Negotiated_speed PIE Fault Standby_fault Disscrm B_Only(0)

1010 DC_connected Max_port_speed (011b) LPP Cable_speed

1011 Connection_unreliable Reserved Beta_mode Reserved

1100 Port_error

1101 Reserved Loop_disable In_standby Hard_disable

1110 Reserved

1111 Reserved

/C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0044 /C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0073 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS559B − DECEMBER 2002 − REVISED OCTOBER 2003

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Table 4. Page 0 (Port Status) Register Field Descriptions encoding as the AStat field. Ch bit is invalid after a bus-reset until tree-ID has completed. to 1. The Con bit is reset to 0 by hardware reset and is unaffected by bus-reset. port detects connection tones from the peer PHY and operating speed negotiation is completed. RxOK 1 Rd Receive OK. In 1394a−2000 mode this bit indicates the reception of a debounced TPBias signal. In Beta_mode, this bit indicates the reception of a continuous electrically valid signal. Note: RxOK is set to false during the time that only connection tones are detected in beta mode. tones, but does not establish an active connection. Negotiated_speed 3 Rd Indicates the maximum speed negotiated between this PHY port and its immediately connected port. established during self-ID when in 1394a−2000 mode. bit to 0. This bit is reset to 0 by hardware reset and is unaffected by bus-reset. to 0. When this bit is cleared, standby errors are cleared. B_Only 1 Rd Beta-mode operation only. For the TSB81BA3, this bit is set to 0 for all ports.

/C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0044 /C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0073 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS559B − DECEMBER 2002 − REVISED OCTOBER 2003 19POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Table 4. Page 0 (Port Status) Register Field Descriptions (Continued) than maximum, but no lower than minimum speed. 1 Rd This flag is set permanently to 1. write of 1 to this field resets the value to 0. Beta_mode is 0, then the port is active and operating in the 1394a−2000 mode. Port_error 8 Rd/Wr Incremented whenever the port receives an invalid codeword, unless the value is already 255. by a single bus-wide diagnostic program. activated, then a loop would exist). Cleared on bus reset and on disconnection. In_standby 1 Rd This bit is set to 1 if the port is in standby power-management state.

/C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0044 /C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0073 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS559B − DECEMBER 2002 − REVISED OCTOBER 2003

20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

The vendor identification page identifies the vendor/manufacturer and compliance level. The page is selected by writing 1 to the Page_Select field in base register 7. Table 5 shows the configuration of the vendor identification page, and Table 6 shows the corresponding field descriptions. Table 5. Page 1 (Vendor ID) Register Configuration

1000 Compliance

1001 Reserved

1010 Vendor_ID[0]

1011 Vendor_ID[1]

1100 Vendor_ID[2]

1101 Product_ID[0]

1110 Product_ID[1]

1111 Product_ID[2]

Table 6. Page 1 (Vendor ID) Register Field Descriptions Compliance 8 Rd Compliance level. For the TSB81BA3 this field is 02h, indicating compliance with the P1394b specification. Instruments) (the MSB is at register address 1010b). Product_ID 24 Rd Product identifier. For the TSB81BA3 this field is 80_10_70h (the MSB is at register address 1101b). Table 8 shows the corresponding field descriptions. Table 7. Page 7 (Vendor-Dependent) Register Configuration

1000 Reserved Reserved

1001 Reserved for test

1010 Reserved for test

1011 Reserved for test

1100 Reserved for test

1101 Reserved for test

1110 SWR Reserved for test

1111 Reserved for test

Table 8. Page 7 (Vendor-Dependent) Register Field Descriptions asserting the RESETz terminal low). This bit is always read as a 0.

/C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0044 /C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0073 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS559B − DECEMBER 2002 − REVISED OCTOBER 2003 21POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 The PC0−PC2 terminals are programmed to set the default value of the power-class indicated in the pwr field (bits 21−23) of the transmitted self-ID packet. Descriptions of the various power-classes are given in Table 9. The default power-class value is loaded following a hardware reset, but is overridden by any value subsequently loaded into the Pwr_Class field in register 4. Table 9. Power Class Descriptions 000 Node does not need power and does not repeat power. 001 Node is self-powered and provides a minimum of 15 W to the bus. 010 Node is self-powered and provides a minimum of 30 W to the bus. 011 Node is self-powered and provides a minimum of 45 W to the bus. provide power to the bus. The amount of bus power that it provides can be found in the configuration ROM. 101 Reserved for future standardization. 110 Node is powered from the bus and uses up to 3 W. An additional 3 W is needed to enable the link. 111 Node is powered from the bus and uses up to 3 W. An additional 7 W is needed to enable the link.

/C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0044 /C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0073 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS559B − DECEMBER 2002 − REVISED OCTOBER 2003

22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

power-class programming (continued) TPA+ TPA− TPB+ TPB− Cable Port CPS TPBIAS 56 Ω56 Ω 56 Ω56 Ω 5 kΩ 1 µF 400 kΩ 270 pF (see Note A) TSB81BA3 Cable Power Pair Cable Pair A Cable Pair B Outer Shield Termination VP VG 1 MΩ 0.1 µF NOTE A: The IEEE Std 1394−1995 calls for a 250-pF capacitor, which is a nonstandard component value. A 270-pF capacitor is recommended. Figure 4. Typical TP Cable Connections Figure 5. Typical DC Isolated Outer Shield Termination

/C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0044 /C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0073 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS559B − DECEMBER 2002 − REVISED OCTOBER 2003

24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

designing with PowerPAD The TSB81BA3 is housed in a high performance, thermally enhanced, 80-terminal PFP PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. Therefore, if not implementing PowerPAD PCB features, the use of solder masks (or other assembly techniques) may be required to prevent any inadvertent shorting by the exposed PowerPAD of connection etches or vias under the package. The recommended option, however, is to not run any etches or signal vias under the device, but to have only a grounded thermal land as explained below. Although the actual size of the exposed die pad may vary, the maximum size required for the keepout area for the 80-terminal PFP PowerPAD package is 10 mm × 10 mm. The actual PowerPAD size for the TSB81BA3 is 6 mm × 6 mm. It is recommended that there be a thermal land, which is an area of solder-tinned-copper, underneath the PowerPAD package. The thermal land varies in size, depending on the PowerPAD package being used, the PCB construction, and the amount of heat that needs to be removed. In addition, the thermal land may or may not contain numerous thermal vias depending on PCB construction. Other requirements for thermal lands and thermal vias are detailed in the TI application note PowerPAD  Thermally Enhanced Package Application Report, (SLMA002), available via the TI Web pages at URL: http://www.ti.com. Figure 9. Example of a Thermal Land for the TSB81BA3 PHY exposed PowerPAD using standard reflow soldering techniques. information may be obtained from the TI application note PHY Layout, (SLLA020). PowerPAD is a trademark of Texas Instruments.

/C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0044 /C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0073 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS559B − DECEMBER 2002 − REVISED OCTOBER 2003 25POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 using the TSB81BA3 with a non-1394b link layer The TSB81BA3 implements the PHY-LLC interface specified in the 1394b Supplement. This interface is based upon the interface described in Section 14 of IEEE P1394b (draft 1.33). When using a LLC compliant with this interface, the BMODE input must be tied high. The TSB81BA3 also functions with a LLC that is compliant with the older 1394 standards. This interface is compatible with both the older Annex J interface specified in the IEEE Std 1394−1995 (with the exception of the Annex J isolation interfacing method) and the PHY-LLC interface specified in 1394a−2000. When using a LLC compliant with this interface, the BMODE input must be tied low. using the TSB81BA3 with a 1394−1995 or 1394a−2000 link layer When the BMODE input is tied low, the TSB81BA3 implements the PHY-LLC interface specified in the 1394a−2000 Supplement. This interface is based upon the interface described in informative Annex J of IEEE Std 1394−1995, which is the interface used in the oldest TI PHY devices. The PHY-LLC interface specified in 1394a−2000 is compatible with the older Annex J. However, the TSB81BA3 does not support the Annex J isolation interfacing method. When implementing the 1394a−2000 interface, certain signals are not used: − The PINT output (terminal 1) may be left open − The LCLK input (terminal 7) must be tied directly to ground or through a pulldown resistor of ~1 kΩ or less. All other signals are connected to their counterparts on the 1394a link-layer controller. The PCLK output corresponds to the SCLK input signal on most LLCs. The 1394a−2000 Supplement includes enhancements to the Annex J interface that should be comprehended when using the TSB81BA3 with a 1394−1995 LLC device. /C0068A new LLC service request was added which allows the LLC to temporarily enable and disable asynchronous arbitration accelerations. If the LLC does not implement this new service request, then the arbitration enhancements must not be enabled (see the EAA bit in PHY register 5). /C0068The capability to perform multispeed concatenation (the concatenation of packets of differing speeds) was added in order to improve bus efficiency (primarily during isochronous transmission). If the LLC does not support multispeed concatenation, then multispeed concatenation must not be enabled in the PHY (see the EMC bit in PHY register 5). /C0068In order to accommodate the higher transmission speeds expected in future revisions of the standard, 1394a−2000 extended the speed code in bus requests from 2 bits to 3 bits, increasing the length of the bus request from 7 bits to 8 bits. The new speed codes were carefully selected so that new 1394a−2000 PHY and LLC devices would be compatible, for speeds from S100 to S400, with legacy PHY and LLC devices that use the 2-bit speed codes. The TSB81BA3 correctly interprets both 7-bit bus requests (with 2-bit speed code) and 8-bit bus requests (with 3-bit speed codes). Moreover, if a 7-bit bus request is immediately followed by another request (for example, a register read or write request), then the TSB81BA3 correctly interprets both requests. Although the TSB81BA3 correctly interprets 8-bit bus requests, a request with a speed code exceeding S400 while in 1394a−2000 PHY-link interface mode results in the TSB81BA3 transmitting a null packet (data-prefix followed by data-end, with no data in the packet).

/C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0044 /C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0073 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS559B − DECEMBER 2002 − REVISED OCTOBER 2003

26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

To ensure proper operation of the TSB81BA3 the RESETz terminal must be asserted low for a minimum of 2 ms from the time that PHY power reaches the minimum required supply voltage. When using a passive capacitor on the RESETz terminal to generate a power-on reset signal, the minimum reset time is assured if the value of the capacitor satisfies the following equation (the value must be no smaller than approximately 0.1 µF): C min = 0.0077 × T + 0.085 + external_oscillator_start-up_time where Cmin is the minimum capacitance on the RESETz terminal in µF, T is the VDD ramp time, 10%−90%, in ms, external_oscillator_start-up_time is the time from power applied to the external oscillator till the oscillator outputs a valid clock in ms. crystal oscillator selection The TSB81BA3 is designed to use an external 98.304-MHz crystal oscillator connected to the XI terminal to provide the reference clock. This clock, in turn, drives a PLL circuit that generates the various clocks required for transmission and resynchronization of data at the S100 through S800 media data rates. A variation of less than ±100 ppm from nominal for the media data rates is required by IEEE Std 1394. Adjacent PHYs may therefore have a difference of up to 200 ppm from each other in their internal clocks, and PHYs must be able to compensate for this difference over the maximum packet length. Larger clock variations may cause resynchronization overflows or underflows, resulting in corrupted packet data. For the TSB81BA3, the PCLK output may be used to measure the frequency accuracy and stability of the internal oscillator and PLL from which it is derived. When operating the PHY-LLC interface with a non-1394b LLC, the frequency of the PCLK output must be within ±100 ppm of the nominal frequency of 49.152 MHz. When operating the PHY-LLC interface with a 1394b LLC, the frequency of the PCLK output must be within ±100 ppm of the nominal frequency of 98.304 MHz. The following are some typical specifications for an oscillator used with the TSB81BA3 physical layer from TI in order to achieve the required frequency accuracy and stability: /C0068RMS jitter of 5 picoseconds or better /C0068RMS phase noise jitter of 1 picosecond or less over the range 12 kHz to 20 MHz or better /C0068Frequency tolerance at 25/C0095C: Total frequency variation for the complete circuit is ±100 ppm. A device with ±30 ppm or ±50 ppm frequency tolerance is recommended for adequate margin. /C0068Frequency stability (over temperature and age): A device with ±30 ppm or ±50 ppm frequency stability is recommended for adequate margin. NOTE: The total frequency variation must be kept below ±100 ppm from nominal with some allowance for error introduced by board and device variations. Trade-offs between frequency tolerance and stability may be made as long as the total frequency variation is less than ±100 ppm. For example, the frequency tolerance of the crystal may be specified at 50 ppm and the temperature tolerance may be specified at 30 ppm to give a total of 80 ppm possible variation due to the oscillator alone. Aging also contributes to the frequency variation. It is strongly recommended that part of the verification process for the design is to measure the frequency of the PCLK output of the PHY. This should be done with a frequency counter with an accuracy of 6 digits or better.

/C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0044 /C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0073 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS559B − DECEMBER 2002 − REVISED OCTOBER 2003 27POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 It is recommended, that whenever the user has a choice, the user should initiate a bus reset by writing to the initiate short bus reset (ISBR) bit (bit 1 PHY register 0101b). Care must be taken to not change the value of any of the other writeable bits in this register when the ISBR bit is written to. In the TSB81BA3, the initiate bus reset (IBR) bit may be set to 1 in order to initiate a bus reset and initialization sequence, however, it is recommended to use the ISBR bit instead. The IBR bit is located in PHY register 1 along with the root-holdoff (RHB) bit and gap-count register. As required by the 1394b Supplement this configuration maintains compatibility with older TI PHY designs which were based upon either the suggested register set defined in Annex J of IEEE Std 1394−1995 or the 1394a−2000 Supplement. Therefore, whenever the IBR bit is written, the RHB bit and gap-count are also necessarily written. It is recommended that the RHB bit and gap-count only be updated by PHY configuration packets. The TSB81BA3 is 1394a and 1394b compliant, and therefore both the reception and transmission of PHY configuration packets cause the RHB and gap-count to be loaded, unlike older IEEE Std 1394−1995 compliant PHYs which decode only received PHY configuration packets. The gap-count is set to the maximum value of 63 after two consecutive bus resets without an intervening write to the gap-count, either by a write to PHY register 1 or by a PHY configuration packet. This mechanism allows a PHY configuration packet to be transmitted and then a bus reset initiated so as to verify that all nodes on the bus have updated their RHB bits and gap-count values, without having the gap-count set back to 63 by the bus reset. The subsequent connection of a new node to the bus, which initiates a bus reset, then causes the gap-count of each node to be set to 63. Note, however, that if a subsequent bus reset is instead initiated by a write to register 1 to set the IBR bit, then all other nodes on the bus have their gap-count values set to 63, while this node’s gap-count remains set to the value just loaded by the write to PHY register 1. Therefore, in order to maintain consistent gap-counts throughout the bus, the following rules apply to the use of the IBR bit, RHB bit, and gap-count in PHY register 1: /C0068Following the transmission of a PHY configuration packet, a bus reset must be initiated in order to verify that all nodes have correctly updated their RHB bits and gap-count values, and to ensure that a subsequent new connection to the bus causes the gap-count to be set to 63 on all nodes in the bus. If this bus reset is initiated by setting the IBR bit to 1, then the RHB bit and gap-count register must also be loaded with the correct values consistent with the just transmitted PHY configuration packet. In the TSB81BA3, the RHB bit and gap-count have been updated to their correct values upon the transmission of the PHY configuration packet, and so these values may first be read from register 1 and then rewritten. /C0068Other than to initiate the bus reset which must follow the transmission of a PHY configuration packet, whenever the IBR bit is set to 1 in order to initiate a bus reset, the gap-count value must also be set to 63 so as to be consistent with other nodes on the bus, and the RHB bit must be maintained with its current value. /C0068The PHY register 1 must not be written to except to set the IBR bit. The RHB bit and gap-count must not be written without also setting the IBR bit to 1. /C0068To avoid these problems all bus resets initiated by software must be initiated by writing the ISBR bit (bit 1 PHY register 0101b). Care must be taken to not change the value of any of the other writeable bits in this register when the ISBR bit is written to. Also, the only means to change the gap count of any node must be by means of the PHY configuration packet, which changes all nodes to the same gap count.

28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

the operation of the PHY-LLC interface. This interface is formally defined in IEEE 1394a−2000, Section 5A. the TSB81BA3, as shown in Figure 10. Figure 10. PHY-LLC Interface of 1394a−2000 compliant PHY devices. between the TSB81BA3 and LLC. the LLC is in control of the D0−D7 bus, unused Dn terminals are ignored by the TSB81BA3. to the serial-bus for packet transmission, read or write PHY registers, or control arbitration acceleration. the LLC when either LPS is inactive or the PHY register L bit is 0. these buses only after the LLC has been granted permission to do so by the PHY.

to gain control of the serial-bus in order to transmit a packet, or to control arbitration acceleration. The PHY initiates a receive operation whenever a packet is received from the serial-bus. The PHY initiates a transmit operation after winning control of the serial-bus following a bus-request by the LLC. The transmit operation is initiated when the PHY grants control of the interface to the LLC. Table 10 and Table 11 show the encoding of the CTL0−CTL1 bus. Table 10. CTL Encoding When PHY Has Control of the Bus 0 1 Status Status information is being sent from the PHY to the LLC. 1 0 Receive An incoming packet is being sent from the PHY to the LLC. 1 1 Grant The LLC has been given control of the bus to send an outgoing packet. Table 11. CTL Encoding When LLC Has Control of the Bus a serial bit stream on the LREQ terminal as shown in Figure 11. Each cell represents one clock sample time, and n is the number of bits in the request stream. Figure 11. LREQ Request Stream

30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

The length of the stream varies depending on the type of request as shown in Table 12. Table 12. Request Stream Bit Length the request. In the descriptions below, bit 0 is the most significant and is transmitted first in the request bit stream. The LREQ terminal is normally low. Table 13 shows the encoding for the request type. Table 13. Request Type Encoding 000 ImmReq Immediate bus request. Upon detection of idle, the PHY takes control of the bus immediately without arbitration. 001 IsoReq Isochronous bus request. Upon detection of idle, the PHY arbitrates for the bus without waiting for a subaction gap. 010 PriReq Priority bus request. The PHY arbitrates for the bus after a subaction gap, ignores the fair protocol. 011 FairReq Fair bus request. The PHY arbitrates for the bus after a subaction gap, follows the fair protocol.

100 RdReg The PHY returns the specified register contents through a status transfer

101 WrReg Write to the specified register

110 AccelCtl Enable or disable asynchronous arbitration acceleration

111 Reserved Reserved

For a bus request, the length of the LREQ bit stream is 7 or 8 bits as shown in Table 14. Table 14. Bus Request

0 Start bit Indicates the beginning of the transfer (always 1)

1−3 Request type Indicates the type of bus request. See Table 13. 4−6 Request speed Indicates the speed at which the PHY sends the data for this request. See Table 15 for the encoding of this field. 7 Stop bit Indicates the end of the transfer (always 0). If bit 6 is 0, then this bit may be omitted. Table 15 shows the 3-bit request speed field used in bus requests. Table 15. Bus Request Speed Encoding

000 S100

010 S200

100 S400

presented by the LLC and transmits a null packet. For a read register request the length of the LREQ bit stream is 9 bits as shown in Table 16. Table 16. Read Register Request

8 Stop bit Indicates the end of the transfer (always 0)

For a write register request, the length of the LREQ bit stream is 17 bits as shown in Table 17. Table 17. Write Register Request

16 Stop bit Indicates the end of the transfer (always 0)

For an acceleration control request, the length of the LREQ data stream is 6 bits as shown in Table 18. Table 18. Acceleration Control Request

4 Control Asynchronous period arbitration acceleration is enabled if 1, and disabled if 0

5 Stop bIt Indicates the end of the transfer (always 0)

clock after the next interface idle. an isochronous request only when the serial bus has been won.

/C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0044 /C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0073 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS559B − DECEMBER 2002 − REVISED OCTOBER 2003

32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION (1394a−2000 INTERFACE) LLC service request (continued) To send an acknowledge packet, the LLC must issue an immediate bus request (ImmReq) during the reception of the packet addressed to it. This is required in order to minimize the idle gap between the end of the received packet and the start of the transmitted acknowledge packet. As soon as the receive packet ends, the PHY immediately grants control of the bus to the LLC. The LLC sends an acknowledgment to the sender unless the header CRC of the received packet is corrupted. In this case, the LLC does not transmit an acknowledge, but instead cancels the transmit operation and releases the interface immediately; the LLC must not use this grant to send another type of packet. After the interface is released the LLC may proceed with another request. The LLC may make only one bus request at a time. Once the LLC issues any request for bus access (ImmReq, IsoReq, FairReq, or PriReq), it cannot issue another bus request until the PHY indicates that the bus request was lost (bus arbitration lost and another packet received), or won (bus arbitration won and the LLC granted control). The PHY ignores new bus requests while a previous bus request is pending. All bus requests are cleared upon a bus reset. For write register requests, the PHY loads the specified data into the addressed register as soon as the request transfer is complete. For read register requests, the PHY returns the contents of the addressed register to the LLC at the next opportunity through a status transfer. If a received packet interrupts the status transfer, then the PHY continues to attempt the transfer of the requested register until it is successful. A write or read register request may be made at any time, including while a bus request is pending. Once a read register request is made, the PHY ignores further read register requests until the register contents are successfully transferred to the LLC. A bus reset does not clear a pending read register request. The TSB81BA3 includes several arbitration acceleration enhancements, which allow the PHY to improve bus performance and throughput by reducing the number and length of interpacket gaps. These enhancements include autonomous (fly-by) isochronous packet concatenation, autonomous fair and priority packet concatenation onto acknowledge packets, and accelerated fair and priority request arbitration following acknowledge packets. The enhancements are enabled when the EAA bit in PHY register 5 is set. The arbitration acceleration enhancements may interfere with the ability of the cycle master node to transmit the cycle start message under certain circumstances. The acceleration control request is therefore provided to allow the LLC to temporarily enable or disable the arbitration acceleration enhancements of the TSB81BA3 during the asynchronous period. The LLC typically disables the enhancements when its internal cycle counter rolls over indicating that a cycle start message is imminent, and then re-enables the enhancements when it receives a cycle start message. The acceleration control request may be made at any time, however, and is immediately serviced by the PHY. Additionally, a bus reset or isochronous bus request causes the enhancements to be re-enabled, if the EAA bit is set.

been successfully transmitted. There is at least one idle cycle between consecutive status transfers. transfer has not yet completed. Table 19 shows the definition of the bits in the status transfer and Figure 12 shows the timing. Table 19. Status Bits the IEEE 1394a−2000 standard). This bit is used by the LLC in the busy/retry state machine. IEEE 1394a−2000 standard). This bit is used by the LLC to detect the completion of an isochronous cycle.

2 Bus reset Indicates that the PHY has entered the bus reset state

cable-power voltage falling too low, a state time-out, or a port status change. Figure 12. Status Transfer Timing

34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

to be sent in addition to any status information. (b) Status transfer terminated. The PHY normally terminates a status transfer by asserting idle on the CTL lines. a receive operation. The PHY asserts at least one idle cycle between consecutive status transfers. not included in the calculation of CRC or any other data protection mechanisms. or terminating the receive operation. to the LLC. This packet it transferred to the LLC just as any other received self-ID packet. Figure 13. Normal Packet Reception Timing

(a) Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines. that which the link is capable of handling, then the link must ignore the subsequent data. on the D lines with receive on the CTL lines for the remainder of the receive operation. (e) Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines. The PHY asserts at least one idle cycle following a receive operation. Figure 14. Null Packet Reception Timing (a) Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines. (b) Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more cycles. (c) Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines. The PHY asserts at least one idle cycle following a receive operation. Table 20. Receive Speed Codes

0100 XXXX S200

NOTE: X = Output as 0 by PHY, ignored by LLC. Y = Output as 1 by PHY, ignored by LLC.

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When the LLC issues a bus request through the LREQ terminal, the PHY arbitrates to gain control of the bus. then takes control of the bus by asserting either idle (00b), hold (01b) or transmit (10b) on the CTL terminals. high-impedance state. The PHY then regains control of the interface bus. speed code that precedes received packet data as given in Table 20. Figure 15. Normal Packet Transmission Timing

(that is, it places its CTL and D outputs in a high-impedance state) following the idle cycle. (b) Optional idle cycle. The link may assert at most one idle cycle preceding assertion of either hold or transmit. This idle cycle is optional; the link is not required to assert idle preceding either hold or transmit. hold cycle(s) are optional; the link is not required to assert hold preceding transmit. cycle before releasing the interface and returning control to the PHY. Table 20). The link may not concatenate an S100 packet onto any higher-speed packet. transfer, receive operation, or transmit operation. Figure 16. Cancelled/Null Packet Transmission

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is optional; the link is not required to assert idle preceding hold. cycle(s) are optional; the link is not required to assert hold preceding idle. cycles are asserted. This ensures that either the link or PHY controls the interface in all cycles. transfer, receive operation, or transmit operation. interface to normal operation. signal. Timing parameters for the LPS signal are given in Table 21. Table 21. LPS Timing Parameters requirements of 1394a−2000 operates correctly with the TSB81BA3).

1. A pulsed LPS signal must have a duty cycle (ratio of TLPSH to cycle period) in the specified range to ensure proper operation when

using an isolation barrier on the LPS signal (for example, as shown in Figure 8).

on the LREQ signal. Figure 17 shows the timing for interface reset. Figure 17. Interface Reset bus activity, places its CTL and D outputs into a high-impedance state, and drives its LREQ output low. bus activity, and drives its CTL and D outputs low. The PHY-LLC interface is now in the reset state. is asserted, the interface is initialized as described below. is disabled, the PHY sets its CTL and D outputs as stated above for interface reset, but also stops PCLK activity. timing for the interface disable. When the interface is disabled, the PHY enters a low-power state if none of its ports are active.

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Figure 18. Interface Disable reception and transmission via the CTL and D lines, and request activity via the LREQ line. bus activity, places its CTL and D outputs into a high-impedance state, and drives its LREQ output low. bus activity, and drives its CTL and D outputs low. The PHY-LLC interface is now in the reset state. activity by driving the PCLK output low. The PHY-LLC interface is now in the disabled state. operation when LPS is reasserted by the LLC. Figure 19 shows the timing for interface initialization.

7 Cycles

Figure 19. Interface Initialization state on the CTL lines and the data-on indication (all 1s) on the D lines for one or more cycles. PHY now accepts requests from the LLC via the LREQ line.

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formally specified in the IEEE P1394b standard. terminals on the TSB81BA3, as shown in Figure 20. Figure 20. PHY-LLC Interface is phase-locked to the PCLK signal. All LLC to PHY transfers are synchronous to LCLK. are synchronized to the rising edge of PCLK. between the TSB81BA3 and LLC. data bus. In S400B and S800 operation all Dn terminals are used. LPS is inactive or the PHY register L bit is 0. The PINT terminal is used by the PHY for the serial transfer of status, interrupt, and other information to the LLC.

these buses only after the LLC has been granted permission to do so by the PHY. PHY to gain control of the serial-bus in order to transmit a packet. The PHY initiates a receive operation whenever a packet is received from the serial-bus. The PHY initiates a transmit operation after winning control of the serial-bus following a bus-request by the LLC. The transmit operation is initiated when the PHY grants control of the interface to the LLC. Table 22 and Table 23 show the encoding of the CTL0−CTL1 bus. Table 22. CTL Encoding When PHY Has Control of the Bus 0 1 Status Status information is being sent from the PHY to the LLC. 1 0 Receive An incoming packet is being sent from the PHY to the LLC. 1 1 Grant The LLC has been given control of the bus to send an outgoing packet. Table 23. CTL Encoding When LLC Has Control of the Bus 0 0 Idle The LLC releases the bus (transmission has been completed). 0 1 Transmit An outgoing packet is being sent from the LLC to the PHY. arbitrate for access to the bus, or the LLC is identifying the end of a subaction gap to the PHY. a serial bit stream on the LREQ terminal as shown in Figure 21. Each cell represents one clock sample time, and n is the number of bits in the request stream. Figure 21. LREQ Request Stream The length of the stream varies depending on the type of request as shown in Table 24.

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Table 24. Request Stream Bit Length request. In the descriptions below, bit 0 is the most significant and is transmitted first in the request bit stream. The LREQ terminal is normally low. Table 25 show the encoding for the request type. Table 25. Request Type Encoding

0000 Reserved Reserved

0001 Immed_Req Immediate request. Upon detection of idle, the PHY arbitrates for the bus.

0101 Reserved Reserved

1000 Cyc_Start_Req Cycle start request. The PHY arbitrates for the bus to send a cycle start packet.

1001 Reserved Reserved

1010 Reg_Read Register read request. The PHY returns the specified register contents through a status transfer. 1011 Reg_Write Register write request. Write to the specified register in the PHY. 2) The link has set the isochronous phase to even. 2) The link has set the isochronous phase to odd. 1110 Cycle_Start_Due Cycle start due notification. The link reports to the PHY that a cycle start packet is due for reception.

1111 Reserved Reserved

For a bus request, the length of the LREQ bit stream is 11 bits as shown in Table 26.

Table 26. Bus Request 1−4 Request type Indicates the type of bus request. See Table 25. 5 Request format Indicates the packet format to be used for packet transmission. See Table 27. 6−9 Request speed Indicates the speed at which the link sends the data to the PHY. See Table 28 for the encoding of this field. 10 Stop bit Indicates the end of the transfer (always 0). If bit 6 is 0, then this bit may be omitted. Table 27 shows the 1-bit request format field used in bus requests. Table 27. Bus Request Format Encoding

0 Link does not request either beta or legacy packet format for bus transmission

1 Link requests beta packet format for bus transmission

Table 28 shows the 4-bit request speed field used in bus requests. Table 28. TBus Request Speed Encoding

0000 S100

0001 Reserved

0010 S200

0011 Reserved

0100 S400

0101 Reserved

0110 S800

presented by the LLC and transmits a null packet. For a read register request, the length of the LREQ bit stream is 10 bits as shown in Table 29. Table 29. Read Register Request

9 Stop bit Indicates the end of the transfer (always 0)

For a write register request, the length of the LREQ bit stream is 18 bits as shown in Table 30.

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Table 30. Write Register Request

17 Stop bit Indicates the end of the transfer (always 0)

For a link notification request, the length of the LREQ bit stream is 6 bits as shown in Table 31. Table 31. Link Notification Request PHY clears an isochronous request only when the serial bus has been won. clear a pending read register request.

interface reset operation, the PHY-link interface is reset on the following PCLK cycle. Table 32 shows the definition of the bits during the bus status transfer and Figure 22 shows the timing. Table 32. Status Bits Figure 22. Bus Status Transfer Timing

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PHY status transfers use the PINT terminal to serially send status information to the LLC as shown in Figure 23. INTERFACE_ERROR PHY status transfer. Each cell represents one clock sample time, and n is the number of bits in the request stream. Figure 23. PINT (PHY Interrupt) Stream Table 33. PHY Status Transfer Encoding

000 NOP No status indication 5

001 PHY_INTERRUPT Interrupt indication: configuration timeout, cable power failure, port event

010 PHY_REGISTER_SOL Solicited PHY register read 17

011 PHY_REGISTER_UNSOL Unsolicited PHY register read 17

100 PH_RESTORE_NO_RESET PHY-link interface initialized; no bus resets occurred 5

101 PH_RESTORE_RESET PHY-link interface initialized; a bus reset occurred 5

110 INTERFACE_ERROR PHY received illegal request 5

111 Reserved Reserved Reserved

additional information of the register address and the data contents of the register (see Table 34). Table 34. Register Read (Solicited and Unsolicited) PHY Status Transfer Encoding

in the calculation of CRC or any other data protection mechanisms. during the data-on indication does not need to be preceded or followed by a data-on indication. terminating the receive operation. to the LLC. This packet it transferred to the LLC just as any other received self-ID packet. Figure 24. Normal Packet Reception Timing

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NOTE A: SPD = Speed code, see Table 35. d0–dn = Packet data. STATUS = status bits, see Table 32. Figure 25. Normal Packet Reception Timing with Optional Bus Status Transfer (a) Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines. that which the link is capable of handling, then the link must ignore the subsequent data. on the D lines with receive on the CTL lines for the remainder of the receive operation. (e) Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines. The PHY asserts at least one idle cycle following a receive operation. Figure 26. Null Packet Reception Timing

(a) Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines. (b) Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more cycles. (c) Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines. The PHY asserts at least one idle cycle following a receive operation. Table 35. Receive Speed Codes and Format NOTE: Y = Output as 1 by PHY, ignored by LLC. X = Output as 0 by PHY, ignored by LLC. When the LLC issues a bus request through the LREQ terminal, the PHY arbitrates to gain control of the bus. LLC need not assert hold before transmit). During the hold state, the LLC is expected to drive the D lines to 0. The PHY asserts data-prefix on the serial bus during this time.

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00 GT 00 ZZ ZZ ZZ ZZ ZZZZ

Figure 27. Transmit Packet Timing with Optional Link Request subaction, then the LLC sets D4 during the hold state at the end of packet transmission.

Table 36. Link Request Type Encoding During Packet Transmission

000 No request

001 Isoch_Req_Odd

010 Isoch_Req_Even

011 Current

100 Next_Even

101 Next_Odd

110 Cyc_Start_Req

111 Reserved

Table 37. Link Request Speed Code Encoding During Packet Transmission

00 S100

01 S200

10 S400

11 S800

Table 38. Link Request Format Encoding During Packet Transmission Table 39. Subaction End Notification Encoding During Packet Transmission

0 Transmitted packet does not represent end of a subaction

1 Transmitted packet marks the end of a subaction

Table 40. Format Type During Grant Cycle

0 Unspecified

1 Beta format

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Table 41. Grant Type Values During Grant Cycle

000 Reserved

001 Reserved

010 Isochronous grant

011 Reserved

100 Reserved

101 Asynchronous grant

110 Cycle start grant

111 Immediate grant

Table 42. Speed Type Values During Grant Cycle

/C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0044 /C0084/C0083/C0066/C0056/C0049/C0066/C0065/C0051/C0073 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS559B − DECEMBER 2002 − REVISED OCTOBER 2003 55POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THERMAL PAD MECHANICAL DATA PPTD014 PFP (S−PQFP−G80) PowerPAD /C0116 PLASTIC QUAD FLATPACK

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