TSB711 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 36
Technical content
Datasheet sections
- 1 Pin description
- 2 Absolute maximum ratings and operating conditions
- 3 Electrical characteristics
- 4 Typical performance characteristics
- 5 Application information
- 5.1 Operating voltages
- 5.2 Input pin voltage range
- 5.3 Rail-to-rail input stage
- 5.4 Input offset voltage drift over the temperature
- 5.5 Long term input offset voltage drift
- 5.6 EMI rejection
- 5.7 Maximum power dissipation
- 5.8 Capacitive load and stability
- 5.9 PCB layout recommendations
- 5.10 Decoupling capacitor
- 6 Typical applications
- 6.1 Low-side current sensing
- 7 Package information
- 7.1 SOT23-5 package information
- 7.2 MiniSO8 package information
- 7.3 SO8 package information
- 7.4 SO14 package information
- 7.5 TSSOP14 package information
- 8 Ordering information
Features
- Rail-to-rail input and output
- Low offset voltage: 300 µV maximum
- Wide supply voltage range: 2.7 V to 36 V
- Gain bandwidth product: 6 MHz
- Slew rate : 3 V/µs
- Low noise : 12 nV/√Hz
- Integrated EMI filter
- 2 kV HBM ESD tolerance
- Extended temperature range : -40 °C to +125 °C
- Automotive-grade available
Applications
- High-side and low-side current sensing
- Hall effect sensors
- Data acquisition and instrumentation
- Test and measurement equipments
- Motor control
- Industrial process control
- Strain gauge
Description
The TSB711, TSB711A, TSB712, TSB712A,TSB714 and TSB714A 6 MHz bandwidth amplifiers feature rail-to-rail input and output, which is guaranteed to operate from +2.7 V to +36 V single supply as well as from ±1.35 V to ±18 V dual supplies. These amplifiers have the advantage of offering a large span of supply voltage and an excellent input offset voltage of 300 µV maximum at 25 °C. The combination of wide bandwidth, slew rate, low noise, rail-to-rail capability and precision makes the TSB711, TSB711A, TSB712, TSB712A,TSB714 and TSB714A useful in a wide variety of applications such as: filters, power supply and motor control, actuator driving, hall effect sensors and resistive transducers. Maturity status link TSB711, TSB711A, TSB712, TSB712A, TSB714, TSB714A
Related products
TSB571, TSB572 Single, Dual op-amps for the low-power consumption version (380 µA with
2.5 MHz GBP)
Precision rail-to-rail input / output 36 V, 6 MHz op-amps TSB711, TSB711A, TSB712 TSB712A, TSB714, TSB714A Datasheet DS12487 - Rev 6 - October 2020 For further information contact your local STMicroelectronics sales office.
1 Pin description
Figure 1. TSB711 pin connections (top view) Table 1. TSB711 pin description (SOT23-5)
1 OUT Output channel
2 VCC- Negative supply voltage
3 IN1+ Non-inverting input channel
4 IN- Inverting input channel
5 VCC+ Positive supply voltage
Figure 2. TSB712 pin connections (top view) Table 2. TSB712 pin description (miniSO8/SO8)
1 OUT1 Output channel 1
2 IN1- Inverting input channel 1
3 IN1+ Non-inverting input channel 1
4 VCC- Negative supply voltage
5 IN2+ Non-inverting input channel 2
6 IN2- Inverting input channel 2
7 OUT2 Output channel 2
8 VCC+ Positive supply voltage
Figure 3. TSB714 pin connections (top view) Table 3. TSB714 pin description
4 VCC+ Positive supply voltage
8 OUT3 Output channel 3
9 IN3- Inverting input channel 3
10 IN3+ Non-inverting input channel 3
11 VCC- Negative supply voltage
12 IN4+ Non-inverting input channel 4
13 IN4- Inverting input channel 4
14 OUT4 Output channel 4
2 Absolute maximum ratings and operating conditions
Table 4. Absolute maximum ratings
- All voltage values, except the differential voltage are with respect to the network ground terminal.
- Differential voltages are the non-inverting input terminal with respect to the inverting input terminal. The maximum input
- Input current must be limited by a resistor in series with the inputs when the input voltage is beyond the rails (see
Section 5.2 Input pin voltage range).
- Short-circuits can cause excessive heating and destructive dissipation.
- Human body according to JEDEC standard JESD22-A114F.
- According to ANSI/ESD STM5.3.1.
Table 5. Operating conditions
3 Electrical characteristics
Table 6. Electrical characteristics at VCC = 36 V, VICM = VOUT = VCC / 2, Tamb = 25 °C and RL connected to
Electrical characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit CMR Common-mode rejection ratio 20 log (∆VINCM / ∆VIO) T = 25 °C dB TSB711A,TSB712A (VCC-) ≤ VICM ≤ (VCC+), TSB711, TSB712 (VCC-) ≤ VICM ≤ (VCC+), T = 25 °C 90 120 TSB711 , TSB712 (VCC-) ≤ VICM ≤ (VCC+), SVR Power supply rejection ratio 20 log (∆VCC / ∆VIO)
5 V < (VCC+) - (VCC-) < 36 V, VICM = VCC / 2
High level output voltage (drop voltage from VCC+) No load, -40 °C < T < 125 °C 120 mV ISOURCE = 2 mA, -40 °C < T < 125 °C 200 ISOURCE = 15 mA, -40 °C < T < 125 °C 1000 VOL Low level output voltage No load , -40 °C < T < 125 °C 120 ISINK = 2 mA, -40 °C < T < 125 °C 200 ISINK = 15 mA , -40 °C < T < 125 °C 1000 IOUT ISINK VOUT = VCC, T = 25 °C 25 50 mA VOUT = VCC, -40 °C < T < 125 °C 20 ISOURCE VOUT = 0 V, T = 25 °C 25 50 VOUT = 0 V, -40 °C < T < 125 °C 20 ICC Supply current by op-amp No load, T = 25 °C 1.8 mA No load, -40 °C < T < 125 °C 3 AC performance GBP Gain bandwidth product RL = 10 kΩ, CL = 100 pF 4.5 6 MHz SR Slew rate
9 V step, RL = 10 kΩ, CL = 100 pF,
AV = 1 V/V, 10% to 90% 2.2 3 V / µs THD+N Total harmonic distorsion + noise VIN = 1 Vrms , RL = 10 kΩ, AV = +1, f = 1 kHz, BW = 22 kHz 0,0003 VIN = 1 Vrms , RL = 1 kΩ, AV = +1, f = 1 kHz, BW = 22 kHz 0,00034 CR Crosstalk VOUT = 5 Vpp, f = 1 kHz, AV = +11, RL = 10 kΩ 125 dB VOUT = 5Vpp, f = 10 kHz, AV = +11, RL = 10 kΩ 100 Φm Phase margin At unity gain, 25 °C, 10 kΩ, 100 pF 45 ᵒ CLOAD Capacitive load drive 100(5) pF en Input voltage noise density f = 10 Hz 20 nV / √Hzf = 100 Hz 13 f = 10 kHz 12 en p-p Input noise voltage 0.1 Hz ≤ f ≤ 10 Hz 0.5 µVPP TSB711, TSB711A, TSB712, TSB712A, TSB714, TSB714A
Symbol Parameter Conditions Min. Typ. Max. Unit in Input current noise density f = 1 kHz 0.15 (6) pA / √Hz 1. See Section 5.4 Input offset voltage drift over the temperature in application information. 2. Typical value is based on the V IO drift observed after 1000 h at 125 °C extrapolated to 25 °C using the Arrhenius law and assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration. See Section 5.5 Long term input offset voltage drift. 3. Current is positive when it is sinked into the op-amp. 4. I io is defined as |Iibp – Iibn| capacitive load and Figure 28. Overshoot vs. capacitive load at VCC = 36 V 6. Theoretical value of the input current noise density based on the measurement of the input transistor base current: i n = 2. q . i b TSB711, TSB711A, TSB712, TSB712A, TSB714, TSB714A
Table 7. Electrical characteristics at VCC = 5 V, VICM = VOUT = VCC / 2, Tamb = 25 °C and RL connected to
Symbol Parameter Conditions Min. Typ. Max. Unit CMR Common-mode rejection ratio 20 log ( ∆VINCM / ∆VIO ) T = 25 °C dBTSB711, TSB712 (VCC-) ≤ VICM ≤ (VCC+), VOH High level output voltage (drop voltage from VCC+) No load, -40 °C < T < 125 °C 90 mV ISOURCE = 2 mA, -40 °C < T < 125 °C 200 VOL Low level output voltage No load, -40 °C < T < 125 °C 90 ISINK = 2 mA, -40 °C < T < 125 °C 200 IOUT ISINK VOUT = VCC, T = 25 °C 20 50 mA VOUT = VCC, -40 °C < T < 125 °C 15 ISOURCE VOUT = 0 V, T = 25 °C 20 50 VOUT = 0 V, -40 °C < T < 125 °C 15 ICC Supply current by op-amp No load, T = 25 °C 1.4 mA No load, -40 °C < T < 125 °C 2.3 AC performance GBP Gain bandwidth product RL = 10 kΩ, CL = 100 pF 4.5 6 MHz SR Slew rate
3 V step, RL = 10 kΩ, CL = 100 pF,
AV = 1 V/V, 10% to 90% 2 2.7 V / µs THD+N Total harmonic distorsion + noise VIN = 1 Vrms , RL = 10 kΩ, AV = +1, f = 1 kHz, BW = 22 kHz 0,00032 VIN = 1 Vrms , RL = 1 kΩ, AV = +1, f = 1 kHz, BW = 22 kHz 0,0004 Φm Phase margin At unity gain, 25 °C, 10 kΩ, 100 pF 34 ᵒ CLOAD Capacitive load drive 100(4) pF en Input voltage noise density f = 10 Hz 20 nV / √Hzf = 100 Hz 13 f = 10 kHz 12 en p-p Input noise voltage 0.1 Hz ≤ f ≤ 10 Hz 0.8 µVPP in Input current noise density f = 1 kHz 0.15 (5) pA / √Hz 1. See Section 5.4 Input offset voltage drift over the temperature in application information. 2. Current is positive when it is sinked into the op-amp. 3. I io is defined as |Iibp – Iibn|. capacitive load 5. Theoretical value of the input current noise density based on the measurement of the input transistor base current: i n = 2. q . i b TSB711, TSB711A, TSB712, TSB712A, TSB714, TSB714A
4 Typical performance characteristics
RL connected to VCC / 2 (unless otherwise specified). Figure 4. Supply current vs. supply voltage Figure 5. Input offset voltage distribution at VCC = 5 V Figure 6. Input offset voltage distribution at VCC = 36 V
5 Application information
5.1 Operating voltages
The TSB711, TSB711A, TSB712, TSB712A devices can operate from 2.7 to 36 V. The parameters are fully specified at 5 V and 36 V power supplies. However, the parameters are very stable over the full VCC range and several characterization curves show the TSB711, TSB711A, TSB712, TSB712A device characteristics over the full operating range. Additionally, the main specifications are guaranteed in extended temperature range from -40 to 125 °C.
5.2 Input pin voltage range
The TSB711, TSB711A,TSB712 and TSB712A devices have an internal ESD diode protection on the inputs. These diodes are connected between the inputs and each supply rail to protect the input stage from electrical discharge, as shown in the figure below. Figure 42. Input current limitation this voltage, excessive current can flow through them. Without limitation this overcurrent can damage the device. In this case, the current has to be limited to 10 mA by adding a resistance in series with the input pin. device is used in comparator mode. inside the absolute maximum ratings (AMR) voltage window, (VCC-) - 200 mV < VICM < (VCC+) + 200 mV.
Application information
DS12487 - Rev 6 page 17/36
5.3 Rail-to-rail input stage
differential pairs, as shown in the figure below. Figure 43. Rail-to-rail input stage Figure 12. Input offset voltage vs. common mode voltage at VCC = 5 V TSB711A, TSB712A and Figure 13. Input Please also notice that the input bias current polarity depends on the operation of NPN or PNP input stage. Figure 17. Input bias current vs. common mode voltage at VCC = 36 V.
5.4 Input offset voltage drift over the temperature
(process capability index) greater than 1.3.
5.5 Long term input offset voltage drift
To evaluate product reliability, two types of stress acceleration are used:
- Voltage acceleration, by changing the applied voltage.
- Temperature acceleration, by changing the die temperature (below the maximum junction temperature allowed by the technology) with the ambient temperature. The voltage acceleration has been defined based on JEDEC results, and is defined using: (2) AFV = еβ.(VS - VU) Where: AFV is the voltage acceleration factor β is the voltage acceleration coefficient in 1/V, constant technology parameter (β = 1) VS is the stress voltage used for the accelerated test VU is the voltage used for the application The temperature acceleration is driven by the Arrhenius model, and is defined as follows: (3) A F T = e E a k . 1 T U − 1 T S . Where: AFT is the temperature acceleration factor Ea is the activation energy of the technology based on the failure rate k is the Boltzmann constant (8.6173 x 10-5 eV.K-1) TU is the temperature of the die when VU is used (K) TS is the temperature of the die under temperature stress (K) The final acceleration factor, AF, is the multiplication of the voltage acceleration factor and the temperature acceleration factor. (4) AF = AFT . AFV AF is calculated using the temperature and voltage defined in the mission profile of the product. The AF value can then be used in Equation 5 to calculate the number of months of use equivalent to 1000 hours of reliable stress duration. (5) Months = AF × 1000 h × 12 months / (24 h × 365.25 days) To evaluate the op-amp reliability, a follower stress condition is used where VCC is defined as a function of the maximum operating voltage and the absolute maximum ratings (as recommended by JEDEC rules). Vio drift (in µV) of the product after 1000 h of stress is tracked with parameters at different measurement conditions. (6) VCC = max(VOP) with Vicm = VCC/2 The long term drift parameter ΔVio (in µV.month-1/2), estimating the reliability performance of the product, is obtained using the ratio of the Vio (input offset voltage value) drift over the square root of the calculated number of months. (7) ∆ V i o = V i o dr i f t mo nt ℎ s Where Vio drift is the measured drift value in the specified test conditions after 1000 h stress duration. The Vio final drift, in µV, to be measured on the device in real operation conditions can be computed from: (8) V i o f i n al d ri f t t o p , T op , V C C = ∆ V io , 25° C . t o p . e β . V C C − V C C n om . e E a k . 1 297 − 1 T op TSB711, TSB711A, TSB712, TSB712A, TSB714, TSB714A Long term input offset voltage drift DS12487 - Rev 6 page 19/36
VCC nom is the nominal VCC at which the ΔVio is computed (36 V for the TSB712A). Ea is the activation energy of the technology (here 0.7 eV).
5.6 EMI rejection
outputs, from 400 MHz to 2.4 GHz. Figure 44. EMIRR on In+, In- and out pins supply and output pins. These capacitances help in minimizing the impedance of these nodes at high frequencies.
5.7 Maximum power dissipation
The usable output load current drive is limited by the maximum power dissipation allowed by the device package. when the op-amp is sinks the current. can cause degradation in the parametric performance or even destroy the device.
5.8 Capacitive load and stability
high values produces gain peaking in the frequency response, with overshoot and ringing in the step response. Generally, unity gain configuration is the worst situation for stability and the ability to drive large capacitive loads. Figure 45. Stability criteria with a serial resistor at different capacitive loads
Figure 46. Test configuration for RISO
5.9 PCB layout recommendations
Particular attention must be paid to the layout of the PCB tracks connected to the amplifier, load, and power supply. The power and ground traces are critical as they must provide adequate energy and grounding for all circuits. The best practice is to use short and wide PCB traces to minimize voltage drops and parasitic inductance. In addition, to minimize parasitic impedance over the entire surface, a multi-via technique that connects the bottom and top layer ground planes together in many locations is often used. The copper traces connecting the output pins to the load and supply pins should be as wide as possible to minimize trace resistance.
5.10 Decoupling capacitor
In order to ensure op-amp full functionality, it is mandatory to place a decoupling capacitor of at least 22 nF as close as possible to the op-amp supply pin. A good decoupling helps to reduce electromagnetic interference impact. TSB711, TSB711A, TSB712, TSB712A, TSB714, TSB714A PCB layout recommendations DS12487 - Rev 6 page 23/36
6 Typical applications
6.1 Low-side current sensing
Figure 47. Low-side current sensing schematic the accuracy of the measurement.
7 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
7.1 SOT23-5 package information
Figure 48. SOT23-5 package outline Table 8. SOT23-5 package mechanical data
Package information
DS12487 - Rev 6 page 25/36
7.2 MiniSO8 package information
Figure 49. MiniSO8 package outline Table 9. MiniSO8 mechanical data
7.3 SO8 package information
Figure 50. SO8 package outline Table 10. SO-8 mechanical data
7.4 SO14 package information
Figure 51. SO14 package outline Table 11. SO14 mechanical data
- Drawing dimensions include “Single” and “Matrix” versions.
- Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed
7.5 TSSOP14 package information
Figure 52. TSSOP14 package outline Table 12. TSSOP14 mechanical data
8 Ordering information
Table 13. Order code
- Qualified and characterized according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001
Ordering information
DS12487 - Rev 6 page 30/36
Revision history
Table 14. Document revision history 23-Apr-2018 1 Initial release. Added the TSB712 as root part number; cover page has been updated accordingly. characteristics, Section 5 Application information and Table 7. Order code. Added Section 7.2 SO8 package information. Tamb = 25 °C and RL connected to VCC / 2 (unless otherwise specified) and Table 4. connected to VCC / 2 (unless otherwise specified). 18-Feb-2019 4 Updated Figure 44. Stability criteria with a serial resistor at different capacitive loads. information and Section 7.5 TSSOP14 package information.
Table 6. Electrical characteristics at VCC = 36 V, VICM = VOUT = VCC / 2, Tamb = 25 °C and RL connected to VCC / 2 (unless Table 7. Electrical characteristics at VCC = 5 V, VICM = VOUT = VCC / 2, Tamb = 25 °C and RL connected to VCC / 2 (unless