TSB571 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 31
Technical content
Datasheet sections
- 1 Package pin connections
- 2 Absolute maximum ratings and operating conditions
- 3 Electrical characteristics
- 4 Application information
- 4.1 Operating voltages
- 4.2 Input pin voltage ranges
- 4.3 Rail-to-rail input
- 4.4 Input offset voltage drift over temperature
- 4.5 Long term input of
- 4.6 Capacitive load
- 4.7 PCB layout recommendations
- 4.8 Optimized application recommendation
- 5 Package information
- 5.1 SOT23-5 package information
- 5.2 MiniSO8 package information
- 5.3 DFN8 3x3 package information
- 5.4 SO-8 package outline
- 6 Ordering information
Features
- Low-power consumption: 380 µA typ. Wide supply voltage: 4 V - 36 V
- Rail-to-rail input and output
- Gain bandwidth product: 2.5 MHz
- Low input bias current: 30 nA max.
- No phase reversal
- High tolerance to ESD: 4 kV HBM
- Extended temperature range: -40 °C to 125 °C
- Automotive grade
- Small SMD packages
- 40 V BiCMOS technology
- Enhanced stability vs. capacitive load
Applications
- Active filtering
- Audio systems
- Automotive
- Power supplies
- Industrial
- Low/high side current sensing
Description
The TSB571 (single) and TSB572 (dual) operational amplifiers offer an extended voltage operating range from 4 V to 36 V and rail-to-rail input/output. The TSB571 and TSB572 give a very good speed/power consumption ratio with a
2.5 MHz gain bandwidth product and a consumption of 380 µA typically only at 36 V
supply voltage. Stability and robustness of these devices make them an ideal solution for a wide voltage range of applications. Maturity status link TSB571, TSB572
Related products
TSB611 For below 100 µA solution TSB711 For a higher precision TSB712 Low-power, 2.5 MHz, RR IO, 36 V BiCMOS operational amplifier TSB571, TSB572 Datasheet DS11248 - Rev 7 - May 2020 For further information contact your local STMicroelectronics sales office. www .st.com
1 Package pin connections
Figure 1. Pin connections (top view) Table 1. Pin description (SOT23-5)
1 OUT Output channel
2 VCC- Negative supply voltage
3 IN1+ Non-inverting input channel
4 IN- Inverting input channel
5 VCC+ Positive supply voltage
Figure 2. Pin connections for each package (top view)
- Exposed pad can be left floating or connected to ground.
1 OUT1 Output channel 1
2 IN1- Inverting input channel 1
3 IN1+ Non-inverting input channel 1
4 VCC- Negative supply voltage
5 IN2+ Non-inverting input channel 2
6 IN2- Inverting input channel 2
7 OUT2 Output channel 2
8 VCC+ Positive supply voltage
2 Absolute maximum ratings and operating conditions
Table 3. Absolute maximum ratings
- All voltage values, except the differential voltage are with respect to network ground terminal.
Differential voltages are the non-inverting input terminal with respect to the inverting input terminal.
- V CC-Vin must not exceed 40 V, Vin must not exceed 40 V.
- Input current must be limited by a resistor in-series with the inputs.
- Short-circuits can cause excessive heating and destructive dissipation.
- According to JEDEC standard JESD22-A114F.
- According to JEDEC standard JESD22-A115A.
- According to ANSI/ESD STM5.3.1.
Table 4. Operating conditions
3 Electrical characteristics
Table 5. Electrical characteristics at Vcc = 4 V, Vicm = Vcc/2, Tamb = 25 °C, and RL connected to Vcc/2 (unless otherwise
Electrical characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit SR Positive slew rate Vin = 0.5 to 3.5 V, Av = 1, 10 % to 90 %, RL = 10 kΩ , CL = 100 pF V/μs 0.50 0.89 -40 °C < T < 125 °C 0.37 en Equivalent input noise voltage f = 1 kHz 20 nV/√Hz f = 0.1 Hz to 10 Hz 0.7 μVpp THD+N Total harmonic distortion + noise f = 1 kHz, Vin = 3.8 Vpp, RL = 10 kΩ, CL = 100 pF 0.001 % TSB571, TSB572
Table 6. Electrical characteristics at Vcc = 12 V, Vicm = Vcc/2, Tamb = 25 °C, and RL connected to Vcc/2 (unless otherwise
Symbol Parameter Conditions Min. Typ. Max. Unit SR Positive slew rate -40 °C < T < 125 °C V/μs0.40 en Equivalent input noise voltage f = 1 kHz 20 nV/√Hz f = 0.1 Hz to 10 Hz 0.7 μVpp THD+N Total harmonic distortion + noise f = 1 kHz, Vin = 7 Vpp, RL = 10 kΩ, CL = 100 pF 0.0005 % TSB571, TSB572
Table 7. Electrical characteristics at Vcc = 36 V, Vicm = Vcc/2, Tamb = 25 °C, and RL connected to Vcc/2 (unless otherwise
Symbol Parameter Conditions Min. Typ. Max. Unit SR Positive slew rate Vin = 13.5 to 22.5 V, Av = 1, 10 % to 90 %, RL = 10 kΩ, CL = 100 pF V/μs 0.60 1.00 -40 °C < T < 125 °C 0.44 en Equivalent input noise voltage f = 1 kHz 20 nV/√Hz f = 0.1 Hz to 10 Hz 0.7 μVpp THD+N Total harmonic distortion + noise f = 1 kHz, Vin = 7 Vpp, RL = 10 kΩ, CL = 100 pF 0.001 % 1. T ypical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using Arrhenius law and assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration (see Section 4.5 Section 4.5). TSB571, TSB572 DS11248 - Rev 7 page 10/31
Figure 33. THD+N vs. output voltage Figure 34. PSRR vs. frequency at VCC = 36 V Figure 35. Channel separation vs. frequency at VCC= 36 V
160 Channel Separation refered to input (dB)
DS11248 - Rev 7 page 16/31
4 Application information
4.1 Operating voltages
The TSB571 and TSB572 can operate from 4 V to 36 V. The parameters are fully specified for 4 V, 12 V, and 36 V power supplies. However, the parameters are stable in the full VCC range. Additionally , the main specifications are guaranteed in extended temperature ranges from -40 to 125 °C.
4.2 Input pin voltage ranges
The TSB571 and TSB572 have an internal ESD diode protection on the inputs. These diodes are connected between the inputs and each supply rail to protect the input transistors from electrical discharge. If the input pin voltage exceeds the power supply by 0.2 V, the ESD diodes become conductive and excessive current can flow through them. Without limitation this over current can damage the device. In this case, it is important to limit the current to 10 mA, by adding resistance on the input pin, as shown in Figure 37. Input current limitation.
4.3 Rail-to-rail input
4.4 Input offset voltage drift over temperature
the system designer to anticipate the effect of temperature variations. The maximum input voltage drift over temperature is computed using Equation 1. size ensuring a Cpk (process capability index) greater than 1.3.
Application information
DS11248 - Rev 7 page 17/31
4.5 Long term input offset voltage drift
To evaluate product reliability, two types of stress acceleration are used:
- V oltage acceleration, by changing the applied voltage
- Temperature acceleration, by changing the die temperature (below the maximum junction temperature allowed by the technology) with the ambient temperature. The voltage acceleration has been defined based on JEDEC results, and is defined using Equation 2. Equation 2 AFV e β V S VU–( ). Where: AFV is the voltage acceleration factor β is the voltage acceleration constant in 1/V, constant technology parameter ( β = 1) VS is the stress voltage used for the accelerated test VU is the voltage used for the application The temperature acceleration is driven by the Arrhenius model, and is defined in Equation 3. Equation 3 AFT e Ea TU TS Where: AFT is the temperature acceleration factor Ea is the activation energy of the technology based on the failure rate k is the Boltzmann constant (8.6173 x 10-5 eV.K-1) TU is the temperature of the die when VU is used (K) TS is the temperature of the die under temperature stress (K) The final acceleration factor , AF, is the multiplication of the voltage acceleration factor and the temperature acceleration factor (Equation 4). Equation 4 AF AFT AFV×= AF is calculated using the temperature and voltage defined in the mission profile of the product. The AF value can then be used in Equation 5 to calculate the number of months of use equivalent to 1000 hours of reliable stress duration. Equation 5 Months A F 1000 h × 12 months 24 h 365.25 days×( )×= / To evaluate the op amp reliability, a follower stress condition is used where VCC is defined as a function of the maximum operating voltage and the absolute maximum rating (as recommended by JEDEC rules). The Vio drift (in µV) of the product after 1000 h of stress is tracked with parameters at different measurement conditions (see Equation 6). Equation 6 VCC maxVop with Vicm VCC 2= = / The long term drift parameter (ΔVio), estimating the reliability performance of the product, is obtained using the ratio of the Vio (input offset voltage value) drift over the square root of the calculated number of months (Equation 7). Equation 7 TSB571, TSB572 Long term input offset voltage drift DS11248 - Rev 7 page 18/31
Where Vio drift is the measured drift value in the specified test conditions after 1000 h stress duration.
4.6 Capacitive load
with a gain peaking higher than 2.3 dB an op amp might become unstable. Generally, unity gain configuration is the worst situation for stability and the ability to drive large capacitive loads. Figure 38. Stability criteria with a serial resistor at dif using an isolation resistor, Riso. Figure 37. Stability criteria with a serial resistor at different supply voltages Figure 38. Test configuration for Riso
4.7 PCB layout recommendations
bottom and top layer ground planes together in many locations is often used.
4.8 Optimized application recommendation
It is recommended to place a 22 nF capacitor as close as possible to the supply pin. A good decoupling will help to reduce electromagnetic interference impact. TSB571, TSB572 Optimized application recommendation DS11248 - Rev 7 page 20/31
5 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
5.1 SOT23-5 package information
Figure 39. SOT23-5 package outline Table 8. SOT23-5 package mechanical data
Package information
DS11248 - Rev 7 page 21/31
5.2 MiniSO8 package information
Figure 40. MiniSO8 package outline Table 9. MiniSO8 package mechanical data
5.3 DFN8 3x3 package information
Figure 41. DFN8 3x3 package outline and mechanical data Table 10. DFN8 3x3 mechanical data
Figure 42. DFN8 3x3 footprint data
5.4 SO-8 package information
Figure 43. SO-8 package outline Table 11. SO-8 mechanical data
6 Ordering information
Table 12. Order codes
- Automotive qualification according to AEC-Q100.
Ordering information
DS11248 - Rev 7 page 26/31
Revision history
Table 13. Document revision history Date Version Changes 12-Oct-2015 1 Initial release 17-Dec-2015 2 Section 2: "Absolute maximum ratings and operating conditions": updated ESD, MM value. Section 6: "Ordering information": removed footnote (1) from order code TSB572IQ2T 26-Jun-2017 3 In Table1: "Absolute maximum ratings": - Updated Latch-up immunity Parameter V alue - updated footnote (3) 10-Nov-2017 4 Added: new SO-8 Package information and new order code TSB572IDT Section 6 26-Mar-2018 5 Updated: Section 5.2 DFN8 3x3 package information 22-Jul-2019 6 Added the root part number TSB571 and updated the whole document accordingly. 06-May-2020 7 Updated cover page TSB571, TSB572 DS11248 - Rev 7 page 27/31