TSB41BA3B

TSB41BA3B TI | Alldatasheet

Document overview

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Technical content

Features

/C0068Interface to Link-Layer Controller Supports Low-Cost Texas Instruments Bus-Holder Isolation /C0068Data Interface to Link-Layer Controller Terminal-Selectable From 1394a-2000 Mode (2/4/8 Parallel Bits at 49.152 MHz) or 1394b Mode (Eight Parallel Bits at 98.304 MHz) /C0068Interoperable With Link-Layer Controllers Using 3.3-V Supplies /C0068Interoperable With Other 1394 Physical Layers (PHYs) Using 1.8-V, 3.3-V, and 5-V Supplies /C0068Low-Cost 49.152-MHz Crystal Provides Transmit and Receive Data at 100/200/400 Mbps and Link-Layer Controller Clock at 49.152 MHz and

98.304 MHz

/C0068Separate Bias (TPBIAS) for Each Port /C0068Low-Cost, High-Performance 80-Terminal TQFP (PFP) Thermally Enhanced Package /C0068Software Device Reset (SWR) /C0068Fail-Safe Circuitry Senses Sudden Loss of Power to the Device and Disables the Ports to Ensure That the TSB41BA3B Does Not Load the TPBIAS of Any Connected Device and Blocks Any Leakage From the Port Back to Power Plane. /C00681394a-2000-Compliant, Common-Mode Noise Filter on the Incoming Bias Detect Circuit to Filter Out Crosstalk Noise /C0068Cable/Transceiver Hardware Speed and Port Mode Are Selectable by Terminal States /C0068Supports Connection to CAT5 Cable Transceiver by Allowing Ports to be Forced to Beta-Only, 100-Mbps-Only /C0068Supports Connection to S200 Plastic Optical Fiber Transceivers by Allowing Ports to be Forced to 1394b Beta-Only, S200-Mbps-Only, and S100-Mbps-Only /C0068Optical Signal Detect Input for All Ports in Beta Mode Enables Connection to Optical Transceivers /C0068Supports Use of 1394a Connectors by Allowing Ports 1 and 2 to Be Forced to 1394a-Only Mode Copyright  2005, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited. i.LINK is a trademark of Sony Kabushiki Kaisha TA Sony Corporation. FireWire is a trademark of Apple Computer, Inc. MicroStar BGA and PowerPAD are trademarks of Texas Instruments. Other trademarks are the property of their respective owners.

/C0084/C0083/C0066/C0052/C0049/C0066/C0065/C0051/C0066 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS678 − SEPTEMBER 2005

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description/ordering information The TSB41BA3B provides the digital and analog transceiver functions needed to implement a three-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB41BA3B interfaces with a link-layer controller (LLC), such as the TSB82AA2, TSB12LV21, TSB12LV26, TSB12LV32, TSB42AA4, TSB42AB4, TSB12LV01B, or TSB12LV01C. It can also be connected via cable port to an integrated 1394 Link + PHY layer such as the TSB43AB2. The TSB41BA3B is powered by a single 3.3-V supply. The core voltage supply is supplied by an internal voltage regulator to the PLLVDD-CORE and DVDD-CORE terminals. To protect the phase-locked loop (PLL) from noise, the PLLVDD-CORE terminals must be separately decoupled from the DVDD-CORE terminals. The PLLVDD-CORE terminals are decoupled with 1-µF and smaller decoupling capacitors and the DVDD-CORE terminals are separately decoupled with 1-µF and smaller decoupling capacitors. The separation between DVDD-CORE and PLLVDD-CORE must be implemented by separate power supply rails or planes. The TSB41BA3B can be powered by dual supplies, a 3.3-V supply for I/O and a core voltage supply. The core voltage supply is supplied to the PLLVDD-CORE and DVDD-CORE terminals to the requirements in the recommended operating conditions section of this data sheet. The PLLVDD-CORE terminals must be separated from the DVDD-CORE terminals, the PLLVDD-CORE terminals are decoupled with 1-µF and smaller decoupling capacitors and the DVDD-CORE terminals separately decoupled with 1-µF and smaller decoupling capacitors. The separation between DVDD-CORE and PLLVDD-CORE can be implemented by separate power supply rails, or by a single power supply rail, where the DVDD-CORE and PLLVDD-CORE are separated by a filter network to keep noise from the PLLVDD-CORE supply. The TSB41BA3B requires an external 49.152-MHz crystal to generate a reference clock. The external clock drives an internal PLL, which generates the required reference signal. This reference signal provides the clock signals that control transmission of the outbound encoded information. A 49.152-MHz clock signal is supplied by the PHY to the associated LLC for synchronization of the two devices and is used for resynchronization of the received data when operating the PHY-link interface in compliance with the IEEE 1394a-2000 standard. A 98.304-MHz clock signal is supplied by the PHY to the associated LLC for synchronization of the two devices when operating the PHY-link interface in compliance with the IEEE 1394b-2002 standard. The power-down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL. Data bits to be transmitted through the cable ports are received from the LLC on 2, 4, or 8 parallel paths (depending on the requested transmission speed and PHY-link interface mode of operation). They are latched

491.52 Mbps (referred to as S100, S100B, S200, S200B, S400, or S400B speed, respectively) as the outbound

information stream.

ORDERING INFORMATION

0°C to 70°C HTQFP - PFP TSB41BA3BPFP −40°C to 85°C HTQFP - PFP TSB41BA3BIPFP TSB41BA3I −40°C to 85°C MicroStar BGA CSP - GGM TSB41BA3BIGGM TSB41BA3I † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. MicroStar BGA is a trademark of Texas Instruments.

/C0084/C0083/C0066/C0052/C0049/C0066/C0065/C0051/C0066 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS678 − SEPTEMBER 2005 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description (continued) The PHY-link interface can follow either the IEEE 1394a-2000 protocol or the IEEE 1394b-2002 protocol. When using a 1394a-2000 LLC such as the TSB12LV26, the BMODE terminal must be deasserted. The PHY-link interface then operates in accordance with the legacy 1394a-2000 standard. When using a 1394b LLC such as the TSB82AA2, the BMODE terminal must be asserted. The PHY-link interface then conforms to the 1394b-2002 standard. The cable interface can follow either the IEEE 1394a-2000 protocol or the 1394b protocol on all ports. The mode of operation is determined by the interface capabilities of the ports being connected. When any of the three ports is connected to a 1394a-2000-compliant device, the cable interface on that port operates in the 1394a-2000 data-strobe mode at a compatible S100, S200, or S400 speed. When a bilingual port is connected to a 1394b-compliant node, the cable interface on that port operates per the 1394b-2002 standard at S100B, S200B, or S400B speed. The TSB41BA3B automatically determines the correct cable interface connection method for the bilingual ports. NOTE: The BMODE terminal does not select the cable interface mode of operation. The BMODE terminal selects the PHY-link interface mode of operation and affects the arbitration modes on the cable. When the BMODE terminal is deasserted, the PHY-link interface is placed in 1394a-2000 mode and BOSS arbitration is disabled. When the BMODE terminal is asserted, the PHY-link interface is placed in 1394b-2002 mode and BOSS arbitration is enabled. During packet reception, the serial data bits are split into 2-, 4-, or 8-bit parallel streams (depending on the indicated receive speed and the PHY-link interface mode of operation), resynchronized to the local system clock, and sent to the associated LLC. The received data is also transmitted (repeated) on the other connected and active cable ports. Both the twisted pair A (TPA) and the twisted pair B (TPB) cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration when connected to a 1394a-2000-compliant device. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during 1394a-mode arbitration and sets the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied twisted pair bias (TPBIAS) voltage. When connected to a 1394a-2000-compliant node, the TSB41BA3B provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. The PHY contains three independent TPBIAS circuits (one for each port). This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter capacitor of 1 µF. The line drivers in the TSB41BA3B are designed to work with external 112-Ω termination resistor networks in order to match the 110-Ω cable impedance. One termination network is required at each end of a twisted-pair cable. Each network is composed of a pair of series-connected ~56-Ω resistors. The midpoint of the pair of resistors that is connected to the TPA terminals is connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly connected to the TPB terminals is coupled to ground through a parallel RC network with recommended values of 5 kΩ and 270 pF. The values of the external line-termination resistors are designed to meet the standard specifications when connected in parallel with the internal receiver circuits. A precision external resistor connected between the R0 and R1 terminals sets the driver output current, along with other internal operating currents. When the power supply of the TSB41BA3B is off while the twisted-pair cables are connected, the TSB41BA3B transmitter and receiver circuitry present a high-impedance signal to the cable that does not load the device at the other end of the cable.

/C0084/C0083/C0066/C0052/C0049/C0066/C0065/C0051/C0066 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS678 − SEPTEMBER 2005

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description (continued) When the TSB41BA3B is used without one or more of the ports brought out to a connector, the twisted-pair terminals of the unused ports must be terminated for reliable operation. For each unused port, the preferred method is for the port to be forced to the 1394a-only mode (data-strobe-only mode, DS), then the TPB+ and TPB– terminals can be tied together and then pulled to ground; or the TPB+ and TPB– terminals can be connected to the suggested normal termination network. The TPA+ and TPA– terminals of an unused port can be left unconnected. The TPBIAS#_SD# terminal can be left unconnected. If the port is left in bilingual (Bi) mode, then the TPB+ and TPB– terminals can be left unconnected or the TPB+ and TPB– terminals can be connected to the suggested normal termination network. The TPA+ and TPA– terminals of an unused port can be left unconnected. The TPBIAS#_SD# terminal can be left unconnected. If the port is left in a forced 1394b Beta-only (B1, B2, or B4) mode, then the TPB+ and TPB– terminals can be left unconnected or the TPB+ and TPB– terminals can be connected to the suggested normal termination network. The TPA+ and TPA– terminals of an unused port can be left unconnected. The TPBIAS#_SD# terminal must be pulled to ground through a 1.2-kΩ or smaller resistor. To operate a port as a 1394b bilingual port, the speed/mode selections terminals (S5_LKON, S4, S3, S2_PC0, S1_PC1, and S0_PC2) need to be pulled to V CC or ground through a 1-kΩ resistor. The port must be operated in the 1394b bilingual mode whenever a 1394b bilingual or a 1394b Beta-only connector is connected to the port. T o operate the port as a 1394a-only port, the speed/mode selection terminals must be configured correctly to force 1394a-2000-only operation on that port. The only time the port must be forced to the data-strobe-only mode is if the port is connected to a 1394a connector (either 6-pin, which is recommended, or 4-pin). This mode is provided to ensure that 1394b signaling is never sent across a 1394a cable. NOTE: A bilingual port can only connect to a 1394b-only port that operates at S400b. It cannot establish a connection to a S200b or S100b port. A port that has been forced to S400b (B4) can connect to a 1394b-only port at S400b (B4) or S200b (B2) or S100b (B1). A port that has been forced to S200b can connect to a 1394b-only port at S200b or S100b. A port that has been forced to S100b can only connect to a 1394b-only port at S100b. The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, the TESTM terminal must be connected to VDD through a 1-kΩ resistor. The SE and SM terminals must be tied to ground through a 1-kΩ resistor. Three package terminals are used as inputs to set the default value for three configuration status bits in the self-ID packet. They can be pulled high through a 1-kΩ resistor or hardwired low as a function of the equipment design. In some speed/mode selections the S2_PC0, S1_PC1, and S0_PC2 terminals indicate the default power−class status for the node (the need for power from the cable or the ability to supply power to the cable); see Table 1. The contender bit in the PHY register set indicates that the node is a contender either for the isochronous resource manager (IRM) or for the bus manager (BM). On the TSB41BA3B, this bit can only be set by a write to the PHY register set. If a node is a contender for IRM or BM, then the node software must set this bit in the PHY register set. The LPS (link power status) terminal works with the S5_LKON terminal to manage the power usage in the node. The LPS signal from the LLC is used with the LCtrl bit (see Table 2 and Table 3 in the APPLICATION INFORMATION section) to indicate the active/power status of the LLC. The LPS signal also resets, disables, and initializes the PHY-LLC interface (the state of the PHY-LCC interface is controlled solely by the LPS input regardless of the state of the LCtrl bit). NOTE: The TSB41BA3B does not have a cable-not-active (CNA) terminal. To achieve a similar function, the individual PHY ports can be set up to issue interrupts whenever the port changes state. If the LPS terminal is low, then this generates a link-on (LKON) output clock. See register bits PIE, PEI, and WDIE along with the individual interrupt bits.

/C0084/C0083/C0066/C0052/C0049/C0066/C0065/C0051/C0066 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS678 − SEPTEMBER 2005 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description (continued) The LPS input is considered inactive if it remains low for more than the LPS_RESET time (see the LPS terminal definition) and is considered active otherwise. When the TSB41BA3B detects that the LPS input is inactive, the PHY-LLC interface is placed into a low-power reset state in which the CTL and D outputs are held in the logic 0 state and the LREQ input is ignored; however, the PCLK output remains active. If the LPS input remains low for more than the LPS_DISABLE time (see the LPS terminal definition), then the PHY-LLC interface is put into a low-power disabled state in which the PCLK output is also held inactive. The TSB41BA3B continues the necessary repeater functions required for normal network operation regardless of the state of the PHY-LLC interface. When the interface is in the reset or disabled state and the LPS input is again observed active, the PHY initializes the interface and returns to normal operation. The PHY-LLC interface is also held in the disabled state during hardware reset. When the LPS terminal is returned to an active state after being sensed as having entered the LPS_DISABLE time, the TSB41BA3B issues a bus reset. This broadcasts the node self-ID packet, which contains the updated L bit state (the PHY LLC now being accessible). The PHY uses the S5_LKON terminal to notify the LLC to power up and become active. When activated, the output S5_LKON signal is a square wave. The PHY activates the S5_LKON output when the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is inactive, as previously described, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet addressed to this node is received, or conditionally when a PHY interrupt occurs. The PHY deasserts the S5_LKON output when the LLC becomes active (both LPS sensed as active and the LCtrl bit set to 1). The PHY also deasserts the S5_LKON output when a bus reset occurs, unless a PHY interrupt condition exists which would otherwise cause S5_LKON to be active. If the PHY is power-cycled and the power class is 0 through 4, then the PHY asserts S5_LKON for approximately 167 µs or until both the LPS is active and the LCtrl bit is 1.

/C0084/C0083/C0066/C0052/C0049/C0066/C0065/C0051/C0066 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS678 − SEPTEMBER 2005

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DVDD−CORE SM SE CPS PLLVDD−3.3 PLLVDD−CORE PLLVDD−CORE PLLGND XI XO PLLGND AVDD AGND AGND AGND AVDD DGND DVDD−CORE S2_PC0 S1_PC1 S0_PC2 DVDD−3.3 DVDD−3.3 DVDD−CORE DGND VREG_PD BMODE RESET DGND PD TESTM SLPEN LPS 5678 PFP PACKAGE (TOP VIEW) TPB1+ 59 58 57 56 5560 54 TPA2+ TPA2− TPB2+ TPB2− TPBIAS1_SD1 TPA1+ LREQ DGND PCLK DVDD−3.3 LCLK_PMC DVDD−CORE 52 51 5053 9 10 11 12 13 49 48 1PINT TPBIAS0_SD0 47 46 45 44 14 15 16 17 DGND TPA0+ TPA0− TPBIAS2_SD2 DVDD−3.3 18 19 20 TPB0+ TPB0− 43 42 41 TPA1− TPB1− AGND CTL1 S5_LKON AVDD TSB41BA3B CTL0 AVDD AVDD AGND

/C0084/C0083/C0066/C0052/C0049/C0066/C0065/C0051/C0066 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS678 − SEPTEMBER 2005 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 terminal assignments (continued) 1098765 J H G F K 321 E D A B C TPA2+ TPA2− AGND AVDD TPB2− TPA1− TPA1+ TPBIAS1_SD1 DVDD 1.8 TBP1− TPB1+ AGND TPBIAS0_SD0 TPA0+ TPA0− AGND TPB0+ AGND TPB0− AVDD AVDD SM SE VDD 1.8 S4_DS1 S3_DS0 CPS AVDD XI PLLGND PLLVDD 1.8 PLLVDD 1.8 DGND XO PLLGND AVDD AGND VDD 3.3 PLLVDD 3.3 CTL0 LCLK_PMC VDD 3.3 PCLK LREQ S5_LKON_DS2 LPS PINT SLPEN TESTM DGND PD RESET BMODE DGND DGND VREG_PD VDD 1.8 CTL1 S1_PC1 DVDD 3.3 DVDD 3.3 VDD 1.8 DGND S2_PC0 AVDD AGND TPBIAS2_SD2 GGM PACKAGE (BOTTOM VIEW) S0_PC2 DGND TPB2+

/C0084/C0083/C0066/C0052/C0049/C0066/C0065/C0051/C0066 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS678 − SEPTEMBER 2005

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPA2− TPB2+ TPB2− TPA1+ TPA1− TPB1+ TPB1− TPB0+ TPB0− Cable Port 0 Cable Port 1 Cable Port 2 CPS LPS SLPEN PINT LCLK_PMC LREQ CTL0 CTL1 RESET S5_LKON PD BMODE Link Interface I/O Received Data Decoder/Retimer Arbitration and Control State Machine Logic Transmit Data Encoder Crystal Oscillator, PLL System, and Transmit Clock Generator PCLK S2_PC0 S1_PC1 S0_PC2 SE SM TESTM VREG_PD Voltage Regulator XI TPA0+ TPA0− Bias Voltage and Current Generator TPBIAS0_SD 0 TPBIAS1_SD 1 TPBIAS2_SD 2 XO

/C0084/C0083/C0066/C0052/C0049/C0066/C0065/C0051/C0066 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS678 − SEPTEMBER 2005 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL NAME TYPE PFP NO. GGM NO. I/O DESCRIPTION AGND Supply 21, 40, 43, 50, 61, 62 J9, A10, B8, D6, C2, C3 − Analog circuit ground terminals. These terminals must be tied together to the low-impedance circuit board ground plane. AVDD Supply 24, 39, 44, 51, 57, 63 H10, C9, C8, E6, B3, C1 − Analog circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal is suggested, such as paralleled 0.1 µF and 0.001µF. Lower frequency 10-µF filtering capacitors are also recommended. These supply terminals are separated from the PLLVDD-CORE, PLLVDD-3.3, DVDD-CORE, and DVDD-3.3 terminals internal to the device to provide noise isolation. The PLLVDD-3.3, AVDD, and DVDD-3.3 terminals must be tied together with a low dc impedance connection on the circuit board. BMODE CMOS 74 G1 I Beta-mode input. This terminal determines the PHY-link interface connection protocol. When logic-high (asserted), the PHY-link interface complies with the 1394b-2002 B PHY-link interface. When logic-low (deasserted), the PHY-link interface complies with the legacy 1394a-2000 standard. When using an LLC such as the 1394b-2002 TSB82AA2, this terminal must be pulled high. When using an LLC such as the 1394a-2000 TSB12LV26, this terminal must be tied low. NOTE: The PHY-link interface cannot be changed between the different protocols during operation. CPS CMOS 34 E8 I Cable-power status input. This terminal is normally connected to cable power through a 400-kΩ resistor. This circuit drives an internal comparator that detects the presence of cable power. This transition from cable power sensed to cable power not sensed can be used to generate an interrupt to the LLC. CTL0 CTL1 CMOS 9 I/O Control I/Os. These bidirectional signals control communication between the TSB41BA3B and the LLC. Bus holders are built into these terminals. D0−D7 CMOS 11, 12, 13, 15, 16, 17, 19, 20 K6, J6, H6, K7, J7, K8, K9, K10 I/O Data I/Os. These are bidirectional data signals between the TSB82BA3 and the LLC. Bus holders are built into these terminals. If power management control (PMC) is selected using LCLK_PMC, then some of these terminals can be used for PMC. See the LCLK_PMC terminal description for more information. DGND Supply 4, 14, 38, 64, 72, 76 H3, G7, C10, D2, F1, G3 Digital circuit ground terminals. These terminals must be tied together to the low-impedance circuit board ground plane. DVDD-CORE Supply 8, 37, 65, H4, D8, D1, E5 − Digital core circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal is suggested, such as paralleled 0.1 µF and 0.001µF. An additional 1-µF capacitor is required for voltage regulation. These supply terminals are separated from the DVDD-3.3, PLLVDD-CORE, PLLVDD-3.3, and AVDD terminals internal to the device to provide noise isolation. DVDD-3.3 Supply 6, 18, 69, J4, J8, E3, − Digital 3.3-V circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal is suggested, such as paralleled 0.1 µF and 0.001µF. Lower-frequency 10-µF filtering capacitors are also recommended. The DVDD-3.3 terminals must be tied together at a low-impedance point on the circuit board. These supply terminals are separated from the PLLVDD-CORE, PLLVDD-3.3, DVDD-CORE, and AVDD terminals internal to the device to provide noise isolation. The PLLVDD-3.3, AVDD, and DVDD-3.3 terminals must be tied together with a low dc impedance connection on the circuit board.

/C0084/C0083/C0066/C0052/C0049/C0066/C0065/C0051/C0066 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS678 − SEPTEMBER 2005

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions (Continued) TERMINAL NAME TYPE PFP NO. GGM NO. I/O DESCRIPTION LCLK_PMC CMOS 7 K4 I Link clock. Link-provided 98.304-MHz clock signal to synchronize data transfers from link to the PHY. On hardware reset, this terminal is sampled to determine the power management control (PMC) mode. LCLK_PMC LPS BMODE Mode H L H No LLC (PMC mode) n/c† lps L Legacy LLC LCLK_PMC‡ lps H Beta LLC † internal pulldown on LCLK_PMC ‡ LCLK_PMC from LLC normally low during reset In PMC mode, because no LLC is attached, the data lines (D7−D0) are available to indicate power states. In PMC mode, the following signals are output: − D0—port 0 cable-power disable (see Note 1) − D1—port 1 cable-power disable (port in sleep or disabled) − D2—port 2 cable-power disable (port in sleep or disabled) − D6—All ports cable-power disable (all ports in sleep/disable) logical AND of bits D0−D2 − D3−D5 and D7 are reserved for future use. Note 1: The cable-power disable is asserted when the port is either: − Hard-disabled (both the disabled and hard-disabled bits are set) − Sleep-disabled (both the disabled and sleep_enable bits are set) − Disconnected − Asleep − Connected in DS mode, but nonactive (that is, suspended or disabled) Otherwise, the cable-power disable output is deasserted (that is, cable power is enabled) when the port is dc-connected or active. A bus holder is built into this terminal. LPS CMOS 80 K1 I Link power status input. This terminal monitors the active/power status of the link-layer controller (LLC) and controls the state of the PHY-LLC interface. This terminal must be connected to either the VDD supplying the LLC through an approximately 1-kΩ resistor or to a pulsed output which is active when the LLC is powered. A pulsed signal must be used when an isolation barrier exists between the LLC and PHY (see Figure 8). The LPS input is considered inactive if it is sampled low by the PHY for more than an LPS_RESET time (~2.6 µs), and is considered active otherwise (that is, asserted steady high or an oscillating signal with a low time less than 2.6 µs). The LPS input must be high for at least 22 ns to be observed as high by the PHY. When the TSB41BA3B detects that the LPS input is inactive, it places the PHY-LLC interface into a low-power reset state. In the reset state, the CTL (CTL0 and CTL1) and D (D0 to D7) outputs are held in the logic 0 state and the LREQ input is ignored; however, the PCLK output remains active. If the LPS input remains low for more than an LPS_DISABLE time (~26 µs), then the PHY-LLC interface is put into a low-power disabled state in which the PCLK output is also held inactive. The LLC state that is communicated in the self-ID packet is considered active only if both the LPS input is active and the LCtrl register bit is set to 1. The LLC state that is communicated in the self-ID packet is considered inactive if either the LPS input is inactive or the LCtrl register bit is cleared to 0. LREQ CMOS 3 J3 I LLC request input. The LLC uses this input to initiate a service request to the TSB41BA3B. A bus holder is built into this terminal. PCLK CMOS 5 K3 O PHY clock. Provides a 98.304-MHz clock signal, synchronized with data transfers, to the LLC when the PHY-link interface is operating in the 1394b mode (BMODE asserted). PCLK output provides a 49.152-MHz clock signal, synchronized with data transfers, to the LLC when the PHY-link interface is in legacy 1394a-2000 (BMODE input deasserted).

/C0084/C0083/C0066/C0052/C0049/C0066/C0065/C0051/C0066 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS678 − SEPTEMBER 2005 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) TERMINAL NAME TYPE PFP NO. GGM NO. I/O DESCRIPTION PD CMOS 77 H1 I Power-down input. A high on this terminal turns off all internal circuitry. Asserting the PD input high also activates an internal pulldown on the RESET terminal to force a reset of the internal control logic. PINT CMOS 1 J2 O PHY interrupt. The PHY uses this output to serially transfer status and interrupt information to the link when PHY-link interface is in the 1394b mode. A bus holder is built into this terminal. PLLGND Supply 25, G9, − PLL circuit ground terminals. These terminals must be tied together to the low-impedance circuit board ground plane. PLLVDD-CORE Supply 29, F8, − PLL core circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal is suggested, such as paralleled 0.1 µF and 0.001 µF. An additional 1-µF capacitor is required for voltage regulation. The PLLVDD-CORE terminals must be separate from the DVDD-CORE terminals. These supply terminals are separated from the DVDD-CORE, DVDD-3.3, PLLVDD-3.3, and AVDD-3.3 terminals internal to the device to provide noise isolation. PLLVDD-3.3 Supply 31 F6 − PLL 3.3-V circuit power terminal. A combination of high-frequency decoupling capacitors near the terminal are suggested, such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering capacitors are also recommended. This supply terminal is separated from the DVDD-CORE, DVDD-3.3, PLLVDD-CORE, and AVDD-3.3 terminals internal to the device to provide noise isolation. The DVDD-3.3 terminals must be tied together at a low-impedance point on the circuit board. The PLLVDD-3.3, AVDD-3.3, and DVDD-3.3 terminals must be tied together with a low dc impedance connection. RESET CMOS 75 G2 I Logic reset input. Asserting this terminal low resets the internal logic. An internal pullup resistor to VDD is provided so only an external delay capacitor is required for proper power-up operation (see power-up reset in the APPLICATIONS INFORMATION section). The RESET terminal also incorporates an internal pulldown which is activated when the PD input is asserted high. This input is otherwise a standard logic input, and can also be driven by an open-drain-type driver. Bias 23 J10 − Current setting resistor terminals. These terminals are connected to a precision external resistance to set the internal operating currents and cable driver output currents. A resistance of 6.34 kΩ ±1% is required to meet the IEEE Std 1394-1995 output voltage limits. SE CMOS 35 D10 I Test control input. This input is used in the manufacturing test of the TSB41BA3B. For normal use, this terminal must be pulled low either through a 1-kΩ resistor to GND or directly to GND. SLPEN CMOS 79 J1 I Automotive sleep mode enable input. This terminal enables the automotive sleep mode. When deasserted (logic-low), normal 1394.b functionality is maintained. SM CMOS 36 D9 I Test control input. This input is used in the manufacturing test of the TSB41BA3B. For normal use this terminal must be pulled low either through a 1-kΩ resistor to GND or directly to GND. S2_PC0 S1_PC1 S0_PC2 CMOS 66 I Port sleep/mode selection terminals 2−0 and power-class programming. On hardware reset, this terminal when used with the other five selection terminals allows the user to select the speed and mode of the ports. See Table 1. Depending on the selection, these inputs can set the default value of the power class indicated during self-ID. Programming is done by tying the terminals high through a 1-kΩ or smaller resistor or by tying directly to ground through a 1-kΩ or smaller resistor. Bus holders are built into these terminals.

/C0084/C0083/C0066/C0052/C0049/C0066/C0065/C0051/C0066 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS678 − SEPTEMBER 2005

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions (Continued) TERMINAL NAME TYPE PFP NO. GGM NO. I/O DESCRIPTION S3 CMOS 33 E9 I Port sleep/mode selection terminal 3. On hardware reset, this terminal when used with the other five selection terminals allows the user to select the speed and mode of the ports. See Table 1. Programming is done by tying the terminals high through a 1-kΩ or smaller resistor or by tying directly to ground through a 1-kΩ or smaller resistor. A bus holder is built into this terminal. S4 CMOS 32 E10 I Port sleep/mode selection terminal 4. On hardware reset, this terminal when used with the other five selection terminals allows the user to select the speed and mode of the ports. See Table 1. Programming is done by tying the terminals high through a 1-kΩ or smaller resistor or by tying directly to ground through a 1-kΩ or smaller resistor. A bus holder is built into this terminal. S5_LKON CMOS 2 K2 I/O Port sleep/mode selection terminal 5 and link-on output. This terminal can be connected to the link-on input terminal of the LLC through a 1-kΩ resistor if the link-on input is available on the link layer. On hardware reset, this terminal when used with the other 5 selection terminals allows the user to select the speed and mode of the ports. See Table 1. A bus holder is built into this terminal. After hardware reset, this terminal is the link-on output, which notifies the LLC or other power-up logic to power up and become active. The link-on output is a square wave signal with a period of approximately 163 ns (8 PCLK cycles) when active. The link-on output is otherwise driven low, except during hardware reset when it is high-impedance. The link-on output is activated if the LLC is inactive (the LPS input inactive or the LCtrl bit cleared) and when one of the following occurs: a) The PHY receives a link-on PHY packet addressed to this node. b) The PEI (port-event interrupt) register bit is 1. c) Any of the CTOI (configuration-timeout interrupt), CPSI (cable-power-status interrupt), or STOI (state-time-out interrupt) register bits is 1 and the RPIE (resuming-port interrupt enable) register bit is also 1. d) The PHY is power-cycled and the power class is 0 through 4. Once activated, the link-on output is active until the LLC becomes active (both the LPS input active and the LCtrl bit set). The PHY also deasserts the link-on output when a bus- reset occurs unless the link-on output is otherwise active because one of the interrupt bits is set (that is, the link-on output is active due solely to the reception of a link-on PHY packet). In the case of power-cycling the PHY, the LKON signal must stop after 167 µs if the preced- ing conditions have not been met. NOTE: If an interrupt condition exists which otherwise would cause the link-on output to be activated if the LLC were inactive, then the link-on output is activated when the LLC subsequently becomes inactive. TESTM CMOS 78 H2 I Test control input. This input is used in the manufacturing test of the TSB41BA3B. For normal use this terminal must be pulled high through a 1-kΩ resistor to VDD . TPA0− TPA0+ TPB0− TPB0+ Cable 45, 46, 41, I/O Port-0 twisted-pair differential-signal terminals. Board traces from each pair of positive and negative differential signal terminals must be kept matched and as short as possible to the external load resistors and to the cable connector. Request the S800 1394b layout recommendations document from your Texas Instruments representative. TPA1− TPA1+ TPB1− TPB1+ Cable 52 I/O Port-1 twisted-pair differential-signal terminals. Board traces from each pair of positive and negative differential signal terminals must be kept matched and as short as possible to the external load resistors and to the cable connector. Request the S800 1394b layout recommendations document from your Texas Instruments representative.

/C0084/C0083/C0066/C0052/C0049/C0066/C0065/C0051/C0066 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS678 − SEPTEMBER 2005 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) TERMINAL NAME TYPE PFP NO. GGM NO. I/O DESCRIPTION TPA2− TPA2+ TPB2− TPB2+ Cable 58 I/O Port-2 twisted-pair differential-signal terminals. Board traces from each pair of positive and negative differential signal terminals must be kept matched and as short as possible to the external load resistors and to the cable connector. Request the S800 1394b layout recommendations document from your Texas Instruments representative. TPBIAS0_SD0 TPBIAS1_SD1 TPBIAS2_SD2 Cable In I/O Twisted-pair bias output and signal detect input. This provides the 1.86-V nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receivers, and for signaling to the remote nodes that there is an active cable connection in 1394a-2000 mode. Each of these terminals, except for an unused port, must be decoupled with a 1-µF capacitor to ground. For the unused port, this terminal can be left unconnected. When a port is configured as a Beta-mode port (B1, B2, B4) this terminal becomes an input and must be high when a valid signal is present. For optical transceivers, the signal detect of the transceiver must be connected to this terminal. The input is an LVCMOS level input. VREG_PD CMOS 73 F2 I Voltage regulator power-down input. When asserted logic-high, this terminal powers down the internal 3.3-V-to-1.8-V regulator. For single-supply (3.3-V only) operation, this terminal must be tied to GND. XI XO Crystal 27 F10 G10 I O Crystal oscillator inputs. These terminals connect to a 49.152-MHz parallel-resonant fundamental-mode crystal. The optimum values for the external shunt capacitors depend on the specifications of the crystal used (see the crystal selection section in the TSB41AB3 IEEE 1394a−2000 Three-Port Cable Transceiver/Arbiter data sheet, SLLS418. XI is a 1.8-V CMOS input.

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Table 1. Port Speed/Mode Selection ‡ Mode 8 must only be used to do an S100 home network translation. It must not be used as a nominal end equation mode.

/C0084/C0083/C0066/C0052/C0049/C0066/C0065/C0051/C0066 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS678 − SEPTEMBER 2005 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 port mode/speed selection example connections TSB41BA3B S5 TPBIAS0_SD0 3.3 V S4 Port 0 3.3 V POF S200 1394b 9-Pin Bilingual S3 TPBIAS1_SD1 S2_PC0 Port 1 1394a 6-Pin DS S1_PC1 TPBIAS2_SD2 S0_PC2 Port 2 PC0 (Don’t Care) 3.3 V Mode 21, Port/Speed Mode (1, 1, 0, PC0, 0, 1) TSB41BA3B S5 TPBIAS0_SD0 3.3 V S4 Port 0 3.3 V RJ45 S100 S3 TPBIAS1_SD1 S2_PC0 Port 1 1394a 6-Pin DS S1_PC1 TPBIAS2_SD2 S0_PC2 Port 2 PC0 (Don’t Care) Mode 24, Port/Speed Mode (1, 1, 1, PC0, 0, 0) POF S100 3.3 V SD High 3.3 V TSB17BA1 Transformer Signal Detect Signal Detect Signal Detect TPBIAS TPBIAS TPBIAS

/C0084/C0083/C0066/C0052/C0049/C0066/C0065/C0051/C0066 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS678 − SEPTEMBER 2005

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absolute maximum ratings over operating free-air temperature (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values, except differential I/O bus voltages, are with respect to network ground. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ‡ ABOVE T A = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING PFP § 5.05 W 52.5 mW/°C 2.69 W 1.9 W PFP ¶ 3.05 W 31.7 mW/°C 1.62 W 1.15 W PFP # 2.01 W 20.3 mW/°C 1.1 W 1.1 W GGM || 1.8 W 18.9 mW/°C 0.95 W 0.67 W ‡ This is the inverse of the traditional junction-to-ambient thermal resistance (RθJA). § 2-oz. trace and copper pad with solder. ¶ 2-oz. trace and copper pad without solder. # For more information, see the Texas Instruments application note PowerPAD  Thermally Enhanced Package, (SLMA002). ||Thermal impedance is calculated in accordance with EIA/JEDEC Standard JESD 51-7. PowerPAD is a trademark of Texas Instruments.

/C0084/C0083/C0066/C0052/C0049/C0066/C0065/C0051/C0066 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS678 − SEPTEMBER 2005 17POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions MIN TYP † MAX UNIT Supply voltage, 3.3 VDD Source power node 3 3.3 3.6 VSupply voltage, 3.3 VDD Nonsource power node 3‡ 3.3 3.6 V Supply voltage, 1.8 VDD TSB41BA3B 1.7 1.85 2 VSupply voltage, 1.8 VDD TSB41BA3BI 1.75 1.85 2 V LREQ, CTL0, CTL1, D0−D7, LCLK_PMC 2.6 High-level input voltage, VIH S5_LKON, S4, S3, S2_PC0, S1_PC1, S0_PC2, SLPEN, PD, BMODE, TPBIAS0_SD0, TPBIAS1_SD1, TPBIAS2_SD2

0.7 VDD V

RESET 0.6 VDD LREQ, CTL0, CTL1, D0−D7, LCLK_PMC 1.2 V Low-level input voltage, VIL S5_LKON, S4, S3, S2_PC0, S1_PC1, S0_PC2, SLPEN, PD, BMODE, TPBIAS0_SD0, TPBIAS1_SD1, TPBIAS2_SD2

0.2 VDD V

RESET 0.3 VDD V Output current, IOL/OH CTL0, CTL1, D0−D7, S5_LKON, PINT, PCLK −4 4 mA Output current, IO TPBIAS outputs −5.6 1.3 mA R θJA = 19°C/W, T A = 70°C 84.1 R θJA = 31.5/C0095C/W, T A = 70°C 93.3 Maximum junction temperature, TJ R θJA = 49.2/C0095C/W, T A = 70°C PFP package 106.4Maximum junction temperature, TJ (see RθJA values listed in thermal characteristics table) R θJA = 19°C/W, T A = 85°C PFP package 99.1 °C(see RθJA values listed in thermal characteristics table) R θJA = 31.5/C0095C/W, T A = 85°C 108.4 C R θJA = 49.2/C0095C/W, T A = 85°C 121.5 R θJA = 52.66/C0095C/W, TA = 85°C GGM package 124.5 1394b Differential input voltage, VID Cable inputs, during data reception 200 800 mV 1394a Differential input voltage, VID Cable inputs, during data reception 118 260 mV1394a Differential input voltage, VID Cable inputs, during arbitration 168 265 mV 1394a Common-mode input voltage, VIC TPB cable inputs, source power node 0.4706 2.515 V1394a Common-mode input voltage, VIC TPB cable inputs, nonsource power node 0.4706 2.015‡ V Power-up reset time, tpu RESET input 2§ ms TPA, TPB cable inputs, S100 operation ±1.08 1394a receive input jitter TPA, TPB cable inputs, S200 operation ±0.5 ns1394a receive input jitter TPA, TPB cable inputs, S400 operation ±0.315 ns Between TPA and TPB cable inputs, S100 operation ±0.8 1394a receive input skew Between TPA and TPB cable inputs, S200 operation ±0.55 ns1394a receive input skew Between TPA and TPB cable inputs, S400 operation ±0.5 ns † All typical values are at VDD = 3.3 V and TA = 25°C. ‡ For a node that does not source power, see Section 4.2.2.2 in IEEE 1394a-2000. § Time after valid clock received at PHY XI input terminal.

/C0084/C0083/C0066/C0052/C0049/C0066/C0065/C0051/C0066 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS678 − SEPTEMBER 2005

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electrical characteristics over recommended ranges of operating conditions (unless otherwise noted) driver PARAMETER TEST CONDITION MIN TYP MAX UNIT VOD 1394a differential output voltage 56 Ω, See Figure 1 172 265 mV VOD 1394b differential output voltage 300 700 800 mV IDIFF Driver difference current, TPA+, TPA−, TPB+, TPB−Drivers enabled, speed signaling off−1.05† 1.05† mA ISP200 Common-mode speed signaling current, TPB+, TPB−S200 speed signaling enabled −4.84‡ −2.53‡ mA ISP400 Common-mode speed signaling current, TPB+, TPB−S400 speed signaling enabled −12.4‡ −8.1‡ mA VOFF Off-state differential voltage Drivers disabled, See Figure 1 20 mV † Limits defined as algebraic sum of TPA+ and TPA− driver currents. Limits also apply to TPB+ and TPB− algebraic sum of driver currents. ‡ Limits defined as absolute limit of each of TPB+ and TPB− driver currents. receiver PARAMETER TEST CONDITION MIN TYP MAX UNIT ZID Differential impedance Drivers disabled 4 7 kΩ ZID Differential impedance Drivers disabled 4 pF ZIC Common-mode impedance Drivers disabled 20 kΩ ZIC Common-mode impedance Drivers disabled 24 pF VTH−R Receiver input threshold voltage Drivers disabled −30 30 mV VTH−CB Cable bias detect threshold, TPBx cable inputsDrivers disabled 0.6 1 V VTH + Positive arbitration comparator threshold voltageDrivers disabled 89 168 mV VTH − Negative arbitration comparator threshold voltageDrivers disabled −168 −89 mV VTH−SP200 Speed signal threshold TPBIAS−TPA common-mode voltage, drivers disabled 49 131 mV VTH−SP400 Speed signal threshold TPBIAS−TPA common-mode voltage, drivers disabled 314 396 mV device PARAMETER TEST CONDITION MIN TYP MAX UNIT IDD Supply current 3.3 VDD See Note 2 75 mA VTH Power status threshold, CPS input† 400-kΩ resistor† 4.7 7.5 V VOH High-level output voltage, CTL0, CTL1, D0−D7, PCLK, S5_LKON outputs VDD = 3 to 3.6 V, IOH = −4 mA 2.8 V VOL Low-level output voltage, CTL0, CTL1, D0−D7, PCLK, S5_LKON outputs IOL = 4 mA 0.4 V IBH+ Positive peak bus holder current, D0−D7, CTL0−CTL1, LREQ VDD = 3.6 V, VI = 0 V to VDD 0.05 1 mA IBH− Negative peak bus holder current, D0−D7, CTL0−CTL1, LREQ VDD = 3.6 V, VI = 0 V to VDD −1.0 −0.05 mA IOZ Off-state output current, CTL0, CTL1, D0−D7,VO = VDD or 0 V TSB41BA3B ±5 AIOZ Off-state output current, CTL0, CTL1, D0−D7, S5_LKON I/Os VO = VDD or 0 V TSB41BA3BI ±20 µA IIRST Pullup current, RESET input VI = 1.5 V or 0 V −90 −20 µA VO TPBIAS output voltage At rated IO current 1.665 2.015 V † Measured at cable-power side of resistor. NOTE 2: Repeat max packet (one port receiving maximum size isochronous packet—4096 bytes, sent on every isochronous interval, data value of 0x00FF 00FFh; two ports repeating; all ports with S400 Beta-mode connection), VDD3.3 = 3.3 V, internal regulator, TA = 25/C0095C

Figure 1. Test Load Diagram

/C0084/C0083/C0066/C0052/C0049/C0066/C0065/C0051/C0066 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS678 − SEPTEMBER 2005

20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION thtsu Dx, CTLx, LREQ xCLK Figure 2. Dx, CTLx, LREQ Input Setup and Hold Time Waveforms Figure 3. Dx and CTLx Output Delay Relative to xCLK Waveforms

APPLICATION INFORMATION

Obtain from the Texas Instruments Web site or your local Texas Instruments representative the reference schematics, reference layouts, debug documents, and software recommendations for the TSB41BA3B. internal register configuration The TSB41BA3B has 16 accessible internal registers. The configuration of the registers at addresses 0h through 7h (the base registers) is fixed, whereas the configuration of the registers at addresses 8h through Fh (the paged registers) depends on which of eight pages, numbered 0h through 7h, is currently selected. The selected page is set in base register 7h. Note that while this register set is compatible with 1394a-2000 register sets, some fields have been redefined, and this register set contains additional fields. Table 2 shows the configuration of the base registers, and Table 3 gives the corresponding field descriptions. The base register field definitions are unaffected by the selected page number. A reserved register or register field (marked as Reserved or Rsvd in the following register configuration tables) is read as 0, but is subject to future usage. All registers in address pages 2 through 6 are reserved.

/C0084/C0083/C0066/C0052/C0049/C0066/C0065/C0051/C0066 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS678 − SEPTEMBER 2005 21POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Table 2. Base Register Configuration

0000 Physical ID R CPS

0001 RHB IBR Gap_Count

0010 Extended (111b) Num_Ports (0011b)

0011 PHY_Speed (111b) SREN Delay (1111b)

0100 LCtrl C Jitter (000b) Pwr_Class

0101 WDIE ISBR CTOI CPSI STOI PEI EAA EMC

0110 Max Legacy SPD BLINK Bridge Rsvd

0111 Page_Select Rsvd Port_Select

Table 3. Base Register Field Descriptions tree-ID if this node becomes root. dropped below its threshold for ensured reliable operation. written using a PHY configuration packet. be changed using PHY configuration packets. PHYs must be checked on a port-by-port basis. 1394b standard only allows leaf (one port connected) nodes to be placed into standby mode. 144+(delay × 20) ns. For the TSB41BA3B, this field is Fh. The worst-case repeater delay for S100B is 538 ns.

/C0084/C0083/C0066/C0052/C0049/C0066/C0065/C0051/C0066 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS678 − SEPTEMBER 2005

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Table 3. Base Register Field Descriptions (Continued) LCtrl 1 Rd/Wr Link-active status control. This bit controls the indicated active status of the LLC reported in the self-ID packet. LLC bit in the node self-ID packet is set active only if both the LPS input is active and the LCtrl bit is set. The LCtrl bit is set to 1 by hardware reset and is unaffected by bus reset. LREQ input are processed, even if the LCtrl bit is cleared to 0. C 1 Rd/Wr Contender status. This bit indicates that this node is a contender for the bus or isochronous resource manager. hardware reset, this bit can only be set via a software register write. This bit is unaffected by a bus reset. delay, expressed as (jitter+1) × 20 ns. For the TSB41BA3B, this field is 0. input terminals on a hardware reset and is unaffected by a bus reset. See Table 1 and Table 10. interface is nonoperational. This bit is reset to 0 by hardware reset and is unaffected by bus reset. disturbance to an audio stream. NOTE: Legacy IEEE Std 1394-1995-compliant PHYs are not capable of performing short bus resets. S5_LKON output to notify the LLC to service the interrupt. includes 1394a nodes; otherwise, 1394b loop healing prevents loops from being formed in the topology. by writing a 1 to this register bit. S5_LKON output to notify the LLC to service the interrupt. occur). This bit is reset to 0 by hardware reset or by writing a 1 to this register bit. S5_LKON output to notify the LLC to service the interrupt. reset, or by writing a 1 to this register bit.

/C0084/C0083/C0066/C0052/C0049/C0066/C0065/C0051/C0066 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS678 − SEPTEMBER 2005 23POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 bit has no effect when the device is operating in 1394b mode. with isochronous traffic by excessively delaying the transmission of cycle-start packets. and is unaffected by bus reset. This bit has no effect when the device is operating in 1394b mode. same as for the PHY_SPEED field (but limited to S400 maximum). BMODE input terminal on the TSB41BA3B. when to set these bits are specified in the IEEE 1394.1 bridging specification. field is reset to 0 by a hardware reset and is unaffected by bus reset. hardware reset and is unaffected by bus reset. Table 4. Page 0 (Port Status) Register Configuration

1000 Astat Bstat Ch Con RxOK Dis

1001 Negotiated_speed PIE Fault Standby_fault Disscrm B_Only

1010 DC_connected Max_port_speed LPP Cable_speed

1011 Connection_unreliable Reserved Beta_mode Reserved

1100 Port_error

1101 Reserved Sleep_Flag Sleep_enable Loop_disable In_standby Hard_disable

1110 Reserved

1111 Reserved

/C0084/C0083/C0066/C0052/C0049/C0066/C0065/C0051/C0066 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS678 − SEPTEMBER 2005

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Table 5. Page 0 (Port Status) Register Field Descriptions encoding as the Astat field. Ch bit is invalid after a bus reset until tree-ID has completed. to 1. The Con bit is reset to 0 by hardware reset and is unaffected by bus reset. port detects connection tones from the peer PHY and operating-speed negotiation is completed. Beta mode, this bit indicates the reception of a continuous electrically valid signal. Note: RxOK is set to false during the time that only connection tones are detected in Beta mode. tones, but does not establish an active connection. Negotiated_speed 3 Rd Indicates the maximum speed negotiated between this PHY port and its immediately connected port. established during self-ID when in 1394a-2000 mode. bit to 0. This bit is reset to 0 by hardware reset and is unaffected by bus reset. to 0. When this bit is cleared, standby errors are cleared.

/C0084/C0083/C0066/C0052/C0049/C0066/C0065/C0051/C0066 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS678 − SEPTEMBER 2005 25POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Table 5. Page 0 (Port Status) Register Field Descriptions (Continued) speed (when in a Beta-only mode), but no lower than the minimum speed. 1 Rd This flag is set permanently to 1. is the same as for Max_port_speed. Connection_unreliable 1 Rd/Wr If this bit is set to 1, then a Beta-mode speed negotiation has failed or synchronization has failed. A write of 1 to this field resets the value to 0. Beta_mode is 0, then the port is active and operating in the 1394a-2000 mode. Port_error 8 Rd/Wr Incremented whenever the port receives an invalid codeword, unless the value is already 255. by a single bus-wide diagnostic program. port has been enabled for the sleep mode. be monitored on the data lines as described in the Terminal Functions table entry for LCLK_PMC. activated, then a loop would exist). Cleared on bus reset and on disconnection. In_standby 1 Rd This bit is set to 1 if the port is in standby power-management state. 1394b ac-connectivity status.

/C0084/C0083/C0066/C0052/C0049/C0066/C0065/C0051/C0066 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS678 − SEPTEMBER 2005

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The vendor identification page identifies the vendor/manufacturer and compliance level. The page is selected by writing 1 to the Page_Select field in base register 7. Table 6 shows the configuration of the vendor identification page, and Table 7 shows the corresponding field descriptions. Table 6. Page 1 (Vendor ID) Register Configuration

1000 Compliance

1001 Reserved

1010 Vendor_ID0

1011 Vendor_ID1

1100 Vendor_ID2

1101 Product_ID0

1110 Product_ID1

1111 Product_ID2

Table 7. Page 1 (Vendor ID) Register Field Descriptions Instruments) (the MSB is at register address 1010b). Product_ID 24 Rd Product identifier. For the TSB41BA3B, this field is 83_30_03h (the MSB is at register address 1101b). Table 9 shows the corresponding field descriptions. Table 8. Page 7 (Vendor-Dependent) Register Configuration

1000 Reserved Reserved

1001 Reserved for test

1010 Reserved for test

1011 Reserved for test

1100 Reserved for test

1101 Reserved for test

1110 SWR Reserved for test

1111 Reserved for test

Table 9. Page 7 (Vendor-Dependent) Register Field Descriptions asserting the RESET terminal low). This bit is always read as a 0.

/C0084/C0083/C0066/C0052/C0049/C0066/C0065/C0051/C0066 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS678 − SEPTEMBER 2005 27POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 The S2_PC0, S1_PC1, and S0_PC2 terminals can be used in some port speed/mode selections to set the default value of the power-class indicated in the pwr field (bits 21−23) of the transmitted self-ID packet. Descriptions of the various power-classes are given in Table 10. The default power-class value is loaded following a hardware reset, but is overridden by any value subsequently loaded into the Pwr_Class field in register 4. Table 10. Power-Class Descriptions 000 Node does not need power and does not repeat power. 001 Node is self-powered and provides a minimum of 15 W to the bus. 010 Node is self-powered and provides a minimum of 30 W to the bus. 011 Node is self-powered and provides a minimum of 45 W to the bus. provide power to the bus. The amount of bus power that it provides can be found in the configuration ROM. 101 Reserved for future standardization. 110 Node is powered from the bus and uses up to 3 W. An additional 3 W is needed to enable the link. 111 Node is powered from the bus and uses up to 3 W. An additional 7 W is needed to enable the link.

/C0084/C0083/C0066/C0052/C0049/C0066/C0065/C0051/C0066 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS678 − SEPTEMBER 2005

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power-class programming (continued) TPA+ TPA− TPB+ TPB− Cable Port CPS TPBIAS 56 Ω56 Ω 56 Ω56 Ω 5 kΩ 1 µF 400 kΩ 270 pF (see Note A) TSB41BA3B Cable Power Pair Cable Pair A Cable Pair B Outer Shield Termination VP VG 1 MΩ 0.1 µF 270 µF NOTE A: The IEEE Std 1394-1995 calls for a 250-pF capacitor, which is a nonstandard component value. A 270-pF capacitor is recommended. Figure 4. Typical TP Cable Connections Figure 5. Typical DC-Isolated Outer Shield Termination

/C0084/C0083/C0066/C0052/C0049/C0066/C0065/C0051/C0066 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS678 − SEPTEMBER 2005

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designing with PowerPAD devices The TSB41BA3B is housed in a high-performance, thermally enhanced, 80-terminal PFP PowerPADpackage. Use of the PowerPAD package does not require any special considerations except to note that the thermal pad, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. Therefore, if not implementing PowerPAD PCB features, the use of solder masks (or other assembly techniques) might be required to prevent any inadvertent shorting by the exposed thermal pad of connection etches or vias under the package. The recommended option, however, is to not run any etches or signal vias under the device, but to have only a grounded thermal land as explained In the following paragraphs. Although the actual size of the exposed die pad can vary, the maximum size required for the keepout area for the 80-terminal PFP PowerPAD package is 10 mm × 10 mm. The actual thermal pad size for the TSB41BA3B is 6 mm × 6 mm. It is required that there be a thermal land, which is an area of solder-tinned-copper, underneath the PowerPAD package. The thermal land varies in size, depending on the PowerPAD package being used, the PCB construction, and the amount of heat that needs to be removed. In addition, the thermal land might or might not contain numerous thermal vias depending on PCB construction. Other requirements for thermal lands and thermal vias are detailed in the Texas Instruments PowerPAD  Thermally Enhanced Package application report (SLMA002) available via the Texas Instruments Web pages at URL http://www.ti.com. Figure 9. Example of a Thermal Land for the TSB41BA3B PHY to the exposed thermal pad using standard reflow soldering techniques. information can be obtained from the Texas Instruments application report PHY Layout (SLLA020).

/C0084/C0083/C0066/C0052/C0049/C0066/C0065/C0051/C0066 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS678 − SEPTEMBER 2005 31POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 using the TSB41BA3B with a 1394-1995 or 1394a-2000 link layer The TSB41BA3B implements the PHY-LLC interface specified in the 1394b Supplement. This interface is based on the interface described in Section 17 of IEEE 1394b-2002. When using an LLC that is compliant with the IEEE 1394b-2002 interface, the BMODE input must be tied high. The TSB41BA3B also functions with an LLC that is compliant with the older 1394 standards. This interface is compatible with both the older Annex J interface specified in the IEEE Std 1394-1995 (with the exception of the Annex J isolation interfacing method) and the PHY-LLC interface specified in 1394a-2000. When using an LLC that is compliant with the IEEE 1394b-2002 interface, the BMODE input must be tied low. When the BMODE input is tied low, the TSB41BA3B implements the PHY-LLC interface specified in the 1394a-2000 Supplement. This interface is based on the interface described in informative Annex J of IEEE Std 1394-1995, which is the interface used in the oldest Texas Instruments PHY devices. The PHY-LLC interface specified in 1394a-2000 is compatible with the older Annex J. However, the TSB41BA3B does not support the Annex J isolation interfacing method. When implementing the 1394a-2000 interface, certain signals are not used: − The PINT output (terminal 1) can be left open. − The LCLK_PMC input (terminal 7) must be tied directly to ground or through a pulldown resistor of ~1 kΩ or less, unless the PMC mode is desired (see LCLK_PMC terminal description). All other signals are connected to their counterparts on the 1394a link-layer controller. The PCLK output corresponds to the SCLK input signal on most LLCs. The 1394a-2000 Supplement includes enhancements to the Annex J interface that should be comprehended when using the TSB41BA3B with a 1394-1995 LLC device. /C0068A new LLC service request was added which allows the LLC to temporarily enable and disable asynchronous arbitration accelerations. If the LLC does not implement this new service request, then the arbitration enhancements must not be enabled (see the EAA bit in PHY register 5). /C0068The capability to perform multispeed concatenation (the concatenation of packets of differing speeds) was added in order to improve bus efficiency (primarily during isochronous transmission). If the LLC does not support multispeed concatenation, then multispeed concatenation must not be enabled in the PHY (see the EMC bit in PHY register 5). /C0068In order to accommodate the higher transmission speeds expected in future revisions of the standard, 1394a-2000 extended the speed code in bus requests from 2 bits to 3 bits, increasing the length of the bus request from 7 bits to 8 bits. The new speed codes were carefully selected so that new 1394a-2000 PHY and LLC devices would be compatible, for speeds from S100 to S400, with legacy PHY and LLC devices that use the 2-bit speed codes. The TSB41BA3B correctly interprets both 7-bit bus requests (with 2-bit speed code) and 8-bit bus requests (with 3-bit speed codes). Moreover, if a 7-bit bus request is immediately followed by another request (for example, a register read or write request), then the TSB41BA3B correctly interprets both requests. Although the TSB41BA3B correctly interprets 8-bit bus requests, a request with a speed code exceeding S400 while in 1394a-2000 PHY-link interface mode results in the TSB41BA3B transmitting a null packet (data prefix followed by data end, with no data in the packet).

/C0084/C0083/C0066/C0052/C0049/C0066/C0065/C0051/C0066 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS678 − SEPTEMBER 2005

32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

To ensure proper operation of the TSB41BA3B, the RESET terminal must be asserted low for a minimum of 2 ms from the time that PHY power reaches the minimum required supply voltage and the input clock to the PHY is valid. When using a passive capacitor on the RESET terminal to generate a power-on-reset signal, the minimum reset time is ensured if the value of the capacitor satisfies the following equation (the value must be no smaller than approximately 0.1 µF): C min = 0.0077 × T + 0.085 + (external_oscillator_start-up_time × 0.05) Where Cmin is the minimum capacitance on the RESET terminal in µF, T is the VDD ramp time, 10%–90%, in ms, external_oscillator_start-up_time is the time in ms from application of power to the external oscillator until the oscillator outputs a valid clock. If a crystal is used rather than an oscillator, then the external_oscillator_start-up_time can be set to 0. For example with a 2-ms power ramp time and a 2-ms oscillator start−up time: C It is appropriate to select the nearest standard value capacitor that exceeds this value, for example 0.22 µF. Or with a 2-ms power ramp time and a 49.152-MHz fundamental crystal: C min = 0.0077 × 2 + 0.085 + (0 × 0.05) = 0.1 µF crystal selection The TSB41BA3B and other Texas Instruments PHY devices are designed to use an external 49.152-MHz crystal connected between the XI and XO terminals to provide the reference for an internal oscillator circuit. This oscillator in turn drives a PLL circuit that generates the various clocks required for transmission and resynchronization of data at the S100 through S400 media data rates. A variation of less than ±100 ppm from nominal for the media data rates is required by IEEE Std 1394. Adjacent PHYs can therefore have a difference of up to 200 ppm from each other in their internal clocks, and PHYs must be able to compensate for this difference over the maximum packet length. Larger clock variations can cause resynchronization overflows or underflows, resulting in corrupted packet data or even PHY lockup. For the TSB41BA3B, the PCLK output can be used to measure the frequency accuracy and stability of the internal oscillator and PLL from which it is derived. When operating the PHY-LLC interface with a non-1394b LLC, the frequency of the PCLK output must be within ±100 ppm of the nominal frequency of 49.152 MHz. When operating the PHY-LLC interface with a 1394b LLC, the frequency of the PCLK output must be within ±100 ppm of the nominal frequency of 98.304 MHz. The following are some typical specifications for crystals used with the physical layers from Texas Instruments in order to achieve the required frequency accuracy and stability: /C0068Crystal mode of operation: Fundamental /C0068Frequency tolerance at 25/C0095C: Total frequency variation for the complete circuit is ±100 ppm. A crystal with ±30 ppm frequency tolerance is recommended for adequate margin. /C0068Frequency stability (over temperature and age): A crystal with ±30 ppm frequency stability is recommended for adequate margin.

/C0084/C0083/C0066/C0052/C0049/C0066/C0065/C0051/C0066 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS678 − SEPTEMBER 2005 33POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 crystal selection (continued) NOTE: The total frequency variation must be kept below ±100 ppm from nominal with some allowance for error introduced by board and device variations. Trade-offs between frequency tolerance and stability can be made as long as the total frequency variation is less than ±100 ppm. For example, the frequency tolerance of the crystal can be specified at 50 ppm, and the temperature tolerance can be specified at 30 ppm to give a total of 80 ppm possible variation due to the oscillator alone. Aging also contributes to the frequency variation. /C0068Load capacitance: For parallel resonant mode crystal circuits, the frequency of oscillation depends on the load capacitance specified for the crystal. Total load capacitance (CL) is a function of not only the discrete load capacitors, but also board layout and circuit. It might be necessary to select discrete load capacitors iteratively until the PCLK output is within specification. It is recommended that load capacitors with a maximum of ±5% tolerance be used. As an example, for the OHCI + 41LV03 evaluation module (EVM), which uses a crystal specified for 12-pF loading, load capacitors (C9 and C10 in Figure 10) of 16 pF each were appropriate for the layout of that particular board. The load specified for the crystal includes the load capacitors (C9, C10), the loading of the PHY terminals PHY ), and the loading of the board itself (CBD ). The value of CPHY is typically about 1 pF and CBD is typically 0.8 pF per centimeter of board etch; a typical board can have 3 pF to 6 pF or more. The load capacitors C9 and C10 combine as capacitors in series so that the total load capacitance is: C L /C0043C9 /C0032C10 C9 /C0041C10 /C0041C PHY /C0041C BD

49.152 MHzIS

Figure 10. Load Capacitance for the TSB41BA3B PHY as possible to the PHY XI and XO terminals to minimize trace lengths.

/C0084/C0083/C0066/C0052/C0049/C0066/C0065/C0051/C0066 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS678 − SEPTEMBER 2005

34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

crystal selection (continued) C9 C10 Figure 11. Recommended Crystal and Capacitor Layout done to both load capacitors (C9 and C10 in Figure 11) at the same time, and both must be of the same value. Additional design details and requirements can be provided by the crystal vendor. any of the other writeable bits in this register when the ISBR bit is written to. the IBR bit is written, the RHB and gap-count register are also necessarily written. 1394-1995-compliant PHYs which decode only received PHY configuration packets. just loaded by the write to PHY register 1.

/C0084/C0083/C0066/C0052/C0049/C0066/C0065/C0051/C0066 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS678 − SEPTEMBER 2005 35POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 bus reset (continued) Therefore, in order to maintain consistent gap-count registers throughout the bus, the following rules apply to the use of the IBR bit, RHB, and gap-count register in PHY register 1: /C0068Following the transmission of a PHY configuration packet, a bus reset must be initiated in order to verify that all nodes have correctly updated their RHBs and gap-count register values, and to ensure that a subsequent new connection to the bus causes the gap-count register to be set to 63 on all nodes in the bus. If this bus reset is initiated by setting the IBR bit to 1, then the RHB and gap-count register must also be loaded with the correct values consistent with the just-transmitted PHY configuration packet. In the TSB41BA3B, the RHB and gap-count register have been updated to their correct values on the transmission of the PHY configuration packet and so these values can first be read from register 1 and then rewritten. /C0068Other than to initiate the bus reset, which must follow the transmission of a PHY configuration packet, whenever the IBR bit is set to 1 in order to initiate a bus reset, the gap-count register value must also be set to 63 so as to be consistent with other nodes on the bus, and the RHB must be maintained with its current value. /C0068The PHY register 1 must not be written to except to set the IBR bit. The RHB and gap-count register must not be written without also setting the IBR bit to 1. /C0068To avoid these problems, all bus resets initiated by software must be initiated by writing the ISBR bit (bit 1 PHY register 0101b). Care must be taken to not change the value of any of the other writeable bits in this register when the ISBR bit is written to. Also, the only means to change the gap count of any node must be by means of the PHY configuration packet, which changes all nodes to the same gap count.

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the operation of the PHY-LLC interface. This interface is formally defined in IEEE 1394a-2000, Section 5A. the TSB41BA3B, as shown in Figure 12. Figure 12. PHY-LLC Interface of 1394a-2000-compliant PHY devices. between the TSB41BA3B and LLC. operations. When the LLC is in control of the D0−D7 bus, unused Dn terminals are ignored by the TSB41BA3B. to the serial bus for packet transmission, read or write PHY registers, or control arbitration acceleration. LLC when either LPS is inactive or the PHY register L bit is 0. these buses only after the LLC has been granted permission to do so by the PHY.

of the serial bus in order to transmit a packet, or to control arbitration acceleration. The PHY initiates a receive operation whenever a packet is received from the serial bus. The PHY initiates a transmit operation after winning control of the serial bus following a bus request by the LLC. The transmit operation is initiated when the PHY grants control of the interface to the LLC. Table 11 and Table 12 show the encoding of the CTL0−CTL1 bus. Table 11. CTL Encoding When PHY Has Control of the Bus 0 1 Status Status information is being sent from the PHY to the LLC. 1 0 Receive An incoming packet is being sent from the PHY to the LLC. 1 1 Grant The LLC has been given control of the bus to send an outgoing packet. Table 12. CTL Encoding When LLC Has Control of the Bus 0 0 Idle The LLC releases the bus (transmission has been completed). be transmitted (concatenated) without arbitrating. 1 0 Transmit An outgoing packet is being sent from the LLC to the PHY. a serial bit stream on the LREQ terminal as shown in Figure 13. Each cell represents one clock sample period, and n is the number of bits in the request stream. Figure 13. LREQ Request Stream

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The length of the stream varies depending on the type of request as shown in Table 13. Table 13. Request Stream Bit Length stream. The LREQ terminal is normally low. Table 14 shows the encoding for the request type. Table 14. Request Type Encoding 000 ImmReq Immediate bus request. On detection of idle, the PHY takes control of the bus immediately without arbitration. 001 IsoReq Isochronous bus request. On detection of idle, the PHY arbitrates for the bus without waiting for a subaction gap. 010 PriReq Priority bus request. The PHY arbitrates for the bus after a subaction gap, ignores the fair protocol. 011 FairReq Fair bus request. The PHY arbitrates for the bus after a subaction gap, follows the fair protocol. 100 RdReg The PHY returns the specified register contents through a status transfer.

101 WrReg Write to the specified register

110 AccelCtl Enable or disable asynchronous arbitration acceleration

111 Reserved Reserved

For a bus request, the length of the LREQ bit stream is 7 or 8 bits as shown in Table 15. Table 15. Bus Request

0 Start bit Indicates the beginning of the transfer (always 1)

1−3 Request type Indicates the type of bus request. See Table 14. 4−6 Request speed Indicates the speed at which the PHY sends the data for this request. See Table 16 for the encoding of this field. 7 Stop bit Indicates the end of the transfer (always 0). If bit 6 is 0, then this bit can be omitted. Table 16 shows the 3-bit request speed field used in bus requests. Table 16. Bus Request Speed Encoding

000 S100

010 S200

100 S400

data presented by the LLC and transmits a null packet. For a read register request, the length of the LREQ bit stream is 9 bits as shown in Table 17. Table 17. Read Register Request 1−3 Request type A 100 indicates this is a read register request.

8 Stop bit Indicates the end of the transfer (always 0)

For a write register request, the length of the LREQ bit stream is 17 bits as shown in Table 18. Table 18. Write Register Request 1−3 Request type A 101 indicates this is a write register request.

16 Stop bit Indicates the end of the transfer (always 0)

For an acceleration control request, the length of the LREQ data stream is 6 bits as shown in Table 19. Table 19. Acceleration Control Request 1−3 Request type A 110 indicates this is an acceleration control request.

4 Control Asynchronous period arbitration acceleration is enabled if 1 and disabled if 0

5 Stop bIt Indicates the end of the transfer (always 0)

clock after the next interface idle. an isochronous request only when the serial bus has been won.

/C0084/C0083/C0066/C0052/C0049/C0066/C0065/C0051/C0066 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0098 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS678 − SEPTEMBER 2005

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PRINCIPLES OF OPERATION (1394a-2000 INTERFACE) LLC service request (continued) To send an acknowledge packet, the LLC must issue an immediate bus request (ImmReq) during the reception of the packet addressed to it. This is required in order to minimize the idle gap between the end of the received packet and the start of the transmitted acknowledge packet. As soon as the receive packet ends, the PHY immediately grants control of the bus to the LLC. The LLC sends an acknowledgment to the sender unless the header CRC of the received packet is corrupted. In this case, the LLC does not transmit an acknowledge, but instead cancels the transmit operation and releases the interface immediately; the LLC must not use this grant to send another type of packet. After the interface is released, the LLC can proceed with another request. The LLC can make only one bus request at a time. Once the LLC issues any request for bus access (ImmReq, IsoReq, FairReq, or PriReq), it cannot issue another bus request until the PHY indicates that the bus request was lost (bus arbitration lost and another packet received), or won (bus arbitration won and the LLC granted control). The PHY ignores new bus requests while a previous bus request is pending. All bus requests are cleared on a bus reset. For write register requests, the PHY loads the specified data into the addressed register as soon as the request transfer is complete. For read register requests, the PHY returns the contents of the addressed register to the LLC at the next opportunity through a status transfer. If a received packet interrupts the status transfer, then the PHY continues to attempt the transfer of the requested register until it is successful. A write or read register request can be made at any time, including while a bus request is pending. Once a read register request is made, the PHY ignores further read register requests until the register contents are successfully transferred to the LLC. A bus reset does not clear a pending read register request. The TSB41BA3B includes several arbitration acceleration enhancements, which allow the PHY to improve bus performance and throughput by reducing the number and length of interpacket gaps. These enhancements include autonomous (fly-by) isochronous packet concatenation, autonomous fair and priority packet concatenation onto acknowledge packets, and accelerated fair and priority request arbitration following acknowledge packets. The enhancements are enabled when the EAA bit in PHY register 5 is set. The arbitration acceleration enhancements can interfere with the ability of the cycle master node to transmit the cycle start message under certain circumstances. The acceleration control request is therefore provided to allow the LLC temporarily to enable or disable the arbitration acceleration enhancements of the TSB41BA3B during the asynchronous period. The LLC typically disables the enhancements when its internal cycle counter rolls over, indicating that a cycle-start message is imminent, and then re-enables the enhancements when it receives a cycle-start message. The acceleration control request can be made at any time and is immediately serviced by the PHY. Additionally, a bus reset or isochronous bus request causes the enhancements to be re-enabled, if the EAA bit is set.

been successfully transmitted. At least one idle cycle occurs between consecutive status transfers. transfer has not yet completed. Table 20 shows the definition of the bits in the status transfer, and Figure 14 shows the timing. Table 20. Status Bits the IEEE 1394a-2000 standard). This bit is used by the LLC in the busy/retry state machine. IEEE 1394a-2000 standard). This bit is used by the LLC to detect the completion of an isochronous cycle.

2 Bus reset Indicates that the PHY has entered the bus reset state

cable-power voltage falling too low, a state time-out, or a port status change. 4−7 Address This field holds the address of the PHY register whose contents are being transferred to the LLC. 8−15 Data This field holds the register contents. Figure 14. Status Transfer Timing

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to be sent in addition to any status information. (b) Status transfer terminated. The PHY normally terminates a status transfer by asserting idle on the CTL lines. receive operation. The PHY asserts at least one idle cycle between consecutive status transfers. not included in the calculation of CRC or any other data protection mechanisms. code or terminating the receive operation. to the LLC. This packet is transferred to the LLC just as any other received self-ID packet. Figure 15. Normal Packet Reception Timing

(a) Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines. that which the link is capable of handling, then the link must ignore the subsequent data. on the D lines with receive on the CTL lines for the remainder of the receive operation. (e) Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines. The PHY asserts at least one idle cycle following a receive operation. Figure 16. Null Packet Reception Timing (a) Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines. (b) Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more cycles. (c) Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines. The PHY asserts at least one idle cycle following a receive operation. Table 21. Receive Speed Codes

0100 XXXX S200

NOTE: X = Output as 0 by PHY, ignored by LLC. Y = Output as 1 by PHY, ignored by LLC.

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When the LLC issues a bus request through the LREQ terminal, the PHY arbitrates to gain control of the bus. then takes control of the bus by asserting either idle (00b), hold (01b) or transmit (10b) on the CTL terminals. high-impedance state. The PHY then regains control of the interface bus. speed code that precedes received packet data as given in Table 21. Figure 17. Normal Packet Transmission Timing

(that is, it places its CTL and D outputs in a high-impedance state) following the idle cycle. (b) Optional idle cycle. The link can assert at most one idle cycle preceding assertion of either hold or transmit. This idle cycle is optional; the link is not required to assert idle preceding either hold or transmit. hold cycle(s) are optional; the link is not required to assert hold preceding transmit. cycle before releasing the interface and returning control to the PHY. Table 21). The link cannot concatenate an S100 packet onto any higher-speed packet. transfer, receive operation, or transmit operation. Figure 18. Cancelled/Null Packet Transmission

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is optional; the link is not required to assert idle preceding hold. cycle(s) are optional; the link is not required to assert hold preceding idle. cycles are asserted. This ensures that either the link or PHY controls the interface in all cycles. transfer, receive operation, or transmit operation. interface to normal operation. signal. Timing parameters for the LPS signal are given in Table 22. Table 22. LPS Timing Parameters requirements of 1394a-2000 operates correctly with the TSB41BA3B).

1. A pulsed LPS signal must have a duty cycle (ratio of tLPSH to cycle period) in the specified range to ensure proper operation when

using an isolation barrier on the LPS signal (for example, as shown in Figure 8).

on the LREQ signal. Figure 19 shows the timing for interface reset. Figure 19. Interface Reset bus activity, places its CTL and D outputs into the high-impedance state, and drives its LREQ output low. bus activity, and drives its CTL and D outputs low. The PHY-LLC interface is now in the reset state. asserted, the interface is initialized as described in the following paragraph. the timing for the interface disable. When the interface is disabled, the PHY enters a low-power state if none of its ports are active.

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Figure 20. Interface Disable reception and transmission via the CTL and D lines, and request activity via the LREQ line. bus activity, places its CTL and D outputs into a high-impedance state, and drives its LREQ output low. bus activity, and drives its CTL and D outputs low. The PHY-LLC interface is now in the reset state. activity by driving the PCLK output low. The PHY-LLC interface is now in the disabled state. operation when LPS is reasserted by the LLC. Figure 21 shows the timing for interface initialization.

7 Cycles

Figure 21. Interface Initialization of 20.345 ns). During the first 7 cycles of PCLK, the PHY continues to drive the CTL and D terminals low. state on the CTL lines and the data-on indication (all 1s) on the D lines for one or more cycles. PHY now accepts requests from the LLC via the LREQ line.

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interface is formally specified in the IEEE 1394b-2002 standard. S5_LKON terminals on the TSB41BA3B, as shown in Figure 22. Figure 22. PHY-LLC Interface and is phase-locked to the PCLK signal. All LLC to PHY transfers are synchronous to LCLK_PMC. are synchronized to the rising edge of PCLK. between the TSB41BA3B and LLC. the D0−D7 data bus. In S400B, S200B, and S100B operation, all Dn terminals are used. on LREQ is synchronous to LCLK_PMC. LPS is inactive or the PHY register L bit is 0. The PINT terminal is used by the PHY for the serial transfer of status, interrupt, and other information to the LLC.

these buses only after the LLC has been granted permission to do so by the PHY. control of the serial bus in order to transmit a packet. The PHY initiates a receive operation whenever a packet is received from the serial bus. The PHY initiates a transmit operation after winning control of the serial bus following a bus request by the LLC. The transmit operation is initiated when the PHY grants control of the interface to the LLC. Table 23 and Table 24 show the encoding of the CTL0−CTL1 bus. Table 23. CTL Encoding When PHY Has Control of the Bus 0 1 Status Status information is being sent from the PHY to the LLC. 1 0 Receive An incoming packet is being sent from the PHY to the LLC. 1 1 Grant The LLC has been given control of the bus to send an outgoing packet. Table 24. CTL Encoding When LLC Has Control of the Bus 0 0 Idle The LLC releases the bus (transmission has been completed). 0 1 Transmit An outgoing packet is being sent from the LLC to the PHY. arbitrate for access to the bus, or the LLC is identifying the end of a subaction gap to the PHY. a serial bit stream on the LREQ terminal as shown in Figure 23. Each cell represents one clock sample period, and n is the number of bits in the request stream. Figure 23. LREQ Request Stream The length of the stream varies depending on the type of request as shown in Table 25.

52 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Table 25. Request Stream Bit Length stream. The LREQ terminal is normally low. Table 27 shows the encoding for the request type. Table 27. Request Type Encoding

0000 Reserved Reserved

0001 Immed_Req Immediate request. On detection of idle, the PHY arbitrates for the bus.

0101 Reserved Reserved

1000 Cyc_Start_Req Cycle start request. The PHY arbitrates for the bus to send a cycle start packet.

1001 Reserved Reserved

1010 Reg_Read Register read request. The PHY returns the specified register contents through a status transfer. 1011 Reg_Write Register write request. Write to the specified register in the PHY. 1) A cycle start packet has been received. 2) The link has set the isochronous phase to even. 1) A cycle start packet has been received. 2) The link has set the isochronous phase to odd. 1110 Cycle_Start_Due Cycle start due notification. The link reports to the PHY that a cycle start packet is due for reception.

1111 Reserved Reserved

For a bus request, the length of the LREQ bit stream is 11 bits as shown in Table 28.

Table 28. Bus Request 1−4 Request type Indicates the type of bus request. See Table 27. 5 Request format Indicates the packet format to be used for packet transmission. See Table 29. 6−9 Request speed Indicates the speed at which the link sends the data to the PHY. See Table 30 for the encoding of this field. 10 Stop bit Indicates the end of the transfer (always 0). If bit 6 is 0, then this bit can be omitted. Table 29 shows the 1-bit request format field used in bus requests. Table 29. Bus Request Format Encoding

0 Link does not request either Beta or legacy packet format for bus transmission

1 Link requests Beta packet format for bus transmission

Table 30 shows the 4-bit request speed field used in bus requests. Table 30. TBus Request Speed Encoding

0000 S100

0001 Reserved

0010 S200

0011 Reserved

0100 S400

0101 Reserved

0110 S800

data presented by the LLC and transmits a null packet. For a read register request, the length of the LREQ bit stream is 10 bits as shown in Table 31. Table 31. Read Register Request 1−4 Request type A 1010 indicates this is a read register request.

9 Stop bit Indicates the end of the transfer (always 0)

54 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

For a write register request, the length of the LREQ bit stream is 18 bits as shown in Table 32. Table 32. Write Register Request 1−4 Request type A 1011 indicates this is a write register request.

17 Stop bit Indicates the end of the transfer (always 0)

For a link notification request, the length of the LREQ bit stream is 6 bits as shown in Table 33. Table 33. Link Notification Request (CTL terminals are asserted to the receive state, 10b) of a packet, queued requests are not cleared by the PHY. PHY clears an isochronous request only when the serial bus has been won. clear a pending read register request.

PHY interface reset operation, the PHY-link interface is reset on the following PCLK cycle. Table 34 shows the definition of the bits during the bus status transfer and Figure 24 shows the timing. Table 34. Status Bits Figure 24. Bus Status Transfer Timing

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PHY status transfers use the PINT terminal to send status information serially to the LLC as shown in Figure 25. INTERFACE_ERROR PHY status transfer. Each cell represents one clock sample period, and n is the number of bits in the request stream. Figure 25. PINT (PHY Interrupt) Stream Table 35. PHY Status Transfer Encoding

000 NOP No status indication 5

001 PHY_INTERRUPT Interrupt indication: configuration time-out, cable-power failure, port event

010 PHY_REGISTER_SOL Solicited PHY register read 17

011 PHY_REGISTER_UNSOL Unsolicited PHY register read 17

111 Reserved Reserved Reserved

additional information of the register address and the data contents of the register (see Table 36). Table 36. Register Read (Solicited and Unsolicited) PHY Status Transfer Encoding 1−3 Request type A 010 or a 011 indicates a solicited or unsolicited register contents transfer.

in the calculation of CRC or any other data protection mechanisms. during the data-on indication does not need to be preceded or followed by a data-on indication. terminating the receive operation. to the LLC. This packet it transferred to the LLC just as any other received self-ID packet. Figure 26. Normal Packet Reception Timing

58 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

NOTE A: SPD = speed code, see Table 37. d0–dn = packet data. STATUS = status bits, see Table 34. Figure 27. Normal Packet Reception Timing With Optional Bus Status Transfer (a) Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines. that which the link is capable of handling, then the link must ignore the subsequent data. on the D lines with receive on the CTL lines for the remainder of the receive operation. (e) Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines. The PHY asserts at least one idle cycle following a receive operation. Figure 28. Null Packet Reception Timing

(a) Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines. (b) Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more cycles. (c) Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines. The PHY asserts at least one idle cycle following a receive operation. Table 37. Receive Speed Codes and Format NOTE: Y = Output as 1 by PHY, ignored by LLC. X = Output as 0 by PHY, ignored by LLC. When the LLC issues a bus request through the LREQ terminal, the PHY arbitrates to gain control of the bus. LLC need not assert hold before transmit). During the hold state, the LLC is expected to drive the D lines to 0. The PHY asserts data-prefix on the serial bus during this time.

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00 GT 00 ZZ ZZ ZZ ZZ ZZZZ

Figure 29. Transmit Packet Timing With Optional Link Request subaction, then the LLC sets D4 during the hold state at the end of packet transmission.

Table 38. Link Request Type Encoding During Packet Transmission

000 No request

001 Isoch_Req_Odd

010 Isoch_Req_Even

011 Current

100 Next_Even

101 Next_Odd

110 Cyc_Start_Req

111 Reserved

Table 39. Link Request Speed Code Encoding During Packet Transmission

00 S100

01 S200

10 S400

11 S800

Table 40. Link Request Format Encoding During Packet Transmission 0 Link does not request either Beta or legacy packet format for bus transmission. 1 Link requests Beta packet format for bus transmission. Table 41. Subaction End Notification Encoding During Packet Transmission 0 Transmitted packet does not represent end of a subaction. 1 Transmitted packet marks the end of a subaction. Table 42. Format Type During Grant Cycle

0 Unspecified

1 Beta format

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Table 43. Grant Type Values During Grant Cycle

000 Reserved

001 Reserved

010 Isochronous grant

011 Reserved

100 Reserved

101 Asynchronous grant

110 Cycle start grant

111 Immediate grant

Table 44. Speed Type Values During Grant Cycle

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TSB41BA3BPFP ACTIVE HTQFP PFP 80 96 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 5-Feb-2007 Addendum-Page 1

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