TSB41AB3PFP

TSB41AB3_14 TI1 | Alldatasheet

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/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0051 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS418I − JUNE 2000 − REVISED DECEMBER 2004 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 /C0068Fully Supports Provisions of IEEE 1394-1995 Standard for High Performance Serial Bus † and the 1394a-2000 Supplement /C0068Fully Interoperable With FireWire and i.LINK Implementation of IEEE Std 1394 /C0068Fully Compliant With Open HCI Requirements /C0068Provides Three 1394a-2000 Fully Compliant Cable Ports at 100/200/400 Megabits Per Second (Mbits/s) /C0068Full 1394a-2000 Support Includes: Connection Debounce, Arbitrated Short Reset, Multispeed Concatenation, Arbitration Acceleration, Fly-By Concatenation, Port Disable/Suspend/Resume /C0068Extended Resume Signaling for Compatibility With Legacy DV Devices /C0068Power-Down Features to Conserve Energy in Battery Powered Applications Include: Automatic Device Power Down During Suspend, Device Power-Down Terminal, Link Interface Disable via LPS, and Inactive Ports Powered Down /C0068Ultralow-Power Sleep Mode /C0068Node Power Class Information Signaling for System Power Management /C0068Cable Power Presence Monitoring /C0068Cable Ports Monitor Line Conditions for Active Connection to Remote Node. /C0068Register Bits Provide Software Control of Contender Bit, Power Class Bits, Link Active Control Bit and 1394a-2000 Features. /C0068Data Interface to Link-Layer Controller Through 2/4/8 Parallel Lines at 49.152 MHz /C0068Interface to Link Layer Controller Supports Low-Cost TI Bus-Holder Isolation and Optional Annex J Electrical Isolation /C0068Interoperable With Link-Layer Controllers Using 3.3-V and 5-V Supplies /C0068Interoperable With Other Physical Layers (PHYs) Using 3.3-V and 5-V Supplies /C0068Low-Cost 24.576-MHz Crystal Provides Transmit Receive Data at 100/200/400 Mbits/s, and Link-Layer Controller Clock at 49.152 MHz. /C0068Separate Cable Bias (TPBIAS) for Each Port /C0068Single 3.3-V Supply Operation /C0068Low-Cost High Performance 80-Pin TQFP (PFP) Thermally Enhanced Package /C0068Direct Drop-In Upgrade for TSB41LV03APFP and TSB41LV03PFP /C0068Software Device Reset (SWR) /C0068Fail-Safe Circuitry Senses Sudden Loss of Power to the Device and Disables the Ports to Ensure That the TSB41AB3 Does Not Load the TPBIAS of Any Connected Device and Blocks Any Leakage From the Port Back to Power Plane. /C0068The TSB41AB3 Has a 1394a-Compliant Common-Mode Noise Filter on the Incoming Bias Detect Circuit to Filter Out Crosstalk Noise. Copyright  2004, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 †Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited. i.LINK is a trademark of Sony Corporation FireWire is a trademark of Apple Computer, Incorporated.

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0051 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS418I − JUNE 2000 − REVISED DECEMBER 2004

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

description

The TSB41AB3 provides the digital and analog transceiver functions required to implement a three-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB41AB3 is designed to interface with a line layer controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23, TSB12LV26, TSB12LV31, TSB12LV41, TSB12LV42, or TSB12LV01A. The TSB41AB3 requires only an external 24.576-MHz crystal as a reference. An external clock may be used instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates the required 393.216-MHz reference signal. This reference signal is internally divided to provide the clock signals used to control transmission of the outbound encoded strobe and data information. A 49.152-MHz clock signal is supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of the received data. The power-down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL. The TSB41AB3 supports an optional isolation barrier between itself and its LLC. When the ISO input terminal is tied high, the LLC interface outputs behave normally. When the ISO terminal is tied low, internal differentiating logic is enabled, and the outputs are driven such that they can be coupled through a capacitive or transformer galvanic isolation barrier as described in Annex J of IEEE Std 1394-1995 and in the 1394a-2000 Supplement (section 5.9.4) (hereinafter referred to as Annex J type isolation). To operate with TI bus holder isolation, the ISO terminal on the PHY must be high. Data bits to be transmitted through the cable ports are received from the LLC on two, four, or eight parallel paths (depending on the requested transmission speed). They are latched internally in the TSB41AB3 in synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded, and transmitted at 98.304, 196.608, or 392.216 Mbits/s (referred to as S100, S200, and S400 speed, respectively) as the outbound data-strobe information stream. During transmission, the encoded data information is transmitted differentially on the TPB cable pair(s), and the encoded strobe information is transmitted differentially on the TPA cable pair(s). During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The serial data bits are split into two-, four-, or eight-bit parallel streams (depending upon the indicated receive speed), resynchronized to the local 49.152-MHz system clock, and sent to the associated LLC. The received data is also transmitted (repeated) on the other active (connected) cable ports. Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied twisted-pair bias voltage. The TSB41AB3 provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. The PHY contains three independent TPBIAS circuits. This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter capacitor of 1 µF. The line drivers in the TSB41AB3, operating in a high-impedance current mode, are designed to work with external 112-Ω line-termination resistor networks in order to match the 110-Ω cable impedance. One network is provided at each end of a twisted-pair cable. Each network is composed of a pair of series-connected 56-Ω resistors. The midpoint of the pair of resistors that is directly connected to the twisted-pair A terminals is

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0051 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS418I − JUNE 2000 − REVISED DECEMBER 2004 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 description (continued) connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly connected to the twisted-pair B terminals is coupled to ground through a parallel R-C network with recommended values of 5 kΩ and 220 pF. The values of the external line-termination resistors are designed to meet the standard specifications when connected in parallel with the internal receiver circuits. An external resistor connected between the R0 and R1 terminals sets the driver output current, along with other internal operating currents. This current setting resistor has a value of 6.34 kΩ ±1%. When the power supply of the TSB41AB3 is off while the twisted-pair cables are connected, the TSB41AB3 transmitter and receiver circuitry presents a high-impedance signal to the cable and does not load the TPBIAS voltage at the other end of the cable. When the TSB41AB3 is used without one or more of the ports brought out to a connector, the twisted-pair terminals of the unused ports must be terminated for reliable operation. For each unused port, the TPB+ and TPB− terminals can be tied together and then pulled to ground through a 1-kΩ resistor, or the TPB+ and TPB− terminals can be connected to the suggested termination network. The TPA+ and TPA− terminals of an unused port can be left unconnected. The TPBIAS terminal can be connected through a 1-µF capacitor to ground or left floating. The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, it is recommended that the TESTM terminal be connected to V DD through a 1-kΩ resistor, and SE be tied to ground through a 1-kΩ resistor, while SM is connected directly to ground. Four package terminals are used as inputs to set the default value for four configuration status bits in the self-ID packet and are tied high through a 1-kΩ resistor or hardwired low as a function of the equipment design. The PC0–PC2 terminals are used to indicate the default power-class status for the node (the need for power from the cable or the ability to supply power to the cable). See Table 9 for power-class encoding. The C/LKON terminal is used as an input to indicate that the node is a contender either for isochronous resource manager (IRM) or for bus manager (BM). The TSB41AB3 supports suspend/resume as defined in the IEEE 1394a-2000 specification. The suspend mechanism allows pairs of directly-connected ports to be placed into a low-power conservation state (suspended state) while maintaining a port-to-port connection between 1394 bus segments. While in the suspended state, a port is unable to transmit or receive data transaction packets. However, a port in the suspended state is capable of detecting connection status changes and detecting incoming TPBias. When all three ports of the TSB41AB3 are suspended, all circuits except the band-gap reference generator and bias detection circuits are powered down resulting in significant power savings. For additional details of suspend/resume operation refer to the IEEE 1394a-2000 specification. The use of suspend/resume is recommended for new designs. The port transmitter and receiver circuitry is disabled during power down (when the PD input terminal is asserted high), during reset (when the RESET input terminal is asserted low), when no active cable is connected to the port, or when controlled by the internal arbitration logic. The TPBias output is disabled during power down, during reset, or when the port is disabled as commanded by the LLC. The CNA (cable-not-active) terminal provides a high when there are no twisted-pair cable ports receiving incoming bias (i.e., they are either disconnected or suspended) and can be used along with link power status (LPS) to determine when to power down the TSB41AB3. The CNA output is not debounced. When the PD terminal is asserted high, the CNA detection circuitry is enabled (regardless of the previous state of the ports) and a pulldown is activated on the RESET terminal so as to force a reset of the TSB41AB3 internal logic. The LPS terminal works with the C/LKON terminal to manage the power usage in the node. The LPS signal from the LLC is used in conjunction with the LCtrl bit (see Table 1 and Table 2 in the APPLICATION INFORMATION section) to indicate the active/power status of the LLC. The LPS signal is also used to reset, disable, and initialize the PHY-LLC interface (the state of the PHY-LCC interface is controlled solely by the LPS input regardless of the state of the LCtrl bit).

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0051 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS418I − JUNE 2000 − REVISED DECEMBER 2004

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 description (continued) The LPS input is considered inactive if it remains low for more than 2.6 µs and is considered active otherwise. When the TSB41AB3 detects that LPS is inactive, it places the PHY-LLC interface into a low-power reset state in which the CTL and D outputs are held in the logic zero state and the LREQ input is ignored; however, the SYSCLK output remains active. If the LPS input remains low for more than 26 µs, the PHY-LLC interface is put into a low-power disabled state in which the SYSCLK output is also held inactive. The PHY-LLC interface is also held in the disabled state during hardware reset. The TSB41AB3 continues the necessary repeater functions required for normal network operation regardless of the state of the PHY−LLC interface. When the interface is in the reset or disabled state and LPS is again observed active, the PHY initializes the interface and returns it to normal operation. When the PHY-LLC interface is in the low-power disabled state, the TSB41AB3 automatically enters a low-power mode if all ports are inactive (disconnected, disabled, or suspended). In this low-power mode, the TSB41AB3 disables its internal clock generators and also disables various voltage and current reference circuits, depending on the state of the ports (some reference circuitry must remain active in order to detect new cable connections, disconnections, or incoming TPBias, for example). The lowest power consumption (the ultralow-power sleep mode) is attained when all ports are either disconnected, or disabled with the port’s interrupt enable bit cleared. The TSB41AB3 exits the low-power mode when the LPS input is asserted high or when a port event occurs which requires that the TSB41AB3 become active in order to respond to the event or to notify the LLC of the event (incoming bias is detected on a suspended port, a disconnection is detected on a suspended port, a new connection is detected on a nondisabled port). The SYSCLK output becomes active (and the PHY-LLC interface is initialized and becomes operative) within 7.3 ms after LPS is asserted high when the TSB41AB3 is in the low-power mode. The PHY uses the C/LKON terminal to notify the LLC to power up and become active. When activated, the C/LKON signal is a square wave of approximately 163-ns period. The PHY activates the C/LKON output when the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet addressed to this node is received, or conditionally when a PHY interrupt occurs. The PHY deasserts the C/LKON output when the LLC becomes active (both LPS active and the LCtrl bit set to 1). The PHY also deasserts the C/LKON output when a bus reset occurs unless a PHY interrupt condition exists which otherwise causes C/LKON to be active. The TSB41AB3 is characterized for operation from 0°C to 70°C. The TSB41AB3I is characterized for operation from −40°C to 85°C.

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0051 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS418I − JUNE 2000 − REVISED DECEMBER 2004 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 pin assignments AGND AGND AGND AGND AGND AV DD AV DD SM SE TESTM DV DD DV DD DGND CPS ISO PC2 PC1 PC0 C/LKON DGND AGND AV DD AV DD AGND AGND DV DD DV DD DGND FILTER0 FILTER1 PLLV DD PLLGND PLLGND XI XO RESET DV DD DGND 5678 PFP PACKAGE (TOP VIEW) TPB1+ 59 58 57 56 5560 54 TPA2+ TPA2− TPB2+ TPB2− TPBIAS1 TPA1+ DGND CTL0 CTL1 DV V 52 51 5053 9 10 11 12 13 49 48 1LREQ AV 47 46 45 44 14 15 16 17 DGND CNA TPBIAS0 TPA0+ TPA0− AGND TPBIAS2 PD LPS 18 19 20 TPB0+ TPB0− 43 42 41 TPA1− TPB1− AGND SYSCLK DGND DD AV DD DD AV DD TSB41AB3 DD-5V

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0051 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS418I − JUNE 2000 − REVISED DECEMBER 2004

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 functional block diagram TPA2+ TPA2− TPB2+ TPB2− TPA1+ TPA1− TPB1+ TPB1− TPA0+ TPA0− TPB0+ TPB0− Cable Port 0 Cable Port 1 Cable Port 2 CPS LPS ISO CNA SYSCLK LREQ CTL0 CTL1 PC0 PC1 C/LK0N PC2 RESET PD Bias Voltage and Current Generator TPBIAS0 TPBIAS1 TPBIAS2 Link Interface I/O XI XO FILTER0 FILTER1 Received Data Decoder/Retimer Arbitration and Control State Machine Logic Transmit Data Encoder Crystal Oscillator, PLL System, and Clock Generator

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0051 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS418I − JUNE 2000 − REVISED DECEMBER 2004 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions TERMINAL I/O DESCRIPTIONNAME TYPE NO. I/O DESCRIPTION AGND Supply 36, 37, 38, 39, 40, 41, 60, 61, 64, − Analog circuit ground terminals. These terminals must be tied together to the low-impedance circuit board ground plane. AV DD Supply 34, 35, 47, 48, 54, 62, − Analog circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal are suggested, such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering capacitors are also recommended. These supply terminals are separated from PLLVDD and DVDD internal to the device to provide noise isolation. They must be tied at a low-impedance point on the circuit board. CNA CMOS 17 O Cable not active output. This terminal is asserted high when there are no ports receiving incoming bias voltage. CPS CMOS 27 I Cable power status input. This terminal is normally connected to cable power through a 400-kΩ resistor. This circuit drives an internal comparator that is used to detect the presence of cable power. This terminal must be tied to DGND through a 1-kΩ resistor if application does not require it to be used. CTL0 CTL1 CMOS

5 V tol

I/O Control I/Os. These bidirectional signals control communication between the TSB41AB3 and the LLC. Bus holders are built into these terminals. C/LKON CMOS 22 I/O Bus manager contender programming input and link-on output. On hardware reset, this terminal is used to set the default value of the contender status indicated during self-ID. Programming is done by tying the terminal through a 10-kΩ resistor to a high (contender) or low (not contender). The resistor allows the link-on output to override the input. However, it is recommended that this terminal be programmed low, and that the contender status be set via the C register bit. If the TSB41AB3 is used with an LLC that has a dedicated terminal for monitoring LKON and also setting the contender status, then a 10-kΩ series resistor is placed on the LKON line between the PHY and LLC to prevent bus contention. Following hardware reset, this terminal is the link-on output, which is used to notify the LLC to power-up and become active. The link-on output is a square-wave signal with a period of approximately 163 ns (8 SYSCLK cycles) when active. The link-on output is otherwise driven low, except during hardware reset when it is high impedance. The link-on output is activated if the LLC is inactive (LPS inactive or the LCtrl bit cleared) and when one of the following is true: a) the PHY receives a link-on PHY packet addressed to this node b) the PEI (port-event interrupt) register bit is 1 c) any of the CTOI (configuration-timeout interrupt), CPSI (cable-power-status interrupt), or STOI (state-timeout interrupt) register bits are 1 and the RPIE (resuming-port interrupt enable) register bit is also 1. Once activated, the link-on output stays active until the LLC becomes active (both LPS active and the LCtrl bit set). The PHY also deasserts the link-on output when a bus-reset occurs unless the link-on output is otherwise active because one of the interrupt bits is set (i.e., the link-on output is active due solely to the reception of a link-on PHY packet). NOTE: If an interrupt condition exists which otherwise causes the link-on output to be activated if the LLC were inactive, the link-on output is activated when the LLC subsequently becomes inactive. DGND Supply 3, 16, 20, 21, 28, 70, − Digital circuit ground terminals. These terminals must be tied together to a low-impedance point on the circuit board ground plane. D0−D7 CMOS 7, 8, 10, 11, 12, 13, 14, 15 I/O Data I/Os. These are bidirectional data signals between the TSB41AB3 and the LLC. Bus holders are built into these terminals. DV DD Supply 6, 29, 30, 68, 69, 79 − Digital circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal is suggested, such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering capacitors are also recommended. These supply terminals are separated from PLLVDD and AVDD internal to the device to provide noise isolation. They must be tied at a low-impedance point on the circuit board.

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0051 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS418I − JUNE 2000 − REVISED DECEMBER 2004

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions (Continued) TERMINAL I/O DESCRIPTIONNAME TYPE NO. I/O DESCRIPTION FILTER0 FILTER1 CMOS 71 I/O PLL filter terminals. These terminals are connected to an external capacitor to form a lag-lead filter required for stable operation of the internal frequency-multiplier PLL using the crystal oscillator. A 0.1-µF ± 10% capacitor is the only external component required to complete this filter. ISO CMOS 26 I Link interface isolation control input. This terminal controls the operation of output differentiation logic on the CTL and D terminals. If an optional isolation barrier of the type described in Annex J of IEEE Std 1394-1995 is implemented between the TSB41AB3 and LLC, the ISO terminal is tied low to enable the differentiation logic. If no isolation barrier is implemented (direct connection), or TI bus holder isolation is implemented, the ISO terminal is tied high through a pullup to disable the differentiation logic. For additional information see the TI application note Serial Bus Galvanic Isolation, literature number SLLA011. LPS CMOS 19 I Link power status input. This terminal is used to monitor the active/power status of the link layer controller and to control the state of the PHY-LLC interface. This terminal is connected either to the VDD supplying the LLC through a 10-kΩ resistor, or to a pulsed output which is active when the LLC is powered. A pulsed signal is used when an isolation barrier exists between the LLC and PHY (see Figure 8). The LPS input is considered inactive if it is sampled low by the PHY for more than 2.6 µs (128 SYSCLK cycles), and is considered active otherwise (i.e., asserted steady high or an oscillating signal with a low time less than 2.6 µs). The LPS input must be high for at least 21 ns in order to be observed as high by the PHY. When the TSB41AB3 detects that LPS is inactive, it places the PHY-LLC interface into a low-power reset state. In the reset state, the CTL and D outputs are held in the logic zero state and the LREQ input is ignored; however, the SYSCLK output remains active. If the LPS input remains low for more than 26 µs (1280 SYSCLK cycles), the PHY-LLC interface is put into a low-power disabled state in which the SYSCLK output is also held inactive. The PHY-LLC interface is placed into the disabled state upon hardware reset. The LLC is considered active only if both the LPS input is active and the LCtrl register bit is set to 1, and is considered inactive if either the LPS input is inactive or the the LCtrl register bit is cleared to 0. LREQ CMOS 1 I LLC request input. The LLC uses this input to initiate a service request to the TSB41AB3. Bus holder is built into this terminal. PC0 PC1 PC2 CMOS 23 I Power class programming inputs. On hardware reset, these inputs set the default value of the power class indicated during self-ID. Programming is done by tying the terminals high or low. See Table 9 for encoding. PD CMOS 18 I Power-down input. A high on this terminal turns off all internal circuitry except the cable-active monitor circuits, which control the CNA output. Asserting the PD input high also activates an internal pull-down on the RESET terminal must to force a reset of the internal control logic. PLLGND Supply 74, 75 − PLL circuit ground terminals. These terminals should be tied together to a low-impedance point on the circuit board ground plane. PLLV DD Supply 73 − PLL circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal are suggested, such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering capacitors are also recommended. These supply terminals are separated from DVDD and AVDD internal to the device to provide noise isolation. They must be tied at a low-impedance point on the circuit board. RESET CMOS 78 I Logic reset input. Asserting this terminal low resets the internal logic. An internal pullup resistor to VDD is provided so only an external delay capacitor is required for proper power-up operation (see power-up reset in the Application Information section). The RESET terminal also incorporates an internal pulldown which is activated when the PD input is asserted high. This input is otherwise a standard logic input, and can also be driven by an open-drain type driver. Bias 66 − Current setting resistor terminals. These terminals are connected to an external resistance to set the internal operating currents and cable driver output currents. A resistance of 6.34 kΩ ±1% is required to meet the IEEE Std 1394-1995 output voltage limits. SE CMOS 32 I Test control input. This input is used in manufacturing test of the TSB41AB3. For normal use this terminal is tied to GND through a 1-kΩ pulldown resistor.

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0051 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS418I − JUNE 2000 − REVISED DECEMBER 2004 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions (Continued) TERMINAL I/O DESCRIPTIONNAME TYPE NO. I/O DESCRIPTION SM CMOS 33 I Test control input. This input is used in the manufacturing test of the TSB41AB3. For normal use this terminal is tied to GND. SYSCLK CMOS 2 O System clock output. Provides a 49.152-MHz clock signal, synchronized with data transfers, to the LLC. TESTM CMOS 31 I Test control input. This input is used in the manufacturing test of the TSB41AB3. For normal use this terminal is tied to VDD through a 1-kΩ resistor. TPA0+ TPA1+ TPA2+ Cable 45 I/O Twisted-pair cable A differential-signal terminals. Board traces from each pair of positive and negative differential signal terminals must be kept matched and as short as possible to the TPA0− TPA1− TPA2− Cable 44 I/O negative differential signal terminals must be kept matched and as short as possible to the external load resistors and to the cable connector. For an unused port, TPA+ and TPA− can be left open. TPB0+ TPB1+ TPB2+ Cable 43 I/O Twisted-pair cable B differential-signal terminals. Board traces from each pair of positive and negative differential signal terminals should be kept matched and as short as possible to the external load resistors and to the cable connector. For each unused port, TPB+ and TPB−TPB0− TPB1− TPB2− Cable 42 I/O external load resistors and to the cable connector. For each unused port, TPB+ and TPB− terminals can be tied together and then connected to ground through a 1-kΩ resistor or the TPB+ and TPB− terminals can be connected to the suggested termination network. TPBIAS0 TPBIAS1 TPBIAS2 Cable 46 I/O Twisted-pair bias output. This provides the 1.86-V nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receivers and for signaling to the remote nodes that there is an active cable connection. Each of these terminals, except for an unused port, must be decoupled with a 1.0-µF capacitor to ground. For the unused port, this terminal can be left unconnected. VDD-5V Supply 9 − 5-V VDD terminal. This terminal must be connected to the LLC VDD supply when a 5-V LLC is used, and connected to the PHY DVDD when a 3-V LLC is used. A combination of high-frequency decoupling capacitors near this terminal is suggested, such as paralleled 0.1 µF and 0.001 µF. When this terminal is tied to a 5-V supply, all terminal bus holders are disabled, regardless of the state of the ISO terminal. When this terminal is tied to a 3-V supply, bus holders are enabled when the ISO terminal is high. XI XO Crystal 76 − Crystal oscillator inputs. These terminals connect to a 24.576-MHz parallel resonant fundamental mode crystal. The optimum values for the external shunt capacitors are dependent on the specifications of the crystal used (see crystal selection in the Applications Information section). When an external clock source is used, XI should be the input and XO should be left open, and the clock must be supplied before the device is taken out of reset. NOTE: It is strongly recommended that signals tied to VDD use a 1-kΩ resistor (minimum). Tying signals directly to VCC may result in ESD failures. Signals tied to ground may be tied directly.

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0051 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS418I − JUNE 2000 − REVISED DECEMBER 2004

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values, except differential I/O bus voltages, are with respect to network ground. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ‡ ABOVE T A = 25°C TA = 70°C POWER RATING PFP § 5.05 W 52.5 mW/°C 2.69 W PFP ¶ 3.05 W 31.7 mW/°C 1.62 W PFP # 2.01 W 20.3 mW/°C 1.1 W ‡ This is the inverse of the traditional junction-to-ambient thermal resistance (RθJA). § 2 oz. trace and copper pad with solder. ¶ 2 oz. trace and copper pad without solder. # For more information, refer to TI application note PowerPAD  Thermally Enhanced Package, TI literature number SLMA002. PowerPAD is a trademark of Texas Instruments.

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0051 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS418I − JUNE 2000 − REVISED DECEMBER 2004 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 recommended operating conditions MIN NOM † MAX UNIT Source power node 3 3.3 3.6 Supply voltage, VDD Non-source power TSB41AB3 2.7‡ 3 3.6 VSupply voltage, VDD Non-source power node TSB41AB3I 3‡ 3.3 3.6 V High-level input voltage, VIH Case1 (bus holder): ISO = VDD , VDD(5V) = VDD Case2 (5 V Tol): ISO = VDD , VDD(5V) = 5 V LREQ, CTL0, CTL1, D0−D7 2.6 VHigh-level input voltage, VIH C/LKON, PC0, PC1, PC2, ISO, PD 0.7×VDD V RESET 0.6×VDD Low-level input voltage, VIL Case1 (bus holder): ISO = VDD , VDD(5V) = VDD Case2 (5 V Tol): ISO = VDD , VDD(5V) = 5 V LREQ, CTL0, CTL1, D0−D7 1.2 VLow-level input voltage, VIL C/LKON, PC0, PC1, PC2, ISO, PD 0.2×VDD V RESET 0.3×VDD Output current, IO TPBIAS outputs −5.6 1.3 mA R JA = 19°C/W TSB41AB3 T A = 70°C 82.3 Maximum junction temperature, T R θJA = 19°C/W TSB41AB3I T A = 85°C 97.3 Maximum junction temperature, TJ (see RJA values listed in thermal R JA = 31.5°C/W TSB41AB3 T A = 70°C 90.4 J (see RθJA values listed in thermal characteristics table) R θJA = 31.5°C/W TSB41AB3I T A = 85°C 105.4 °C characteristics table) R JA = 49.2°C/W TSB41AB3 T A = 70°C 101.9 R θJA = 49.2°C/W TSB41AB3I T A = 85°C 116.9 Differential input voltage, VID Cable inputs, during data reception 118 260 mVDifferential input voltage, VID Cable inputs, during arbitration 168 265 mV Common-mode input voltage, VIC TPB cable inputs, source power node 0.4706 2.515 VCommon-mode input voltage, VIC TPB cable inputs, nonsource power node 0.4706 2.015‡ V Power-up reset time, t(pu) RESET input 2 ms TPA, TPB cable inputs, S100 operation ±1.08 Receive input jitter TPA, TPB cable inputs, S200 operation ±0.5 nsReceive input jitter TPA, TPB cable inputs, S400 operation ±0.315 ns Between TPA and TPB cable inputs, S100 operation ±0.8 Receive input skew Between TPA and TPB cable inputs, S200 operation ±0.55 nsReceive input skew Between TPA and TPB cable inputs, S400 operation ±0.5 ns † All typical values are at VDD = 3.3 V and TA = 25°C. ‡ For a node that does not source power; see Section 4.2.2.2 in IEEE 1394a-2000.

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0051 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS418I − JUNE 2000 − REVISED DECEMBER 2004

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics over recommended ranges of operating conditions (unless otherwise noted) driver PARAMETER TEST CONDITION MIN TYP MAX UNIT VOD Differential output voltage 56 Ω, See Figure 1 172 265 mV I(DIFF) Driver difference current, TPA+, TPA−, TPB+, TPB−Drivers enabled, speed signaling off−1.05† 1.05† mA I(SP200) Common-mode speed signaling current, TPB+, TPB− S200 speed signaling enabled −4.84‡ −2.53‡ mA I(SP400) Common-mode speed signaling current, TPB+, TPB− S400 speed signaling enabled −12.4‡ −8.1‡ mA VOFF Off state differential voltage Drivers disabled, See Figure 1 20 mV † Limits defined as algebraic sum of TPA+ and TPA− driver currents. Limits also apply to TPB+ and TPB− algebraic sum of driver currents. ‡ Limits defined as absolute limit of each of TPB+ and TPB− driver currents. receiver PARAMETER TEST CONDITION MIN TYP MAX UNIT zid Differential impedance Drivers disabled 4 7 kΩ zid Differential impedance Drivers disabled 4 pF zic Common-mode impedance Drivers disabled 20 kΩ zic Common-mode impedance Drivers disabled 24 pF V(TH_R) Receiver input threshold voltage Drivers disabled −30 30 mV V(TH_CB) Cable bias detect threshold, TPBx cable inputsDrivers disabled 0.6 1 V V(TH+) Positive arbitration comparator threshold voltageDrivers disabled 89 168 mV V(TH−) Negative arbitration comparator threshold voltageDrivers disabled −168 −89 mV V(TH_SP200) Speed signal threshold TPBIAS−TPA common-mode voltage, drivers disabled 49 131 mV V(TH_SP400) Speed signal threshold TPBIAS−TPA common-mode voltage, drivers disabled 314 396 mV

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0051 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS418I − JUNE 2000 − REVISED DECEMBER 2004 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics over recommended ranges of operating conditions (unless otherwise noted) (continued) device PARAMETER TEST CONDITION MIN TYP MAX UNIT See Note 2 115 IDD Supply current See Note 3 97 mAIDD Supply current See Note 4 75 mA IDD(ULP) Supply current—ultralow power mode VDD = 3.3 V, TA = 25°C, Ports disabled, PD = 0 V, LPS = 0 V 150 µA V(TH) Power status threshold, CPS input† 400-kΩ resistor† 4.7 7.5 V VOH High-level output voltage, CTL0, CTL1,VDD = 2.7 V, IOH = −4 mA 2.2 V VOH High-level output voltage, CTL0, CTL1, D0−D7, CNA, C/LKON, SYSCLK outputs VDD = 3 V to 3.6 V, IOH = −4 mA 2.8 V VOL Low-level output voltage, CTL0, CTL1, D0−D7, CNA, C/LKON, SYSCLK outputs IOL = 4 mA 0.4 V VOH(AJ) High-level Annex J output voltage, CTL0, CTL1, D0−D7, C/LKON, SYSCLK outputs Annex J: IOH = −9 mA, ISO = 0 V, V DD_5V = VDD VDD ≥ 3 V VDD −0.4 V VOL(AJ) Low-level Annex J output voltage, CTL0, CTL1, D0−D7, C/LKON, SYSCLK outputs Annex J: IOL = 9 mA, ISO = 0 V, V DD_5V = VDD VDD ≥ 3 V 0.4 V I(BH+) Positive peak bus holder current, D0−D7, CTL0−CTL1, LREQ ISO = 3.6 V, V DD = 3.6 V, VI = 0 V to VDD ,VDD_5V = VDD 0.05 1 mA I(BH−) Negative peak bus holder current, D0−D7, CTL0−CTL1, LREQ ISO = 3.6 V, V DD = 3.6 V, VI = 0 V to VDD ,VDD_5V = VDD −1.0 −0.05 mA II Input current, LREQ, LPS, PD, TESTM, SM, SE, PC0–PC2 inputs ISO = 0 V, VDD = 3.6 V 1 µA IOZ Off-state output current, CTL0, CTL1, D0–D7, C/LKON I/O’s VO = VDD or 0 V ±5 µA I(IRST) Pullup current, RESET input VI = 1.5 V or 0 V −90 −20 µA VIT+ Positive input threshold voltage, LREQ, CTL0, CTL1, D0–D7 inputs‡ VDD_5V = VDD , ISO = 0 V VDD ≥ 3 V VDD /2+0.3 VDD /2+0.9 VVIT+ Positive input threshold voltage, LPS inputsVDD_5V = VDD , ISO = 0 V, Vref = VDD × 0.4, VDD ≥ 3 V Vref+1 V VIT− Negative input threshold voltage, LREQ, CTL0, CTL1, D0–D7 inputs‡ ISO = 0 V, V DD_5V = VDD VDD ≥ 3 V VDD /2−0.9 VDD /2−0.3 VVIT− Negative input threshold voltage, LPS inputs ISO = 0 V, V DD_5V = VDD, Vref = VDD × 0.4, VDD ≥ 3 V Vref+0.2 V VO TPBIAS output voltage At rated IO current 1.665 2.015 V † Measured at cable power side of resistor. ‡ This parameter applicable only when ISO is low. NOTES: 2. Transmit max packet (three ports transmitting max size isochronous packet—4096 bytes, sent on every isochronous interval, s400, data value of 0xCCCCCCCCh), VDD = 3.3 V, TA = 25°C 3. Repeat typical packet (one port receiving DV packets on every isochronous interval, two ports repeating the packet, s100), VDD =

3.3 V, TA = 25°C

1. Idle (three ports transmitting cycle starts), VDD = 3.3 V, TA = 25°C

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

or grease thermal connection to thermal land with 2 oz. Figure 1. Test Load Diagram

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0051 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS418I − JUNE 2000 − REVISED DECEMBER 2004 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 PARAMETER MEASUREMENT INFORMATION thtsu D, CTL, LREQ SYSCLK Figure 2. Dx, CTLx, LREQ Input Setup and Hold Time Waveforms Figure 3. Dx and CTLx Output Delay Relative to SYSCLK Waveforms

APPLICATION INFORMATION

internal register configuration There are 16 accessible internal registers in the TSB41AB3. The configuration of the registers at addresses 0h through 7h (the base registers) is fixed, while the configuration of the registers at addresses 8h through Fh (the paged registers) is dependent upon which one of eight pages, numbered 0h through 7h, is currently selected. The selected page is set in base register 7h. The configuration of the base registers is shown in Table 1, and corresponding field descriptions given in Table 2. The base register field definitions are unaffected by the selected page number. is read as 0, but is subject to future usage. All registers in address pages 2 through 6 are reserved. Table 1. Base Register Configuration

0000 Physical ID R CPS

0001 RHB IBR Gap_Count

0010 Extended (111b) Rsvd Num_Ports (0011b)

0011 PHY_Speed (010b) Rsvd Delay (0000b)

0100 LCtrl C Jitter (000b) Pwr_Class

0101 RPIE ISBR CTOI CPSI STOI PEI EAA EMC

0110 Reserved

0111 Page_Select Rsvd Port_Select

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0051 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS418I − JUNE 2000 − REVISED DECEMBER 2004

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 internal register configuration (continued) Table 2. Base Register Field Descriptions after a bus reset until self-ID has completed as indicated by an unsolicited register-0 status transfer. tree-ID if this node becomes root. dropped below its threshold for ensured reliable operation. reset to 0 by a hardware reset is unaffected by a bus reset. IBR bit is reset to 0 after a hardware reset or a bus reset. Gap_Count 6 Rd/Wr Arbitration gap count. This value is used to set the subaction (fair) gap, arb-reset gap, and arb-delay times. intervening write to the gap count register (either by a write to the PHY register or by a PHY_CONFIG packet). PHY_Speed 3 Rd PHY speed capability. For the TSB41AB3 PHY this field is 010b, indicating S400 speed capability. 144+(delay × 20) ns. For the TSB41AB3 this field is 0. LCtrl 1 Rd/Wr Link-active status control. This bit is used to control the active status of the LLC as indicated during self-ID. LLC is considered active only if both the LPS input is active and the LCtrl bit is set. The LCtrl bit is set to 1 by hardware reset and is unaffected by bus-reset. LREQ input is processed, even if the LCtrl bit is cleared to 0. the C/LKON input terminal by a hardware reset and is unaffected by a bus reset. data delay, expressed as (jitter+1) × 20 ns. For the TSB41AB3, this field is 0. PC0−PC2 input terminals upon a hardware reset, and is unaffected by a bus reset. See Table 9.

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0051 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS418I − JUNE 2000 − REVISED DECEMBER 2004 17POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Table 2. Base Register Field Descriptions (Continued) reset at the next opportunity. This bit is reset to 0 by a bus reset. NOTE: Legacy IEEE Std 1394-1995 compliant PHYs can not be capable of performing short bus resets. output to notify the LLC to service the interrupt. to complete and then generate a state time-out interrupt and bus-reset. by writing a 1 to this register bit. output to notify the LLC to service the interrupt. occur). This bit is reset to 0 by hardware reset, or by writing a 1 to this register bit. output to notify the LLC to service the interrupt. or by writing a 1 to this register bit. and isochronous fly-by concatenation). This bit is reset to 0 by hardware reset and is unaffected by bus reset. excessively delaying the transmission of cycle-start packets. reset and is unaffected by bus reset. Page_Select 3 Rd/Wr Page_Select. This field selects the register page to use when accessing register addresses 8 through 15. This field is reset to 0 by a hardware reset and is unaffected by bus-reset. hardware-reset and is unaffected by bus-reset.

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0051 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS418I − JUNE 2000 − REVISED DECEMBER 2004

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 internal register configuration (continued) The port status page provides access to configuration and status information for each of the ports. The port is selected by writing 0 to the Page_Select field and the desired port number to the Port_Select field in base register 7. The configuration of the port status page registers is shown in Table 3 and corresponding field descriptions given in Table 4. If the selected port is unimplemented, all registers in the port status page are read as 0. Table 3. Page 0 (Port Status) Register Configuration

1000 AStat BStat Ch Con Bias Dis

1001 Peer_Speed PIE Fault Reserved

1010 Reserved

1011 Reserved

1100 Reserved

1101 Reserved

1110 Reserved

1111 Reserved

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0051 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS418I − JUNE 2000 − REVISED DECEMBER 2004 19POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 internal register configuration (continued) Table 4. Page 0 (Port Status) Register Field Descriptions bus-reset until tree-ID has completed. hardware reset and is unaffected by bus-reset. Bias 1 Rd Debounced incoming cable bias status. A 1 indicates that the selected port is detecting incoming cable bias. The incoming cable bias must be stable for the debounce time of 52 µs for the bias bit to be set to 1. enabled for normal operation following hardware reset). The dis bit is not affected by bus-reset.

000 S100

001 S200

010 S400

The Peer_Speed field is invalid after a bus-reset until self-ID has completed. capable of detecting peer speeds up to S400. and notify the link. This bit is reset to 0 by a hardware reset, and is unaffected by bus-reset.

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0051 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS418I − JUNE 2000 − REVISED DECEMBER 2004

20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 internal register configuration (continued) The vendor identification page is used to identify the vendor/manufacturer and compliance level. The page is selected by writing 1 to the Page_Select field in base register 7. The configuration of the vendor identification page is shown in Table 5, and corresponding field descriptions given in Table 6. Table 5. Page 1 (Vendor ID) Register Configuration

1000 Compliance

1001 Reserved

1010 Vendor_ID[0]

1011 Vendor_ID[1]

1100 Vendor_ID[2]

1101 Product_ID[0]

1110 Product_ID[1]

1111 Product_ID[2]

Table 6. Page 1 (Vendor ID) Register Field Descriptions Compliance 8 Rd Compliance level. For the TSB41AB3 this field is 01h, indicating compliance with the 1394a-2000 specification. Instruments) (the MSB is at register address 1010b). Product_ID 24 Rd Product identifier. For the TSB41AB3 this field is 43_41_95h (the MSB is at register address 1101b). and corresponding field descriptions given in Table 8. Table 7. Page 7 (Vendor-Dependent) Register Configuration

1000 NPA Reserved Link_Speed

1001 Reserved for test

1010 Reserved for test

1011 Reserved for test

1100 Reserved for test

1101 Reserved for test

1110 SWR Reserved for test

1111 Reserved for test

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0051 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS418I − JUNE 2000 − REVISED DECEMBER 2004 21POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 internal register configuration (continued) Table 8. Page 7 (Vendor-Dependent) Register Field Descriptions less than 8 bits. This bit is cleared to 0 by hardware reset and is unaffected by bus-reset.

00 S100

01 S200

10 S400

in this field. This field is set to 10b (S400) by hardware reset and is unaffected by bus-reset. RESET pin low). This bit is always read as a 0. loaded into the Pwr_Class field in register 4. Table 9. Power Class Descriptions 000 Node does not need power and does not repeat power. 001 Node is self-powered and provides a minimum of 15 W to the bus. 010 Node is self-powered and provides a minimum of 30 W to the bus. 011 Node is self-powered and provides a minimum of 45 W to the bus. it provides can be found in the configuration ROM.

101 Reserved

110 Node is powered from the bus and uses up to 3 W. An additional 3 W is needed to enable the link. 111 Node is powered from the bus and uses up to 3 W. An additional 7 W is needed to enable the link.

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0051 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS418I − JUNE 2000 − REVISED DECEMBER 2004

22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 power-class programming (continued) TPA+ TPA− TPB+ TPB− Cable Port CPS TPBIAS 56 Ω‡56 Ω‡ 56 Ω‡56 Ω‡ 5 kΩ 1 µF 400 kΩ 220 pF† TSB41AB3 Cable Power Pair Cable Pair A Cable Pair B Outer Shield Termination † The IEEE Std 1394-1995 calls for a 250-pF capacitor, which is a nonstandard component value. A 220-pF capacitor is recommended. ‡ ±0.5% to meet 1394−1995 specification. Figure 4. TP Cable Connections Figure 5. Typical Compliant DC Isolated Outer Shield Termination

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0051 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS418I − JUNE 2000 − REVISED DECEMBER 2004

24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 NOTE A: See Crystal Selection section 21 22 23 24 25 26 27 28 79 78 77 76 7580 74 RESET XO XI CPS 72 71 7073 29 30 31 32 33 69 68 67 66 65 34 35 36 AGND DGND C/LKON PC0 PC1 DGND DV DD DGND TSB41AB3 6.34 kΩ ± 1% V DD

24.576 MHz

TPA2− TPB2+ TPB2− TPBIAS1 TPA1+ AV TPBIAS0 TPA0+ TPA0− AGND TPBIAS2 TPB0+ TPB0− TPA1− TPB1− AGND AV DD DD AV DD 64 63 62 61 AGND AV DD AV DD AGND DV DD DV DD FILTER0 FILTER1 DGND PLLGND PLLV DD PLLGND DV DD VDD (see Note A) 0.001µF 0.1 µF 0.1µF 0.001µF 0.1µF V D D 0.001µF 0.1µF V DD 0.001µF 0.001µF 0.001µF V DD 10 kΩ LKON Bus Power-Class Programming ISO Cable Power 400 kΩ 0.001µF 0.1µF 0.001µF 1 µF V DD VDD Link VDD CNA Out TP Cables Interface Connection V DD TPBIAS TP Cables Interface Connection V DD 1 µF TPBIAS TP Cables Interface Connection 1 µF TPBIAS 0.1µF 0.001µF 0.1µF 0.1µF 0.001µF 0.1µF 0.001 µF 0.001 µF 0.001 µF 0.01 µF 0.1µF 0.1µF 0.001µF C10 (see Note A)Manager 1 kΩ 1 kΩ Figure 9. External Component Connections

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0051 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS418I − JUNE 2000 − REVISED DECEMBER 2004 25POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 For electromagnetic interference (EMI) guidelines and recommendations, send a request via email to: 1394-EMI@list.ti.com designing with PowerPAD The TSB41AB3 is housed in a high performance, thermally enhanced, 80-pin PFP PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. Therefore, if not implementing PowerPAD PCB features, the use of solder masks (or other assembly techniques) may be required to prevent any inadvertent shorting by the exposed PowerPAD of connection etches or vias under the package. The recommended option, however, is to not run any etches or signal vias under the device, but to have only a grounded thermal land as explained below. Although the actual size of the exposed die pad may vary, the minimum size required for the keepout area for the 80-pin PFP PowerPAD package is 10 mm × 10 mm. It is recommended that there be a thermal land, which is an area of solder-tinned-copper, underneath the PowerPAD package. The thermal land varies in size, depending on the PowerPAD package being used, the PCB construction, and the amount of heat that needs to be removed. In addition, the thermal land may or may not contain numerous thermal vias depending on PCB construction. Other requirements for thermal lands and thermal vias are detailed in the TI application note PowerPAD Thermally Enhanced Package Application Report, TI literature number SLMA002, available via the TI Web pages beginning at URL: http://www.ti.com. Figure 10. Example of a Thermal Land for the TSB41AB3 PHY exposed PowerPAD using standard reflow soldering techniques. information may be obtained from the TI application note PHY Layout, TI literature number SLLA020.

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0051 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS418I − JUNE 2000 − REVISED DECEMBER 2004

26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 using the TSB41AB3 with a non-1394a-2000 link layer (continued) The 1394a-2000 Supplement includes enhancements to the Annex J interface that must be comprehended when using the TSB41AB3 with a non-1394a-2000 LLC device. /C0068A new LLC service request was added which allows the LLC to temporarily enable and disable asynchronous arbitration accelerations. If the LLC does not implement this new service request, the arbitration enhancements is not enabled (see the EAA bit in PHY register 5). /C0068The capability to perform multispeed concatenation (the concatenation of packets of differing speeds) was added in order to improve bus efficiency (primarily during isochronous transmission). If the LLC does not support multispeed concatenation, multispeed concatenation is not enabled in the PHY (see the EMC bit in PHY register 5). /C0068In order to accommodate the higher transmission speeds expected in future revisions of the standard, 1394a-2000 extended the speed code in bus requests from 2 bits to 3 bits, increasing the length of the bus request from 7 bits to 8 bits. The new speed codes were carefully selected so that new 1394a-2000 PHY and LLC devices would be compatible, for speeds from S100 to S400, with legacy PHY and LLC devices that use the 2-bit speed codes. The TSB41AB3 correctly interprets both 7-bit bus requests (with 2-bit speed code) and 8-bit bus requests (with 3-bit speed codes). Moreover, if a 7-bit bus request is immediately followed by another request (e.g., a register read or write request), the TSB41AB3 correctly interprets both requests. Although the TSB41AB3 correctly interprets 8-bit bus requests, a request with a speed code exceeding S400 results in the TSB41AB3 transmitting a null packet (data-prefix followed by data-end, with no data in the packet). More explanation is included in the TI application note IEEE 1394a-2000 Features Supported by TI TSB41LV0X Physical Layer Devices, TI literature number SLLA019. using the TSB41AB3 with a lower-speed link layer Although the TSB41AB3 is an S400-capable PHY, it may be used with lower speed LLCs, such as the S200 capable TSB12LV31. In such a case, the LLC has fewer data terminals than the PHY, and some Dn terminals on the TSB41AB3 are not used. Unused Dn terminals are pulled to ground through 10-kΩ resistors. The TSB41AB3 transfers all received packet data to the LLC, even if the speed of the packet exceeds the capability of the LLC to accept it. Some lower speed LLC designs do not properly ignore packet data in such cases. On the rare occasions that the first 16 bits of partial data accepted by such a LLC match a node’s bus and node ID, spurious header CRC or tcode errors may result. During bus initialization following a bus-reset, each PHY transmits a self-ID packet that indicates, among other information, the speed capability of the PHY. The bus manager (if one exists) builds a speed map from the collected self-ID packets. This speed map gives the highest possible speed that can be used on the node-to-node communication path between every pair of nodes in the network. In the case of a node consisting of a higher-speed PHY and a lower-speed LLC, the speed capability of the node (PHY and LLC in combination) is that of the lower-speed LLC. A sophisticated bus manager may be able to determine the LLC speed capability by reading the configuration ROM Bus_Info_Block or by sending asynchronous request packets at different speeds to the node and checking for an acknowledge; the speed map may then be adjusted accordingly. The speed-map should reflect that communication to such a node must be done at the lower speed of the LLC, instead of the higher speed of the PHY. However, speed map entries for paths that merely pass through the node’s PHY , but do not terminate at that node, are not restricted by the lower speed of the LLC.

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0051 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS418I − JUNE 2000 − REVISED DECEMBER 2004 27POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 using the TSB41AB3 with a lower-speed link layer (continued) To assist in building an accurate speed-map, the TSB41AB3 has the capability to indicate a speed other than S400 in its transmitted self-ID packet. This is controlled by the Link_Speed field in register 8 of the vendor-dependent page (page 7). Setting the Link_Speed field affects only the speed indicated in the self-ID packet; it has no effect on the speed signaled to peer PHYs during self-ID. The TSB41AB3 identifies itself as S400 capable to its peers regardless of the value in the Link_Speed field. Generally, the Link_Speed field is not changed from its power-on default value of S400 unless it is determined that the speed-map (if one exists) is incorrect for path entries terminating in the local node. If the speed map is incorrect, it can be assumed that the bus manager has used only the self-ID packet information to build the speed map. In this case, the node may update the Link_Speed field to reflect the lower speed capability of the LLC and then initiate another bus-reset to cause the speed-map to be rebuilt. Note that in this scenario any speed-map entries for node-to-node communication paths that pass through the local node’s PHY are restricted by the lower speed. In the case of a leaf node (which has only one active port) the Link_Speed field may be set to indicate the speed of the LLC without first checking the speed-map. Changing the Link_Speed field in a leaf node can only affect those paths that terminate at that node, because no other paths can pass through a leaf node. It can have no effect on other paths in the speed map. For hardware configurations that can only be a leaf node (all ports but one are unimplemented), it is recommended that the Link_Speed field be updated immediately after power-on or hardware reset. power-up reset To ensure proper operation of the TSB41AB3 the RESET terminal must be asserted low for a minimum of 2 ms from the time that PHY power reaches the minimum required supply voltage. When using a passive capacitor on the RESET terminal to generate a power-on reset signal, the minimum reset time is assured if the value of the capacitor has a minimum value of 0.1 µF and also satisfies the following equation: C min = 0.0077× T + 0.085 where Cmin is the minimum capacitance on the RESET terminal in µF, and T is the VDD ramp time, 10%–90%, in ms. crystal selection The TSB41AB3 and other TI PHY devices are designed to use an external 24.576 MHz crystal connected between the XI and XO terminals to provide the reference for an internal oscillator circuit. This oscillator in turn drives a PLL circuit that generates the various clocks required for transmission and resynchronization of data at the S100 through S400 media data rates. A variation of less than ±100 ppm from nominal for the media data rates is required by IEEE Std 1394. Adjacent PHYs may therefore have a difference of up to 200 ppm from each other in their internal clocks, and PHYs must be able to compensate for this difference over the maximum packet length. Larger clock variations may cause resynchronization overflows or underflows, resulting in corrupted packet data. For the TSB41AB3, the SYSCLK output may be used to measure the frequency accuracy and stability of the internal oscillator and PLL from which it is derived. The frequency of the SYSCLK output must be within ±100 ppm of the nominal frequency of 49.152 MHz.

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0051 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS418I − JUNE 2000 − REVISED DECEMBER 2004

28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 crystal selection (continued) The following are some typical specifications for crystals used with the physical layers from TI in order to achieve the required frequency accuracy and stability: /C0068Crystal mode of operation: Fundamental /C0068Frequency tolerance at 25°C: Total frequency variation for the complete circuit is ±100 ppm. A crystal with ±30-ppm frequency tolerance is recommended for adequate margin. /C0068Frequency stability (over temperature and age): A crystal with ±30-ppm frequency stability is recommended for adequate margin. NOTE: The total frequency variation must be kept below ±100 ppm from nominal with some allowance for error introduced by board and device variations. Trade-offs between frequency tolerance and stability may be made as long as the total frequency variation is less than ±100 ppm. For example, the frequency tolerance of the crystal may be specified at 50 ppm and the temperature tolerance may be specified at 30 ppm to give a total of 80 ppm possible variation due to the crystal alone. Crystal aging also contributes to the frequency variation. /C0068Load capacitance: For parallel resonant mode crystal circuits, the frequency of oscillation is dependent upon the load capacitance specified for the crystal. Total load capacitance (CL) is a function of not only the discrete load capacitors, but also board layout and circuit. It may be necessary to iteratively select discrete load capacitors until the SYSCLK output is within specification. It is recommended that load capacitors with a maximum of ±5% tolerance be used. For example, the OHCI + 41LV03 evaluation module (EVM), which uses a crystal specified for 12 pF loading, uses load capacitors (C9 and C10 in Figure 11) of 16 pF each were appropriate for the layout of that particular board. The load specified for the crystal includes the load capacitors (C9, C10), the loading of the PHY terminals (CPHY ), and the loading of the board itself (CBD ). The value of CPHY is typically about 1 pF, and CBD is typically 0.8 pF per centimeter of board etch; a typical board can have 3 pF to 6 pF or more. The load capacitors C9 and C10 combine as capacitors in series so that the total load capacitance is: C L = [(C9 × C10) / (C9+C10)] + CPHY + CBD . C10 XI XO Figure 11. Load Capacitance for the TSB41AB3 PHY possible to the PHY XI and XO terminals to minimize trace lengths.

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0051 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS418I − JUNE 2000 − REVISED DECEMBER 2004 29POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 crystal selection (continued) C10 Figure 12. Recommended Crystal and Capacitor Layout details and requirements may be provided by the crystal vendor. designs which were based upon the suggested register set defined in Annex J of IEEE Std 1394-1995). Therefore, whenever the IBR bit is written, the RHB bit and gap-count are also necessarily written. remains set to the value just loaded by the write to PHY register 1. first be read from register 1 and then rewritten. consistent with other nodes on the bus. The RHB bit must be maintained with its current value. without also setting the IBR bit to 1.

30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

the operation of the PHY-LLC interface. terminals on the TSB41AB3, as shown in Figure 13. Figure 13. PHY-LLC Interface and sampled on, the rising edge of SYSCLK. between the TSB41AB3 and LLC. the LLC is in control of the D0–D7 bus, unused Dn terminals are ignored by the TSB41AB3. to the serial-bus for packet transmission, read or write PHY registers, or control arbitration acceleration. indicates the power status of the LLC and may be used to reset the PHY-LLC interface or to disable SYSCLK. when either LPS is inactive or the PHY register L bit is zero. terminal is used to enable the output differentiation logic on the CTL0–CTL1 and D0–D7 terminals. is implemented between the PHY and LLC. these buses only after the LLC has been granted permission to do so by the PHY.

to gain control of the serial-bus in order to transmit a packet, or to control arbitration acceleration. The PHY initiates a receive operation whenever a packet is received from the serial bus. The PHY initiates a transmit operation after winning control of the serial-bus following a bus-request by the LLC. The transmit operation is initiated when the PHY grants control of the interface to the LLC. The encoding of the CTL0-CTL1 bus is shown in Table 10 and Table 11. Table 10. CTL Encoding When PHY Has Control of the Bus 0 1 Status Status information is being sent from the PHY to the LLC. 1 0 Receive An incoming packet is being sent from the PHY to the LLC. 1 1 Grant The LLC has been given control of the bus to send an outgoing packet. Table 11. CTL Encoding When LLC Has Control of the Bus 0 0 Idle The LLC releases the bus (transmission has been completed). another packet is to be transmitted (concatenated) without arbitrating. 1 0 Transmit An outgoing packet is being sent from the LLC to the PHY. voltage level between the hysteresis thresholds of the input buffer so that the previous logic state is maintained. The correspondence between the output logic state and the output signal level is shown in Figure 14.

32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Figure 14. Signal Transformation for Digital Differentiation circuitry on its LREQ terminal. Figure 15. Input/Output Differentiation Logic

a serial bit stream on the LREQ terminal as shown in Figure 16. Each cell represents one clock sample time, and n is the number of bits in the request stream. Figure 16. LREQ Request Stream The length of the stream varies depending on the type of request as shown in Table 12. Table 12. Request Stream Bit Length stream. The LREQ terminal is normally low. Encoding for the request type is shown in Table 13. Table 13. Request Type Encoding 000 ImmReq Immediate bus request. Upon detection of idle, the PHY takes control of the bus immediately without arbitration. 001 IsoReq Isochronous bus request. Upon detection of idle, the PHY arbitrates for the bus without waiting for a subaction gap. 010 PriReq Priority bus request. The PHY arbitrates for the bus after a subaction gap, ignores the fair protocol. 011 FairReq Fair bus request. The PHY arbitrates for the bus after a subaction gap, follows the fair protocol. 100 RdReg The PHY returns the specified register contents through a status transfer.

101 WrReg Write to the specified register

110 AccelCtl Enable or disable asynchronous arbitration acceleration

111 Reserved Reserved

For a bus request the length of the LREQ bit stream is 7 or 8 bits as shown in Table 14. Table 14. Bus Request 0 Start bit Indicates the beginning of the transfer (always 1). 1-3 Request type Indicates the type of bus request. See Table 13. 4-6 Request speed Indicates the speed at which the PHY sends the data for this request. See Table 15 for the encoding of this field. 7 Stop bit Indicates the end of the transfer (always 0). If bit 6 is 0, this bit may be omitted.

34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

The 3-bit request speed field used in bus requests is shown in Table 15. Table 15. Bus Request Speed Encoding

010 S200

100 S400

presented by the LLC and transmits a null packet. For a read register request the length of the LREQ bit stream is 9 bits as shown in Table 16. Table 16. Read Register Request

0 Start bit Indicates the beginning of the transfer (always 1)

8 Stop bit Indicates the end of the transfer (always 0)

For a write register request the length of the LREQ bit stream is 17 bits as shown in Table 17. Table 17. Write Register Request

16 Stop bit Indicates the end of the transfer (always 0)

For an acceleration control request the Length of the LREQ data stream is 6 bits as shown in Table 18. Table 18. Acceleration Control Request

4 Control Asynchronous period arbitration acceleration is enabled if 1, and disabled if 0

5 Stop bIt Indicates the end of the transfer (always 0)

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0051 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS418I − JUNE 2000 − REVISED DECEMBER 2004 35POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 PRINCIPLES OF OPERATION LLC service request (continued) For fair or priority access, the LLC sends the bus request (FairReq or PriReq) at least one clock after the PHY-LLC interface becomes idle. If the CTL terminals are asserted to the receive state (10b) by the PHY, then any pending fair or priority request is lost (cleared). Additionally, the PHY ignores any fair or priority requests if the receive state is asserted while the LLC is sending the request. The LLC may then reissue the request one clock after the next interface idle. The cycle master node uses a priority bus request (PriReq) to send a cycle start message. After receiving or transmitting a cycle start message, the LLC can issue an isochronous bus request (IsoReq). The PHY clears an isochronous request only when the serial bus has been won. To send an acknowledge packet, the LLC must issue an immediate bus request (ImmReq) during the reception of the packet addressed to it. This is required in order to minimize the idle gap between the end of the received packet and the start of the transmitted acknowledge packet. As soon as the receive packet ends, the PHY immediately grants control of the bus to the LLC. The LLC sends an acknowledgment to the sender unless the header CRC of the received packet is corrupted. In this case, the LLC does not transmit an acknowledge, but instead cancels the transmit operation and releases the interface immediately; the LLC must not use this grant to send another type of packet. After the interface is released the LLC may proceed with another request. The LLC may make only one bus request at a time. Once the LLC issues any request for bus access (ImmReq, IsoReq, FairReq, or PriReq), it cannot issue another bus request until the PHY indicates that the bus request was lost (bus arbitration lost and another packet received), or won (bus arbitration won and the LLC granted control). The PHY ignores new bus requests while a previous bus request is pending. All bus requests are cleared upon a bus reset. For write register requests, the PHY loads the specified data into the addressed register as soon as the request transfer is complete. For read register requests, the PHY returns the contents of the addressed register to the LLC at the next opportunity through a status transfer. If a received packet interrupts the status transfer, then the PHY continues to attempt the transfer of the requested register until it is successful. A write or read register request may be made at any time, including while a bus request is pending. Once a read register request is made, the PHY ignores further read register requests until the register contents are successfully transferred to the LLC. A bus reset does not clear a pending read register request. The TSB41AB3 includes several arbitration acceleration enhancements, which allow the PHY to improve bus performance and throughput by reducing the number and length of inter-packet gaps. These enhancements include autonomous (fly-by) isochronous packet concatenation, autonomous fair and priority packet concatenation onto acknowledge packets, and accelerated fair and priority request arbitration following acknowledge packets. The enhancements are enabled when the EAA bit in PHY register 5 is set. The arbitration acceleration enhancements may interfere with the ability of the cycle master node to transmit the cycle start message under certain circumstances. The acceleration control request is therefore provided to allow the LLC to temporarily enable or disable the arbitration acceleration enhancements of the TSB41AB3 during the asynchronous period. The LLC typically disables the enhancements when its internal cycle counter rolls over indicating that a cycle start message is imminent, and then reenables the enhancements when it receives a cycle start message. The acceleration control request may be made at any time, however, and is immediately serviced by the PHY. Additionally, a bus reset or isochronous bus request causes the enhancements to be reenabled, if the EAA bit is set.

36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

been successfully transmitted. There is at least one idle cycle between consecutive status transfers. transfer has not yet completed. The definition of the bits in the status transfer is shown in Table 19 and the timing is shown in Figure 17. Table 19. Status Bits the IEEE 1394-1995 standard). This bit is used by the LLC in the busy/retry state machine. IEEE 1394-1995 standard). This bit is used by the LLC to detect the completion of an isochronous cycle. 2 Bus reset Indicates that the PHY has entered the bus reset state. cable-power voltage falling too low, a state time-out, or a port status change. 4-7 Address This field holds the address of the PHY register whose contents are being transferred to the LLC. 8-15 Data This field holds the register contents. Figure 17. Status Transfer Timing

register data is to be sent in addition to any status information. in the calculation of CRC or any other data protection mechanisms. terminating the receive operation. to the LLC. This packet it transferred to the LLC just as any other received self-ID packet. Figure 18. Normal Packet Reception Timing

38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

to receive without an intervening idle. cycles preceding the speed-code. a speed higher that that which the link is capable of handling, the link should ignore the subsequent data. data on the D lines with receive on the CTL lines for the remainder of the receive operation. lines. The PHY asserts at least one cycle of idle following a receive operation. Figure 19. Null Packet Reception Timing to receive without an intervening idle. b. Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more cycles. lines. The PHY asserts at least one cycle of idle following a receive operation. Table 20. Receive Speed Codes

0100 XXXX S200

NOTE: X = Output as 0 by PHY, ignored by LLC. Y = Output as 1 by PHY, ignored by LLC.

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0051 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS418I − JUNE 2000 − REVISED DECEMBER 2004 39POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 PRINCIPLES OF OPERATION transmit When the LLC issues a bus request through the LREQ terminal, the PHY arbitrates to gain control of the bus. If the PHY wins arbitration for the serial bus, the PHY-LLC interface bus is granted to the LLC by asserting the grant state (11b) on the CTL terminals for one SYSCLK cycle, followed by idle for one clock cycle. The LLC then takes control of the bus by asserting either idle (00b), hold (01b) or transmit (10b) on the CTL terminals. Unless the LLC is immediately releasing the interface, the LLC may assert the idle state for at most one clock before it must assert either hold or transmit on the CTL terminals. The hold state is used by the LLC to retain control of the bus while it prepares data for transmission. The LLC may assert hold for zero or more clock cycles (i.e., the LLC need not assert hold before transmit). The PHY asserts data-prefix on the serial bus during this time. When the LLC is ready to send data, the LLC asserts transmit on the CTL terminals as well as sending the first bits of packet data on the D lines. The transmit state is held on the CTL terminals until the last bits of data have been sent. The LLC then asserts either hold or idle on the CTL terminals for one clock cycle, and then asserts idle for one additional cycle before releasing the interface bus and putting the CTL and D terminals in a high-impedance state. The PHY then regains control of the interface bus. The hold state asserted at the end of packet transmission indicates to the PHY that the LLC requests to send another packet (concatenated packet) without releasing the serial bus. The PHY responds to this concatenation request by waiting the required minimum packet separation time and then asserting grant as before. This function may be used to send a unified response after sending an acknowledge, or to send consecutive isochronous packets during a single isochronous period. Unless multispeed concatenation is enabled, all packets transmitted during a single bus ownership must be of the same speed (since the speed of the packet is set before the first packet). If multispeed concatenation is enabled (when the EMSC bit of PHY register 5 is set), the LLC must specify the speed code of the next concatenated packet on the D terminals when it asserts hold on the CTL terminals at the end of a packet. The encoding for this speed code is the same as the speed code that precedes received packet data as given in Table 20. After sending the last packet for the current bus ownership, the LLC releases the bus by asserting idle on the CTL terminals for two clock cycles. The PHY begins asserting idle on the CTL terminals one clock after sampling idle from the link. Note that whenever the D and CTL terminals change direction between the PHY and the LLC, there is an extra clock period allowed so that both sides of the interface can operate on registered versions of the interface signals.

40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Figure 20. Normal Packet Transmission Timing the interface (i.e., it places its CTL and D outputs in a high-impedance state) following the idle cycle. transmit. This idle cycle is optional; the link is not required to assert idle preceding either hold or transmit. hold cycle(s) are optional; the link is not required to assert hold preceding transmit. with the data on the D lines. this cycle of hold or idle before releasing the interface and returning control to the PHY. Table 20). The link may not concatenate an S100 packet onto any higher-speed packet. status transfer, receive operation, or transmit operation.

Figure 21. Cancelled/Null Packet Transmission of the interface to the link. is optional; the link is not required to assert idle preceding hold. hold cycle(s) are optional; the link is not required to assert hold preceding idle. status transfer, receive operation, or transmit operation. interface to normal operation.

42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Table 21. LPS Timing Parameters requirements of 1394a-2000 operates correctly with the TSB41AB3).

1. A pulsed LPS signal must have a duty cycle (ratio of TLPSH to cycle period) in the specified range to ensure proper operation when

on the LREQ signal. The timing for interface reset is shown in Figure 22 and Figure 23. Figure 22. Interface Reset, ISO Low

data reception and transmission via the CTL and D lines, and request activity via the LREQ line. terminate any output signal activity such that signals end in a logic 0 state). become unbalanced.) When LPS is asserted, the interface initializes as described below. Figure 23. Interface Reset, ISO High

44 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

packet data reception and transmission via the CTL and D lines, and request activity via the LREQ line. required when using an isolation barrier (whether of the TI bus holder type or Annex J type). bus activity, places its CTL and D outputs into a high-impedance state, and drives its LREQ output low. is asserted, the interface initializes as described below. for interface disable is shown in Figure 24 and Figure 25. When the interface is disabled, the PHY enters a low-power state if none of its ports is active. Figure 24. Interface Disable, ISO Low

data reception and transmission via the CTL and D lines, and request activity via the LREQ line. any output signal activity such that signals end in a logic 0 state). is now in the disabled state. Figure 25. Interface Disable, ISO High

46 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

data reception and transmission via the CTL and D lines, and request activity via the LREQ line. bus activity, places its CTL and D outputs into a high-impedance state, and drives its LREQ output low. SYSCLK activity by driving the SYSCLK output low. The PHY-LLC interface is now in the disabled state.

7 Cycles

Figure 26. Interface Initialization, ISO Low

for SYSCLK to be restored; if the PHY is not in a low-power state, SYSCLK is restored within 60 ns. cycles of SYSCLK (in the above diagram, this is shown as occurring in the first SYSCLK cycle). high-impedance state after the first cycle). indicates that the PHY-LLC interface initialization is complete and normal operation may commence. The PHY accepts requests from the LLC via the LREQ line. Figure 27. Interface Initialization, ISO High

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0051 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0084/C0072/C0082/C0069/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS418I − JUNE 2000 − REVISED DECEMBER 2004

48 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 PRINCIPLES OF OPERATION interface reset and disable (continued) The sequence of events for initialization of the PHY-LLC interface when the interface is in the nondifferentiated mode of operation (ISO terminal is high) is as follows:1 a. LPS reasserted. After the interface has been in the reset or disabled state for at least the minimum TRESTORE time, the LLC causes the interface to be initialized and restored to normal operation by reasserting the LPS signal. (In Figure 27, the interface is shown in the disabled state with SYSCLK low inactive. However, the interface initialization sequence described here is also executed if the interface is merely reset but not yet disabled. ) b. SYSCLK activated. If the interface is disabled, the PHY reactivates its SYSCLK output when it detects that LPS has been reasserted. If the PHY has entered a low-power state, it takes between 5.3 ms to 7.3 ms for SYSCLK to be restored; if the PHY is not in a low-power state, SYSCLK is restored within 60 ns. The SYSCLK output is a 50% duty cycle square wave with a frequency of 49.152 MHz ±100 ppm (period of 20.345 ns). During the first seven cycles of SYSCLK, the PHY continues to drive the CTL and D terminals low. The LLC is also required to drive its CTL and D outputs low for one of the first six cycles of SYSCLK but to otherwise place its CTL and D outputs in a high-impedance state. The LLC continues to drive its LREQ output low during this time. c. Receive indicated. Upon the eighth SYSCLK cycle following reassertion of LPS, the PHY asserts the receive state on the CTL lines and the data-on indication (all ones) on the D lines for one or more cycles. d. Initialization complete. The PHY asserts the Idle state on the CTL lines and logic 0 on the D lines. This indicates that the PHY-LLC interface initialization is complete and normal operation may commence. The PHY accepts requests from the LLC via the LREQ line. TBS41AB3 data sheet document history DATE PAGE NUMBER REVISION 12/2002 10 Changed part number TSB41AB3I to TSB41AB3II 12/2002 20 Corrected value of Vendor_ID to 08_00_28h 12/2002 20 Corrected value of Product_ID to 43_41_95h

www.ti.com 15-Nov-2012 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Samples (Requires Login) TSB41AB3PFP ACTIVE HTQFP PFP 80 96 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TSB41AB3PFPG4 ACTIVE HTQFP PFP 80 96 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TSB41AB3 :

• Enhanced Product: TSB41AB3-EP NOTE: Qualified Version Definitions:

www.ti.com 15-Nov-2012 Addendum-Page 2

• Enhanced Product - Supports Defense, Aerospace and Medical Applications

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