TSB41AB1PHPG4

TSB41AB1_19 TI1 | Alldatasheet

Document overview

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Technical content

Features

/C0068IEEE 1394a-2000 Compliant Common Mode Noise Filter on Incoming TPBIAS /C0068Extended Resume Signaling for Compatibility With Legacy DV Devices, and Terminal- and Register-Compatibility With TSB41LV01, Allow Direct Isochronous Transmit to Legacy DV Devices With Any Link Layer Even When Root /C0068Power-Down Features to Conserve Energy in Battery Powered Applications Include: Automatic Device Power Down During Suspend, Device Power-Down Terminal, Link Interface Disable via LPS, and Inactive Ports Powered Down /C0068Failsafe Circuitry Senses Sudden Loss of Power to the Device and Disables the Port to Ensure That the Device Does Not Load TPBIAS of the Connected Device and Blocks Any Leakage Path From the Port Back to the Device Power Plane /C0068Software Device Reset (SWR) /C0068Industry Leading Low Power Consumption /C0068Ultralow-Power Sleep Mode /C0068Cable Power Presence Monitoring /C0068Cable Ports Monitor Line Conditions for Active Connection to Remote Node /C0068Data Interface to Link-Layer Controller Through 2/4/8 Parallel Lines at 49.152 MHz /C0068Interface to Link Layer Controller Supports Low Cost TI Bus-Holder Isolation and Optional Annex J Electrical Isolation /C0068Interoperable With Link-Layer Controllers Using 3.3 V /C0068Single 3.3-V Supply Operation /C0068Low-Cost 24.576-MHz Crystal Provides Transmit, Receive Data at 100/200/400 Mbits/s, and Link-Layer Controller Clock at

49.152 MHz

/C0068Low-Cost High-Performance 48/64-Pin TQFP (PHP/PAP) Thermally Enhanced Packages Increase Thermal Performance by up to 210% /C0068Meets Intel Mobile Power Guideline 2000 /C0068Available in 80-Ball, MicroStar Junior BGA (GQE) Package /C0068Available in 64-Ball, Pb-Free, MicroStar Junior BGA (ZQE) Package Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. † Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited. Copyright  2000 − 2004, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 FireWire is a trademark of Apple Computer, Incorporated. i.LINK is a trademark of Sony Kabushiki Kaisha TA Sony Corporation. Intel is a trademark of Intel Corporation. Other trademarks are the property of their respective owners. MicroStar Junior is a trademark of Texas Instruments Incorporated.

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

description

The TSB41AB1 provides the digital and analog transceiver functions needed to implement a one-port node in a cable-based IEEE 1394 network. The cable port incorporates one differential line transceiver. The transceiver includes circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB41AB1 is designed to interface with a link layer controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23, TSB12LV26, TSB12LV31, TSB12LV41 , TSB12LV42, or TSB12LV01A. The TSB41AB1 requires only an external 24.576-MHz crystal as a reference. An external clock may be provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates the required 393.216-MHz reference signal. This reference signal is internally divided to provide the clock signals used to control transmission of the outbound encoded strobe and data information. A 49.152-MHz clock signal is supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of the received data. The power-down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL. The TSB41AB1 supports an optional isolation barrier between itself and its LLC. When the ISO input terminal is tied high, the LLC interface outputs behave normally. When the ISO terminal is tied low, internal differentiating logic is enabled, and the outputs are driven such that they can be coupled through a capacitive or transformer galvanic isolation barrier as described in Annex J of IEEE Std 1394-1995 and in IEEE 1394a-2000 (section 5.9.4) (hereinafter referred to as Annex J type isolation). To operate with TI bus holder isolation the ISO terminal on the PHY must be high. Data bits to be transmitted through the cable port are received from the LLC on two, four or eight parallel paths (depending on the requested transmission speed) and are latched internally in the TSB41AB1 in synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded, and transmitted at 98.304, 196.608, or 393.216 Mbits/s (referred to as S100, S200, and S400 speeds, respectively) as the outbound data-strobe information stream. During transmission, the encoded data information is transmitted differentially on the TPB cable pair, and the encoded strobe information is transmitted differentially on the TPA cable pair. During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The serial data bits are split into two-, four-, or eight-bit parallel streams (depending upon the indicated receive speed), resynchronized to the local 49.152-MHz system clock and sent to the associated LLC. Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied twisted-pair bias voltage. The TSB41AB1 provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter capacitor of 1 µF. TPBIAS is typically V DD −0.2 V when the port is not connected to another node. The line drivers in the TSB41AB1 operate in a high-impedance current mode, and are designed to work with external 112-Ω line-termination resistor networks in order to match the 110-Ω cable impedance. One network is provided at each end of a twisted-pair cable. Each network is composed of a pair of series-connected 56-Ω resistors. The midpoint of the pair of resistors that is directly connected to the twisted-pair-A terminals is connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 description (continued) connected to the twisted-pair-B terminals is coupled to ground through a parallel R-C network with recommended values of 5 kΩ and 220 pF. The values of the external line termination resistors are designed to meet IEEE Std 1394-1995 when connected in parallel with the internal receiver circuits. An external resistor connected between the R0 and R1 terminals sets the driver output current, along with other internal operating currents. This current-setting resistor has a value of 6.34 kΩ ±1.0%. When the power supply of the TSB41AB1 is off while the twisted-pair cables are connected, the TSB41AB1 transmitter and receiver circuitry presents a high impedance to the cable and does not load the TPBIAS voltage at the other end of the cable. Fail-safe circuitry blocks any leakage path from the port back to the device power plane. The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, the TESTM terminal should be connected to V DD through a 1-kΩ resistor, SE should be tied to ground through a 1-kΩ resistor, and SM should be connected directly to ground. Four package terminals are used as inputs to set the default value for four configuration status bits in the self-ID packet, and are tied high through a 1-kΩ resistor or hardwired low as a function of the equipment design. The PC0–PC2 terminals are used to indicate the default power-class status for the node (the need for power from the cable or the ability to supply power to the cable). See Table 9 for power-class encoding. The C/LKON terminal is used as an input to indicate that the node is a contender for either isochronous resource manager (IRM) or for bus manager (BM). The TSB41AB1 supports suspend/resume as defined in the IEEE 1394a-2000 specification. The suspend mechanism allows pairs of directly connected ports to be placed into a low-power state (suspended state) while maintaining a port-to-port connection between bus segments. While in the suspended state, a port is unable to transmit or receive data transaction packets. However, a port in the suspended state is capable of detecting connection status changes and detecting incoming TPBIAS. When the port of the TSB41AB1 is suspended, all circuits except the band gap reference generator and bias detection circuit is powered down, resulting in significant power savings. For additional details of suspend/resume operation see IEEE 1394a-2000. The use of suspend/resume is recommended for new designs. The port transmitter and receiver circuitry is disabled during power down (when the PD input terminal is asserted high), during reset (when the RESET input terminal is asserted low), when no active cable is connected to the port, or when controlled by the internal arbitration logic. The TPBIAS output is disabled during power down, during reset, or when the port is disabled as commanded by the LLC. The cable-not-active (CNA) output terminal (64-terminal PAP package only) is asserted high when there are no twisted-pair cable ports receiving incoming bias (that is, they are either disconnected or suspended), and can be used along with LPS to determine when to power down the TSB41AB1. The CNA output is not debounced. When the PD terminal is asserted high, the CNA detection circuitry is enabled (regardless of the previous state of the ports) and a pulldown is activated on the RESET terminal so as to force a reset of the TSB41AB1 internal logic. The LPS (link power status) terminal works with the C/LKON terminal to manage the power usage in the node. The LPS signal from the LLC is used in conjunction with the LCtrl bit (see Table 1 and Table 2 in the Application Information section) to indicate the active/power status of the LLC. The LPS signal is also used to reset, disable, and initialize the PHY-LLC interface (the state of the PHY-LLC interface is controlled solely by the LPS input, regardless of the state of the LCtrl bit). The LPS input is considered inactive if it remains low for more than 2.6 µs and is considered active otherwise. When the TSB41AB1 detects that LPS is inactive, it places the PHY-LLC interface into a low-power reset state in which the CTL and D outputs are held in the logic zero state and the LREQ input is ignored; however, the SYSCLK output remains active. If the LPS input remains low for more than 26 µs, the PHY-LLC interface is put into a low-power disabled state in which the SYSCLK output is also held inactive. The PHY-LLC interface is also held in the disabled state during hardware reset. The TSB41AB1 continues the necessary repeater functions

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 description (continued) required for normal network operation regardless of the state of the PHY-LLC interface. When the interface is in the reset or disabled state and LPS is again observed active, the PHY initializes the interface and returns it to normal operation. When the PHY-LLC interface is in the low-power disabled state, the TSB41AB1 automatically enters a low-power mode if the port is inactive (disconnected, disabled, or suspended). In this low-power mode, the TSB41AB1 disables its internal clock generators and also disables various voltage and current reference circuits depending on the state of the port (some reference circuitry must remain active in order to detect new cable connections, disconnections, or incoming TPBIAS, for example). The lowest power consumption (the ultralow-power sleep mode) is attained when the port is either disconnected, or disabled with the port interrupt enable bit cleared. The TSB41AB1 exits the low-power mode when the LPS input is asserted high or when a port event occurs which requires that the TSB41AB1 become active in order to respond to the event or to notify the LLC of the event (for example, incoming bias is detected on a suspended port, a disconnection is detected on a suspended port, a new connection is detected on a nondisabled port, etc.). The SYSCLK output becomes active (and the PHY-LLC interface is initialized and becomes operative) within 7.3 ms after LPS is asserted high when the TSB41AB1 is in the low-power mode. The PHY uses the C/LKON terminal to notify the LLC to power up and become active. When activated, the C/LKON signal is a square wave of approximately 163-ns period. The PHY activates the C/LKON output when the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet addressed to this node is received, or when a PHY interrupt occurs. The PHY deasserts the C/LKON output when the LLC becomes active (both LPS active and the LCtrl bit set to 1). The PHY also deasserts the C/LKON output when a bus reset occurs unless a PHY interrupt condition exists which would otherwise cause C/LKON to be active. PHP package terminal diagram 14 15 AGND AV DD AGND TPBIAS TPA+ TPA− TPB+ TPB− AGND AV DD SYSCLK CTL0 CTL1 PD 17 18 19 20 47 46 45 44 4348 42 40 39 3841 21 22 23 24 PHP PACKAGE (TOP VIEW) TSB41AB1 PLLGND PLLV FILTER1 FILTER0 LREQ DGND DGND DV TESTM SE SM C/LKON PC1 PC2 ISO CPS DV RESET XO XI DGND LPS PC0 DD DV DD DD DD NOTE A: For latch-up considerations, it is recommended that the TESTM terminal have a pullup resistor.

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 PAP package terminal diagram 12 3 AGND AV DD AV DD SM SE TESTM DV DD DV DD CPS ISO PC2 PC1 PC0 C/LKON DGND DGND AGND AGND AV DD AV DD RESET FILTER0 FILTER1 PLLV DD PLLGND PLLGND XI XO DV DD DV DD DGND DGND 56 78 TPB− TPBIAS 47 46 45 44 4348 42 NC NC NC NC AV CNA CTL0 CTL1 40 39 3841 91 0 1 1 1 2 1 3 37 36 LREQ TPA+ TPA− 35 34 33 14 15 16 PD LPS NC TPB+ AGND AGND AGND NCSYSCLK PAP PACKAGE (TOP VIEW)DD TSB41AB1 NOTES: A. Pin 16 (NC) could be tied to VDD for backward compatibility with the TSB41LV02A device. B. For latch-up considerations, it is recommended that the TESTM terminal have a pullup resistor.

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 GQE package terminal diagram—NC connections (top view) B (TOP VIEW) GQE PACKAGE TERMINAL DIAGRAM AGND AVDD AGND SM TESTM PC2 DGND TPA− TPB+ AGND TPBIAS TPA+ TPB− AGND AVDD SE CPS DVDD /ISO PC1 PC0 RESET FILTER0 FILTER1 PLLVDD PLLGND PLLGND AVDD XI XO DGND LREQ CNA DVDD C/LKON CTL0 CTL1 PD LPS SYSCLK NCNCNC4NC4NC4 NCNC3NC3NC2NC2 NC1NC1NC2NC2NC2 NC1NC1NC1NC2NC NCNC1NCNC NC NC NC NC2 NC1 NC3 A B C D E F G H J 123456789 NOTES: A. NC − not connected B. For latch-up considerations, it is recommended that the TESTM terminal have a pullup resistor.

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 ZQE package terminal diagram—NC connections (top view) B (TOP VIEW) ZQE PACKAGE TERMINAL DIAGRAM AGND AVDD AGND SM TESTM PC2 DGND TPA− TPB+ AGND TPBIAS TPA+ TPB− AGND AVDD SE CPS DVDD /ISO PC1 PC0 RESET FILTER0 FILTER1 PLLVDD PLLGND PLLGND AVDD XI XO DGND LREQ CNA DVDD C/LKON CTL0 CTL1 PD LPS SYSCLK NC3NC3NC2 NC1NC2NC2 NC1NC2 NC NC NC NC2 NC1 NC3 A B C D E F G H J 123456789 NOTES: A. NC − not connected B. For latch-up considerations, it is recommended that the TESTM terminal have a pullup resistor.

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 GQE package terminal diagram—NC connections (bottom view) (BOTTOM VIEW) GQE PACKAGE TERMINAL DIAGRAM AGND AVDD AGND SM TESTM PC2 DGND TPA− TPB+ AGND TPBIAS TPA+ TPB− AGND AVDD SE CPS DVDD /ISO PC1 PC0 RESET FILTER0 FILTER1 PLLVDD PLLGND PLLGND AVDD XI XO DGND LREQ CNA DVDD C/LKON CTL0 CTL1 PD LPS SYSCLK B NC NC NC4 NC4 NC4 NC NC3 NC3 NC2 NC2 NC1 NC1 NC2 NC2 NC2 NC1 NC1 NC1 NC2 NC NC NC1 NC NC NC NC NC NC2 NC1 NC3 A B C D E F G H J 123456789 NOTES: A. NC − not connected B. For latch-up considerations, it is recommended that the TESTM terminal have a pullup resistor.

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 ZQE package terminal diagram—NC connections (bottom view) (BOTTOM VIEW) ZQE PACKAGE TERMINAL DIAGRAM AGND AVDD AGND SM TESTM PC2 DGND TPA− TPB+ AGND TPBIAS TPA+ TPB− AGND AVDD SE CPS DVDD /ISO PC1 PC0 RESET FILTER0 FILTER1 PLLVDD PLLGND PLLGND AVDD XI XO DGND LREQ CNA DVDD C/LKON CTL0 CTL1 PD LPS SYSCLK B NC3 NC3 NC2 NC1 NC2 NC2 NC1 NC2 NC NC NC NC2 NC1 NC3 A B C D E F G H J 123456789 NOTES: A. NC − not connected B. For latch-up considerations, it is recommended that the TESTM terminal have a pullup resistor.

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 functional block diagram Received Data Decoder/RetimerLink Interface I/O Arbitration and Control State Machine Logic Bias Voltage and Current Generator Transmit Data Encoder Cable Port Crystal Oscillator, PLL System, and Clock Generator TPA+ CPS TPA− TPB+ TPB− XI XO FILTER0 FILTER1 LPS ISO CNA † SYSCLK LREQ CTL0 CTL1 PC0 PC1 PC2 C/LKON TPBIAS PD RESET † CNA output is only available in the 64-pin PAP package

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions TERMINAL NAME NUMBER TYPE I/O DESCRIPTION NAME PAP PHP GQE/ZQE TYPE I/O DESCRIPTION AGND 32, 33, 39, 48, 49, 50 26, 32, A9, B9, D9, J8 Supply − Analog circuit ground terminals. These terminals should be tied together to the low-impedance circuit board ground plane. AV DD 30, 31, 42, 51, 25, 35 B8, C8, Supply − Analog circuit power terminals. A combination of high frequency decoupling capacitors near each terminal is suggested, such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering capacitors are also recommended. These supply terminals are separated from PLLVDD and DVDD inside the device to provide noise isolation. They should be tied at a low-impedance point on the circuit board. C/LKON 19 15 J1 CMOS I/O Bus manager contender programming input and link-on output. On hardware reset, this terminal is used to set the default value of the contender status indicated during self-ID. Programming is done by tying the terminal through a 10-kΩ resistor to a high (contender) or low (not contender). The resistor allows the link-on output to override the input. However, it is recommended that this terminal should be programmed low, and that the contender status be set via the C register bit. If the TSB41AB1 is used with an LLC that has a dedicated terminal for monitoring LKON and also setting the contender status, then a 1-kΩ series resistor should be placed on the LKON line between the PHY and LLC to prevent bus contention. Following hardware reset, this terminal is the link-on output, which is used to notify the LLC to power up and become active. The link-on output is a square-wave signal with a period of approximately 163 ns (8 SYSCLK cycles) when active. The link-on output is otherwise driven low, except during hardware reset when it is high-impedance. The link-on output is activated if the LLC is inactive (LPS inactive or the LCtrl bit cleared) and when: a) the PHY receives a link-on PHY packet addressed to this node, or b) the PEI (port-event interrupt) register bit is 1, or c) any of the CTOI (configuration-time-out interrupt), CPSI (cable-power-status interrupt), or STOI (state-time-out interrupt) register bits are 1 and the RPIE (resuming-port interrupt enable) register bit is also 1. Once activated, the link-on output continues active until the LLC becomes active (both LPS active and the LCtrl bit set). The PHY also deasserts the link-on output when a bus reset occurs unless the link-on output would otherwise be active because one of the interrupt bits is set (that is, the link-on output is active due solely to the reception of a link-on PHY packet). NOTE: If an interrupt condition exists which would otherwise cause the link-on output to be activated if the LLC were inactive, the link-on output is activated when the LLC subsequently becomes inactive. CNA 3 N/A B2 CMOS O Cable-not-active output. This terminal is asserted high when there is no incoming bias voltage. CNA is not valid at intial power up until a device hard reset is performed. CPS 24 20 J5 CMOS I Cable power status input. This terminal is normally connected to cable power through a 400-kΩ resistor. This circuit drives an internal comparator that is used to detect the presence of cable power. This terminal should be tied directly to DGND through a 1-kΩ resistor if the application does not require it to be used. CTL0 CTL1 CMOS I/O Control I/Os. These bidirectional signals control communication between the TSB41AB1 and the LLC. Bus holders are built into these terminals.

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions (Continued) TERMINAL NAME NUMBER TYPE I/O DESCRIPTION NAME PAP PHP GQE/ZQE TYPE I/O DESCRIPTION CMOS I/O Data I/Os. These are bidirectional data signals between the TSB41AB1 and the LLC. Bus holders are built into these terminals. DGND 17, 18, 63, 64 14, 46, B3, H2 Supply − Digital circuit ground terminals. These terminals should be tied together to the low-impedance circuit board ground plane. DV DD 25, 26, 61, 62 21, 44, A3, H5 Supply − Digital circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal is suggested, such as paralleled 0.1µF and 0.001µF. Lower frequency 10-µF filtering capacitors are also recommended. These supply terminals are separated from PLLVDD and AVDD inside the device to provide noise isolation. They should be tied at a low-impedance point on the circuit board. FILTER0 FILTER1 CMOS I/O PLL filter terminals. These terminals are connected to an external capacitor to form a lag-lead filter required for stable operation of the internal frequency multiplier PLL running from the crystal oscillator. A 0.1-µF ±10% capacitor is the only external component required to complete this filter. ISO 23 19 H4 CMOS I Link interface isolation control input. This terminal controls the operation of output differentiation logic on the CTL and D terminals. If an optional Annex J type isolation barrier is implemented between the TSB41AB1 and LLC, the ISO terminal should be tied low to enable the differentiation logic. If no isolation barrier is implemented (direct connection), or TI bus holder isolation is implemented, the ISO terminal should be tied high through a pullup to disable the differentiation logic. For additional information see the TI application note Galvanic Isolation of the IEEE 1394-1995 Serial Bus, literature number SLLA011. LPS 15 13 H1 CMOS I Link power status input. This terminal monitors the active/power status of the link layer controller and controls the state of the PHY-LLC interface. This terminal should be connected through a 10-kΩ resistor either to the VDD supplying the LLC, or to a pulsed output which is active when the LLC is powered (see Figure 13). A pulsed signal should be used when an isolation barrier exists between the LLC and PHY (see Figure 14). The LPS input is considered inactive if it is sampled low by the PHY for more than 2.6 µs (128 SYSCLK cycles), and is considered active otherwise (that is, asserted steady high or an oscillating signal with a low time less than 2.6 µs). The LPS input must be high for at least 21 ns to assure that a high is observed by the PHY. When the TSB41AB1 detects that LPS is inactive, it places the PHY-LLC interface into a low-power reset state. In the reset state, the CTL and D outputs are held in the logic zero state and the LREQ input is ignored; however, the SYSCLK output remains active. If the LPS input remains low for more than 26 µs (1280 SYSCLK cycles), the PHY-LLC interface is put into a low-power disabled state in which the SYSCLK output is also held inactive. The PHY-LLC interface is placed into the disabled state upon hardware reset. The LLC is considered active only if both the LPS input is active and the LCtrl register bit is set to 1, and is considered inactive if either the LPS input is inactive or the LCtrl register bit is cleared to 0. LREQ 1 48 A2 CMOS I LLC request input. The LLC uses this input to initiate a service request to the TSB41AB1. Bus holder is built into this terminal.

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions (Continued) TERMINAL NAME NUMBER TYPE I/O DESCRIPTION NAME PAP PHP GQE ZQE TYPE I/O DESCRIPTION NC C4, C6, C7, D7, F3, F8, G3, G4, G8, H8 F8, G8, − − Each of these terminals is not connected to the silicon device. NC: Group 1 B4, C5, D3, D4, D5, E3, B4, D5, Supply − Each of these terminals is not connected to the silicon device, but they are connected to each other. It is recommended this group of terminals be used for a via connection to the GND plane in application board. NC: Group 2 D6, E5, E6, E7, E8, F6, D6, E5, E6, E8, Supply − Each of these terminals is not connected to the silicon device, but they are connected to each other. It is recommended this group of terminals be used for a via connection to the VDD −supply plane in application board. NC: Group 3 F4, F5, F4, F5, Supply − Each of these terminals is not connected to the silicon device, but they are connected to each other. It is recommended this group of terminals be used for a via connection to the GND plane in application board. NC: Group 4 G5, G6, − Supply − Each of these terminals are not connected to the silicon device, but they are connected to each other. It is recommended this group of terminals be used for a via connection to the VDD −supply plane in application board. PC0 PC1 PC2 CMOS I Power class programming inputs. On hardware reset, these inputs set the default value of the power class indicated during self-ID. Programming is done by tying these terminals high or low. See Table 9 for encoding. PD 14 12 G2 G2 CMOS I Power-down input. A high on this terminal turns off all internal circuitry except the cable-active monitor circuits, which control the CNA output (64-terminal PAP package only). Asserting the PD input high also activates an internal pulldown on the RESET terminal to force a reset of the internal control logic. (PD is provided for legacy compatibility and is not recommended for power management in place of IEEE 1394a-2000 suspend/resume LPS and C/LKON features.) PLLGND 57, 58 41 A6, B5 A6, Supply − PLL circuit ground terminals. These terminals should be tied together to the low-impedance circuit board ground plane. PLLV DD 56 40 B6 B6 Supply − PLL circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal is suggested, such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering capacitors are also recommended. This supply terminal is separated from DVDD and AVDD inside the device to provide noise isolation. It should be tied at a low-impedance point on the circuit board. Bias − Current setting resistor terminals. These terminals are connected through an external resistor to set the internal operating currents and cable driver output currents. A resistance of 6.34 kΩ ±1.0% is required to meet the IEEE Std 1394-1995 output voltage limits. NOTE: It is strongly recommended that signals tied to VDD use a 1-kΩ resistor (minimum). Tying signals directly to VCC may result in ESD failures. Signals tied to ground may be tied directly.

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions (Continued) TERMINAL NAME NUMBER TYPE I/O DESCRIPTION NAME PAP PHP GQE/ZQE TYPE I/O DESCRIPTION RESET 53 37 A8 CMOS I Logic reset input. Asserting this terminal low resets the internal logic. An internal pullup resistor to VDD is provided so only an external delay capacitor is required for proper power-up operation (see power-up reset in the Application Information section). The RESET terminal also incorporates an internal pulldown which is activated when the PD input is asserted high. This input is otherwise a standard logic input, and may also be driven by an open-drain type driver. SE 28 23 H6 CMOS I Test control input. This input is used in manufacturing test of the TSB41AB1. For normal use this terminal may be tied to GND through a 1-kΩ pulldown resistor or it may be tied to GND directly. SM 29 24 J7 CMOS I Test control input. This input is used in manufacturing test of the TSB41AB1. For normal use this terminal should be tied to GND. SYSCLK 2 1 A1 CMOS O System clock output. Provides a 49.152-MHz clock signal, synchronized with data transfers, to the LLC. TESTM 27 22 J6 CMOS I Test control input. This input is used in manufacturing test of the TSB41AB1. For normal, use this terminal should be tied to VDD through a 1-kΩ resistor. TPA+ 37 30 F9 Cable I/O Twisted-pair cable A differential signal terminals. Board traces from the pair of positive and negative differential signal terminals should be kept matched and as TPA− 36 29 G9 Cable I/O positive and negative differential signal terminals should be kept matched and as short as possible to the external load resistors and to the cable connector. TPB+ 35 28 H9 Cable I/O Twisted-pair cable B differential signal terminals. Board traces from the pair of positive and negative differential signal terminals should be kept matched and as TPB− 34 27 J9 Cable I/O positive and negative differential signal terminals should be kept matched and as short as possible to the external load resistors and to the cable connector. TPBIAS 38 31 E9 Cable I/O Twisted-pair bias output. This provides the 1.86-V nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receivers, and for signaling to the remote nodes that there is an active cable connection. XI XO Crystal − Crystal oscillator inputs. These terminals connect to a 24.576-MHz parallel resonant fundamental mode crystal. The optimum values for the external shunt capacitors are dependent on the specifications of the crystal used (see crystal selection in the Application Information section). When an external clock source is used, XI should be the input and XO should be left open, and the clock must be supplied before the device is taken out of reset. NOTE: It is strongly recommended that signals tied to VDD use a 1-kΩ resistor (minimum). Tying signals directly to VCC may result in ESD failures. Signals tied to ground may be tied directly.

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† † Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ‡ ABOVE T A = 25°C TA = 70°C POWER RATING PAP § 4.78 W 38 mW/°C 3.06 W PAP ¶ 2.13 W 17 mW/°C 1.36 W PAP # 2.08 W 16 mW/°C 1.33 W PHP § 3.92 W 31.4 mW/°C 2.51 W PHP ¶ 1.9 W 10.4 mW/°C 1.22 W PHP # 1.45 W 11 mW/°C 0.93 W GQE || 1.76 W 17.6 mW/°C 0.97 W GQE # 0.84 W 8.4 mW/°C 0.46 W ZQE || 1.71 W 17.1 mW/°C 0.94 W ZQE # 0.83 W 8.4 mW/°C 0.45 W ‡ This is the inverse of the traditional junction-to-ambient thermal resistance (RθJA). § 1 oz. trace and copper pad with solder ¶ 1 oz. trace and copper pad without solder # Standard JEDEC low-K board ||Standard JEDEC high-K board For more information, refer to TI technical brief PowerPAD Thermally Enhanced Package, TI literature number SLMA002. PowerPAD is a trademark of Texas Instruments.

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 recommended operating conditions MIN TYP † MAX UNIT Supply voltage, VDD Source power node 3 3.3 3.6 VSupply voltage, VDD Non-source power node 2.7‡ 3 3.6 V LREQ, CTL0, CTL1, D0−D7 2.6 V High-level input voltage, VIH C/LKON, PC0, PC1, PC2, ISO, PD 0.7 VDD VHigh-level input voltage, VIH RESET 0.6 VDD V LREQ, CTL0, CTL1, D0−D7 1.2 V Low-level input voltage, VIL C/LKON, PC0, PC1, PC2, ISO, PD 0.2 VDD VLow-level input voltage, VIL RESET 0.3 VDD V Output current, IO TPBIAS outputs −5.6 1.3 mA Maximum junction temperature, TJ R θJA = 26.1°C/W, T A = 70°C 78.9Maximum junction temperature, TJ (see RθJA values listed in thermal characteristics table) 64PAP R θJA = 58.6°C/W, T A = 70°C 90 °C(see RθJA values listed in thermal characteristics table) 64PAP R θJA = 60.1°C/W, T A = 70°C 90.5 C Maximum junction temperature, TJ R θJA = 31.9°C/W, T A = 70°C 80.9Maximum junction temperature, TJ (see RθJA values listed in thermal characteristics table) 48PHP R θJA = 65.8°C/W, T A = 70°C 92.5 °C(see RθJA values listed in thermal characteristics table) 48PHP R θJA = 85.6°C/W, T A = 70°C 99.3 C Maximum junction temperature, TJ (see RJA values listed in thermal R θJA = 56.61°C/W, T A = 70°C 80.19 J (see RθJA values listed in thermal characteristics table) 80GQE R θJA = 118.12°C/W, T A = 70°C 91.26 Maximum junction temperature, TJ (see RJA values listed in thermal R θJA = 58.32°C/W, T A = 70°C 80.50 J (see RθJA values listed in thermal characteristics table) 64ZQE R θJA = 119.63°C/W, T A = 70°C 91.53 Differential input voltage, VID Cable inputs, during data reception 118 260 mVDifferential input voltage, VID Cable inputs, during arbitration 168 265 mV Common-mode input voltage, VIC TPB cable inputs, source power node 0.4706 2.515 VCommon-mode input voltage, VIC TPB cable inputs, nonsource power node 0.4706 2.015‡ V Power-up reset time, t(pu) RESET input 2 ms TPA, TPB cable inputs, S100 operation ±1.08 Receive input jitter TPA, TPB cable inputs, S200 operation ±0.5 nsReceive input jitter TPA, TPB cable inputs, S400 operation ±0.315 ns Between TPA and TPB cable inputs, S100 operation ±0.8 Receive input skew Between TPA and TPB cable inputs, S200 operation ±0.55 nsReceive input skew Between TPA and TPB cable inputs, S400 operation ±0.5 ns † All typical values are at VDD = 3.3 V and TA = 25°C. ‡ For a node that does not source power; see Section 4.2.2.2 in IEEE 1394a-2000.

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005 17POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics over recommended ranges of operating conditions (unless otherwise noted) driver PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOD Differential output voltage 56 Ω, See Figure 1 172 265 mV I(DIFF) Driver difference current, TPA+, TPA−, TPB+, TPB−Drivers enabled, speed signaling off −1.05† 1.05† mA I(SP200) Common mode speed signaling current, TPB+, TPB−S200 speed signaling enabled−4.84‡ −2.53‡ mA I(SP400) Common mode speed signaling current, TPB+, TPB−S400 speed signaling enabled−12.4‡ −8.1‡ mA V(OFF) Off state differential voltage Drivers disabled, See Figure 1 20 mV † Limits defined as algebraic sum of TPA+ and TPA− driver currents. Limits also apply to TPB+ and TPB− algebraic sum of driver currents. ‡ Limits defined as absolute limit of each of TPB+ and TPB− driver currents receiver PARAMETER TEST CONDITIONS MIN TYP MAX UNIT zid Differential impedance Drivers disabled 4 7 kΩ zid Differential impedance Drivers disabled 4 pF zic Common-mode impedance Drivers disabled 20 kΩ zic Common-mode impedance Drivers disabled 24 pF V(TH−R) Receiver input threshold voltage Drivers disabled −30 30 mV V(TH−CB) Cable bias detect threshold, TPB cable inputsDrivers disabled 0.6 1 V V(TH+) Positive arbitration comparator threshold voltage Drivers disabled 89 168 mV V(TH−) Negative arbitration comparator threshold voltage Drivers disabled −168 −89 mV V(TH−SP200) Speed signal threshold TPBIAS−TPA common-mode voltage, drivers disabled 49 131 mV V(TH−SP400) Speed signal threshold TPBIAS−TPA common-mode voltage, drivers disabled 314 396 mV

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics over recommended ranges of operating conditions (unless otherwise noted) (continued) device PARAMETER TEST CONDITIONS MIN TYP MAX UNIT See Note 2 48 IDD Supply current See Note 3 42 mAIDD Supply current See Note 4 41 mA IDD(ULP) Supply current, ultralow-power mode VDD = 3.3 V, TA = 25°C, Port disabled or unconnected, PD = 0 V, LPS = 0 V 150 µA IDD(PD) Supply current, power-down mode PD = VDD , VDD = 3.3 V, TA= 25°C 150 µA V(TH) Power status threshold, CPS input† 400-kΩ resistor† 4.7 7.5 V VOH High-level output voltage, CTL0, CTL1,VDD = 2.7 V, IOH = −4 mA 2.2 VVOH High-level output voltage, CTL0, CTL1, D0−D7, CNA, C/LKON, SYSCLK outputs VDD = 3 to 3.6 V, IOH = −4 mA 2.8 V VOL Low-level output voltage, CTL0, CTL1, D0−D7, CNA, C/LKON, SYSCLK outputs IOL = 4 mA 0.4 V VOH(AJ) High-level Annex J output voltage, CTL0, CTL1, D0−D7, C/LKON, SYSCLK outputs Annex J: IOH = −9 mA, ISO = 0 V, VDD ≥ 3 V VDD −0.4 V VOL(AJ) Low-level Annex J output voltage, CTL0, CTL1, D0−D7, C/LKON, SYSCLK outputs Annex J: IOL = 9 mA, ISO = 0 V, VDD ≥ 3 V 0.4 V I(BH+) Positive peak bus holder current, D0−D7, CTL0, CTL1, LREQ ISO = 3.6 V, VDD = 3.6 V, VI = 0 V to VDD 0.05 1 mA I(BH−) Negative peak bus holder current, D0−D7, CTL0, CTL1, LREQ ISO = 3.6 V, VDD = 3.6 V, VI = 0 V to VDD −1.0 −0.05 mA II Input current, LREQ, LPS, PD, TESTM, SM, PC0–PC2 inputs ISO = 0 V, VDD = 3.6 V 5 µA IOZ Off-state output current, CTL0, CTL1, D0–D7, C/LKON I/Os VO = VDD or 0 V ±5 µA I(IRST) Pullup current, RESET input VI = 1.5 V or 0 V −90 −20 µA I(SE−Pd) Pullup/pulldown current, SE input VI = VDD/2 or VDD 5 50 µA VIT+ Positive input threshold voltage, LREQ, CTL0, CTL1, D0–D7 inputs‡ ISO = 0 V, VDD = 3 V to 3.6 VVDD /2+0.3 VDD /2+0.9 VVIT+ Positive input threshold voltage, LPS inputs ISO = 0 V, VDD = 3 V to 3.6 V Vref = 0.4 VDD VREF +1 V VIT− Negative input threshold voltage, LREQ, CTL0, CTL1, D0–D7 inputs‡ ISO= 0 V, VDD = 3 V to 3.6 VVDD /2−0.9 VDD /2−0.3 VVIT− Negative input threshold voltage, LPS inputs ISO= 0 V, Vref = 0.4 VDD , VDD = 3 V to 3.6 V Vref+0.2 V VO TPBIAS output voltage§ At rated IO current 1.665 2.015 V † Measured at cable power side of resistor ‡ This parameter applicable only when ISO low § TPBIAS is typically VDD −0.2 V when the port is not connected. NOTES: 2. Transmit maximum packet (one port transmitting maximum size isochronous packet – 4096 bytes, sent on every isochronous interval, S400, data value of CCCCCCCCh), VDD = 3.3 V, TA = 25°C. 3. Receive typical packet (one port receiving DV packets on every isochronous interval, S100), VDD = 3.3 V, TA = 25°C. 4. Idle (one port transmitting cycle starts), VDD = 3.3 V, TA = 25°C.

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005 19POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 thermal characteristics, PAP package PARAMETER TEST CONDITIONS † MIN TYP MAX UNIT R θJA Junction-to-ambient thermal resistanceBoard-mounted, no air flow, high conductivity TI-recommended test board, chip soldered or 26 °C/W R θJC Junction-to-case-thermal resistance TI-recommended test board, chip soldered or greased to thermal land with 1 oz. copper 5.9 °C/W R θJA Junction-to-ambient thermal resistanceBoard-mounted, no air flow, high conductivity TI-recommended test board with thermal land, but 58.6 °C/W R θJC Junction-to-case thermal resistance TI-recommended test board with thermal land, but no solder or grease thermal connection to thermal land with 1 oz. copper 5.9 °C/W R θJA Junction-to-ambient thermal resistanceBoard-mounted, no air flow, low conductivity 60.1 °C/W R θJC Junction-to-case thermal resistance Board-mounted, no air flow, low conductivity JEDEC test board with 1 oz. copper 5.9 °C/W † Use of thermally enhanced PowerPad PAP package is assumed in all three test conditions. thermal characteristics, PHP package PARAMETER TEST CONDITIONS † MIN TYP MAX UNIT R θJA Junction-to-ambient thermal resistanceBoard-mounted, no air flow, high conductivity TI-recommended test board, chip soldered or 31.9 °C/W R θJC Junction-to-case-thermal resistance TI-recommended test board, chip soldered or greased to thermal land with 1 oz. copper 6.2 °C/W R θJA Junction-to-ambient thermal resistanceBoard-mounted, no air flow, high conductivity TI-recommended test board with thermal land, but 65.8 °C/W R θJC Junction-to-case thermal resistance TI-recommended test board with thermal land, but no solder or grease thermal connection to thermal land with 1 oz. copper 6.2 °C/W R θJA Junction-to-ambient thermal resistanceBoard-mounted, no air flow, low conductivity 85.7 °C/W R θJC Junction-to-case thermal resistance Board-mounted, no air flow, low conductivity JEDEC test board with 1 oz. copper 6.2 °C/W † Use of thermally enhanced PowerPad PHP package is assumed in all three test conditions. thermal characteristics, GQE package PARAMETER TEST CONDITIONS MIN TYP MAX UNIT R θJA Junction-to-ambient thermal resistanceBoard-mounted, no air flow, JEDEC low-k test 118.12 °C/W R θJC Junction-to-case-thermal resistance Board-mounted, no air flow, JEDEC low-k test board, no thermal vias used on board 38.62 °C/W R θJA Junction-to-ambient thermal resistanceBoard-mounted, no air flow, JEDEC high-k test 56.61 °C/W R θJC Junction-to-case-thermal resistance Board-mounted, no air flow, JEDEC high-k test board, no thermal vias used on board 38.62 °C/W thermal characteristics, ZQE package PARAMETER TEST CONDITIONS MIN TYP MAX UNIT R θJA Junction-to-ambient thermal resistanceBoard-mounted, no air flow, JEDEC low-k test 119.63 °C/W R θJC Junction-to-case-thermal resistance Board-mounted, no air flow, JEDEC low-k test board, no thermal vias used on board 39.03 °C/W R θJA Junction-to-ambient thermal resistanceBoard-mounted, no air flow, JEDEC high-k test 58.32 °C/W R θJC Junction-to-case-thermal resistance Board-mounted, no air flow, JEDEC high-k test board, no thermal vias used on board 39.09 °C/W

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005

20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 switching characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Jitter, transmit Between TPA and TPB ±0.15 ns Skew, transmit Between TPA and TPB ±0.1 ns th Hold time, CTL0, CTL1, D0–D7, LREQ after SYSCLK50% to 50%, See Figure 2 2 ns tsu Setup time, CTL0, CTL1, D0–D7, LREQ to SYSCLK 50% to 50%, See Figure 2 5 ns td Delay time, SYSCLK to CTL0, CTL1, D0–D7 50% to 50%, See Figure 3 2‡ ns tr TP differential rise time, transmit 10% to 90%, at 1394 connector 0.5 1.2 ns tf TP differential fall time, transmit 90% to 10%, at 1394 connector 0.5 1.2 ns ‡ Test Conditions: 3.3 VCC , TA = 25°C

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005

22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

APPLICATION INFORMATION

Details regarding connection of components to the various terminals of the TSB41AB1 are discussed primarily in entries for each terminal in the terminal functions table. Figure 4, Figure 5, Figure 6, and Figure 8 are diagrammatic views showing the connections for all required external components. Note: All component connection diagrams are top view. 1 kΩ † See Figure 10, Figure 11, and Figure 12. ‡ See Figure 13 and Figure 14. § See Terminal Functions Table. 123456789 1 0 1 1 1 2 373839404142434445464748 RESET FILTER0 FILTER1 PLLV DD PLLGND XI XO DV DD DV DD DGND DGND LREQ SYSCLK CNA CTL0 PD DGND C/LKON PC0 PC1 PC2 ISO CPS DV DD TESTM SE SM DDAV AGND TPB− TPB+ TPA− TPA+ TPBIAS NC AGND 13 14 15 16 33343536 CTL1 LPS NC DGND DV DD AV DD AV DD AGNDAGND NC NC NC AGND AGND AV DD AV DD NC 0.1 µF 0.001 µF 0.001 µF VDD 6.34 kΩ ± 1% TP Cables Interface Connection † 0.001 µF 0.001 µF 0.1 µF VDD 1 kΩ (Optional) § 0.1 µF 0.001 µF 0.001 µF VDD DGND400 kΩ Cable Power ISO Power-Class Programming 10 kΩ LKON Bus Manager 0.001 µF0.1 µF VDD12 pF¶ 12 pF¶ 24.576 MHz 0.01 µF1.0 µF VDD 0.1 µF 0.1 µF 0.1 µF 0.001 µF 0.001 µF VDD CNA OUT TSB41AB1 POWER DOWN ¶ See crystal selection section for more details PLLGND Figure 4. External Component Connections (PAP)

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005 23POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 component connection (continued) † See Figure 10, Figure 11, and Figure 12. ‡ See Figure 13 and Figure 14. § See Terminal Functions Table. 1234 56789 1 0 1 1 1 2 252627282930313233343536 RESET FILTER0 FILTER1 PLLV DD PLLGND XI XO DV DD DV DD DGND DGND SYSCLK CTL0 LPS DGND C/LKON PC0 PC1 PC2 ISO CPS TESTM SE SM TPB− AGND TPBIAS TPB+ TPA− AGND CTL1 DV DD AGND 0.1 µF 0.001 µF 0.001 µF VDD 6.34 kΩ ± 1% TP Cables Interface Connection † 0.1 µF 0.001 µF 0.001 µF VDD DGND 400 kΩ Cable Power ISO Power-Class Programming 10 kΩ LKON Bus Manager 0.001 µF0.1 µF VDD

24.576 MHz

0.01 µF1.0 µF VDD 0.1 µF 0.1 µF 37 POWER DOWN TSB41AB1 PD LREQ DDAV TPA+ DDAV 1 kΩ (Optional) § 1 kΩ 12 pF¶ 12 pF¶ ¶ See crystal selection section for more details Figure 5. External Component Connections (PHP)

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005

24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 component connection (continued) † See Figure 10, Figure 11, and Figure 12. ‡ See Figure 13 and Figure 14. § See Terminal Functions Table. ¶ See crystal selection section for more details AB CDE FG H J NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC SYSCLK CTL0 CNA CTL1 PD LPS C/LKON PC0 DGND PC1 PC2 /ISO CPS DVDD TESTM SE SM AVDD AGND /RESET FILTER0 FILTER1 PLLVDD PLLGND PLLGND XI XO DGND DVDD LREQ AGND AVDD AGND AVDD AGND TPBIAS TPA+ TPA− TPB+ TPB− CNA OUT POWER DOWN 10 k Bus Manager LKON Power−Class Programming /ISO 400 k Cable Power 0.001 0.001 0.1 VDD 1 k (Optional) § 0.001 0.001 0.1 VDD VDD 6.34 k TP Cables Interface Connections † 0.1 0.1 VDD 0.0010.1 VDD 12 pF ¶ 12 pF ¶ 0.0010.0010.1 400 k 1 k/C0087 /C0109F/C0109F/C0109F /C0109F /C0109F /C0109F /C0109F/C0109F/C0109F /C0109F /C0109F /C0109F /C0109F /C0048/C0046/C0048/C0049 /C0109F/C0049/C0046/C0048 /C0109F Figure 6. External Component Connections (GQE)

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005 25POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 component connection (continued) (TOP VIEW) GQE package terminal diagram TESTM NOTE: NC − not connected B NCNCNC4NC4NC4 NCNC3NC3NC2NC2 NC1NC1NC2NC2NC2 NC1NC1NC1NC2NC NCNC1NCNC NC NC NC NC2 NC1 NC3 A B C D E F G H J 129 AGND SM PC2 DGND AVDD SE CPS DVDD /ISO PC1 PC0 AGND AVDD TPA− TPB+ AGND TPBIAS TPA+ TPB− AGND RESET FILTER0 FILTER1 PLLVDD PLLGND PLLGND AVDD XI XO DGND LREQ CNA DVDD 345678 C/LKON CTL0 PD LPS SYSCLK CTL1 Figure 7. Recommended Application Board Layout for GQE Package

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005

26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 component connection (continued) † See Figure 10, Figure 11, and Figure 12. ‡ See Figure 13 and Figure 14. § See Terminal Functions Table. ¶ See crystal selection section for more details AB CDE FG H J NC NC NC NC NC NC NC NC NC NC NC NC NC NC SYSCLK CTL0 CNA CTL1 PD LPS C/LKON PC0 DGND PC1 PC2 /ISO CPS DVDD TESTM SE SM AVDD AGND /RESET FILTER0 FILTER1 PLLVDD PLLGND PLLGND XI XO DGND DVDD LREQ AGND AVDD AGND AVDD AGND TPBIAS TPA+ TPA− TPB+ TPB− CNA OUT POWER DOWN 10 k Bus Manager LKON Power−Class Programming /ISO 400 k Cable Power 0.001 0.001 0.1 VDD 1 k (Optional) § 0.001 0.001 0.1 VDD VDD 6.34 k TP Cables Interface Connections † 0.1 0.1 VDD 0.0010.1 VDD 12 pF ¶ 12 pF ¶ 0.0010.0010.1 400 k 1 k/C0087 /C0109F/C0109F/C0109F /C0109F /C0109F /C0109F /C0109F/C0109F/C0109F /C0109F /C0109F /C0109F /C0109F /C0048/C0046/C0048/C0049 /C0109F/C0049/C0046/C0048 /C0109F Figure 8. External Component Connections (ZQE)

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005 27POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 component connection (continued) (TOP VIEW) TESTM NOTE: NC − not connected B NC3NC3NC2 NC1NC2NC2 NC1NC2 NC NC NC NC2 NC1 NC3 A B C D E F G H J 129 AGND SM PC2 DGND AVDD SE CPS DVDD /ISO PC1 PC0 AGND AVDD TPA− TPB+ AGND TPBIAS TPA+ TPB− AGND RESET FILTER0 FILTER1 PLLVDD PLLGND PLLGND AVDD XI XO DGND LREQ CNA DVDD 345678 C/LKON CTL0 PD LPS SYSCLK CTL1 Figure 9. Recommended Application Board Layout for ZQE Package

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005

28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 component connection (continued) Cable Port TPA+ TPA− TPB+ TPB− Cable Power Pair Cable Pair A Cable Pair B TPBIAS 1 µF 56 Ω‡56 Ω‡ 56 Ω‡56 Ω‡ 5 kΩ220 pF † CPS 400 kΩTSB41AB1 Outer Shield Termination † The IEEE Std 1394-1995 calls for a 250-pF capacitor, which is a nonstandard component value. A 220-pF capacitor is recommended. ‡ ±0.5% to meet 1394−1995 specification. Figure 10. TP Cable Connections Figure 11. Compliant DC Isolated Outer Shield Termination

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005

30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 crystal selection (continued) The following are some typical specifications for crystals used with the physical layers from TI in order to achieve the required frequency accuracy and stability: /C0068Crystal mode of operation: Fundamental /C0068Frequency tolerance at 25°C: Total frequency variation for the complete circuit is ±100 ppm. A crystal with ±30-ppm frequency tolerance is recommended for adequate margin. /C0068Frequency stability (over temperature and age): A crystal with ±30-ppm frequency stability is recommended for adequate margin. NOTE: The total frequency variation must be kept below ±100 ppm from nominal with some allowance for error introduced by board and device variations. Trade-offs between frequency tolerance and stability may be made as long as the total frequency variation is less than ±100 ppm. For example, the frequency tolerance of the crystal may be specified at 50 ppm and the temperature tolerance may be specified at 30 ppm to give a total of 80 ppm possible variation due to the crystal alone. Crystal aging also contributes to the frequency variation. /C0068Load capacitance: For parallel resonant mode crystal circuits, the frequency of oscillation is dependent upon the load capacitance specified for the crystal. Total load capacitance (CL) is a function not only of the discrete load capacitors, but also of the board layout and circuit. It may be necessary to select discrete load capacitors iteratively until the SYSCLK output is within specification. It is recommended that load capacitors with a maximum of ±5% tolerance be used. As an example, for the OHCI + 41AB1 evaluation module (EVM), which uses a crystal specified for 12 pF loading, load capacitors (C9 and C10 in Figure 15) of 16 pF each were appropriate for the layout of that particular board. The load specified for the crystal includes the load capacitors (C9, C10), the loading of the PHY terminals (C(PHY)), and the loading of the board itself (C(BD)). The value of C(PHY) is typically about 1 pF, and C(BD) is typically 0.8 pF per centimeter of board etch; a typical board can have 3 pF to 6 pF or more. The load capacitors C9 and C10 combine as capacitors in series so that the total load capacitance is: C L /C0043/C0426(C9 /C0032C10 )/C0324(C9 /C0041C10 )/C0427/C0041C (PHY) /C0041C (BD)

24.576 MHz X1 C (PHY) + C(BD)

Figure 15. Load Capacitance for the TSB41AB1 PHY

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005 31POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 crystal selection (continued) The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency, minimizing noise introduced into the PHYs phase-lock loop, and minimizing any emissions from the circuit. The crystal and two load capacitors should be considered as a unit during layout. The crystal and load capacitors should be placed as close as possible to one another while minimizing the loop area created by the combination of the three components. Varying the size of the capacitors may help in this. Minimizing the loop area minimizes the effect of the resonant current (Is) that flows in this resonant circuit. This layout unit (crystal and load capacitors) should then be placed as close as possible to the PHY XI and XO terminals to minimize trace lengths. Figure 16 depicts a layout that meets these guidelines. C9 C10 Figure 16. Recommended Crystal and Capacitor Layout and Specification of Crystals for Texas Instruments IEEE 1394 Physical Layers, TI literature number SLLA051. PowerPAD, which is an exposed metallic pad on the bottom of the device, is a thermal and electrical conductor. 64-terminal PAP PowerPAD package, and 5 mm × 5 mm for the 48-terminal PHP PowerPAD package. land may or may not contain numerous thermal vias depending on PCB construction.

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005

32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 designing with the PowerPad package (continued) Other requirements for thermal lands and thermal vias are detailed in the PowerPAD Thermally Enhanced http://www.ti.com. Figure 17. Example of a Thermal Land for the TSB41AB1PAP PHY For the TSB41AB1, this thermal land should be grounded to the low-impedance ground plane of the device. recommended that the device ground terminal landing pads be connected directly to the grounded thermal land. be soldered to the exposed PowerPAD using standard reflow soldering techniques. selected page is set in base register 7. Table 2. The base register field definitions are unaffected by the selected page number. but is subject to future usage. All registers in pages 2 through 6 are reserved. Table 1. Base Register Configuration

0000 Physical ID R CPS

0001 RHB IBR Gap_Count

0010 Extended (111b) Num_Ports (00001b)

0011 PHY_Speed (010b) Rsvd Delay (0000b)

0100 LCtrl C Jitter (000b) Pwr_Class

0101 RPIE ISBR CTOI CPSI STOI PEI EAA EMC

0110 Reserved

0111 Page_Select Rsvd Port_Select

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005 33POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 internal register configuration (continued) Table 2. Base Register Field Descriptions after a bus reset until self-ID has completed as indicated by an unsolicited register-0 status transfer. 1 during tree-ID if this node becomes root. has dropped below its threshold for reliable operation. is reset to 0 by hardware reset and is unaffected by bus reset. receive or transmit operation in progress when this bit is set completes before the bus reset is initiated. The IBR bit is reset to 0 by hardware reset or bus reset. Gap_Count 6 Rd/Wr Arbitration gap count. This value is used to set the subaction (fair) gap, arb-reset gap, and arb-delay times. PHY_Speed 3 Rd PHY speed capability. For the TSB41AB1 PHY this field is 010b, indicating S400 speed capability. as 144+(Delay*20) ns. For the TSB41AB1 this field is 0. LCtrl 1 Rd/Wr Link-active status control. This bit is used to control the active status of the LLC as indicated during self-ID. The logical AND of this bit and the LPS active status is replicated in the L field (bit 9) of the self-ID packet. The LLC is considered active only if the LPS input is active and the LCtrl bit is set. The LCtrl bit is set to 1 by hardware reset and is unaffected by bus reset. indicated on the LREQ input are processed, even if the LCtrl bit is cleared to 0. by the C/LKON input terminal upon hardware reset and is unaffected by bus reset. data delay, expressed as (Jitter+1)×20 ns. For the TSB41AB1 this field is 0. PC0–PC2 input terminals upon hardware reset and is unaffected by bus reset (see Table 9).

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005

34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Table 2. Base Register Field Descriptions (Continued) is reset to 0 by hardware reset and is unaffected by bus reset. bus reset at the next opportunity. This bit is reset to 0 by bus reset. NOTE: Legacy IEEE Std 1394-1995 compliant PHYs may not be capable of performing short bus resets. writing a 1 to this register bit. output to notify the LLC to service the interrupt. process to complete and then generate a state time-out interrupt and bus reset. indicating that cable power may be too low for reliable operation. This bit is reset to 1 by hardware reset. It can be cleared by writing a 1 to this register bit. output to notify the LLC to service the interrupt. LLC to service the interrupt. by hardware reset, or by writing a 1 to this register bit. activates the C/LKON output to notify the LLC to service the interrupt. isochronous traffic by excessively delaying the transmission of cycle-start packets. hardware reset and is unaffected by bus reset. Page_Select 3 Rd/Wr Page select. This field selects the register page to use when accessing register addresses 8 through 15. This field is reset to 0 by hardware reset and is unaffected by bus reset. reset to 0 by hardware reset and is unaffected by bus reset.

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005 35POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 internal register configuration (continued) The port status page provides access to configuration and status information for each of the ports. The port is selected by writing 0 to the Page_Select field and the desired port number to the Port_Select field in base register 7. The configuration of the port status page registers is shown in Table 3, and corresponding field descriptions are given in Table 4. If the selected port is unimplemented, all registers in the port status page are read as 0. Table 3. Page 0 (Port Status) Register Configuration

1000 Astat Bstat Ch Con Bias Dis

1001 Peer_Speed PIE Fault Reserved

1010 Reserved

1011 Reserved

1100 Reserved

1101 Reserved

1110 Reserved

1111 Reserved

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005

36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 internal register configuration (continued) Table 4. Page 0 (Port Status) Register Field Descriptions invalid after a bus reset until tree-ID has completed. reset to 0 by hardware reset and is unaffected by bus reset. Bias 1 Rd Debounced incoming cable bias status. A 1 indicates that the selected port is detecting incoming cable bias. The incoming cable bias must be stable for the debounce time of 52 µs for the bias bit to be set to 1. are enabled for normal operation following hardware reset). The dis bit is not affected by bus reset.

000 S100

001 S200

010 S400

The Peer_Speed field is invalid after a bus reset until self-ID has completed. TSB41AB1 is only capable of detecting peer speeds up to S400. bit and notifies the link. This bit is reset to 0 by hardware reset and is unaffected by bus reset. reset and is unaffected by bus reset.

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005 37POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 internal register configuration (continued) The vendor identification page is used to identify the vendor/manufacturer and compliance level. The page is selected by writing 1 to the Page_Select field in base register 7. The configuration of the vendor identification page is shown in Table 5, and corresponding field descriptions are given in Table 6. Table 5. Page 1 (Vendor ID) Register Configuration

1000 Compliance

1001 Reserved

1010 Vendor_ID[0]

1011 Vendor_ID[1]

1100 Vendor_ID[2]

1101 Product_ID[0]

1110 Product_ID[1]

1111 Product_ID[2]

Table 6. Page 1 (Vendor ID) Register Field Descriptions (Texas Instruments) (the MSB is at register address 1010b). and corresponding field descriptions are given in Table 8. Table 7. Page 7 (Vendor-Dependent) Register Configuration

1000 NPA Reserved Link_Speed

1001 Reserved for test

1010 Reserved for test

1011 Reserved for test

1100 Reserved for test

1101 Reserved for test

1110 SWR Reserved for test

1111 Reserved for test

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005

38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 internal register configuration (continued) Table 8. Page 7 (Vendor-Dependent) Register Field Descriptions of less than 8 bits. This bit is cleared to 0 by hardware reset and is unaffected by bus reset.

00 S100

01 S200

10 S400

value in this field. This field is set to 10b (S400) by hardware reset and is unaffected by bus reset. the RESET terminal low). This bit is always read as a 0. (bits 21–23) of the transmitted self-ID packet. Descriptions of the various power classes are given in Table 9. loaded into the Pwr_Class field in register 4. Table 9. Power Class Descriptions 000 Node does not need power and does not repeat power. 001 Node is self-powered and provides a minimum of 15 W to the bus. 010 Node is self-powered and provides a minimum of 30 W to the bus. 011 Node is self-powered and provides a minimum of 45 W to the bus. bus power that it provides can be found in the configuration ROM.

101 Reserved

110 Node is powered from the bus and uses up to 3 W. An additional 3 W is needed to enable the link. 111 Node is powered from the bus and uses up to 3 W. An additional 7 W is needed to enable the link.

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005 39POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 using the TSB41AB1 with a non-IEEE 1394a-2000 link layer The TSB41AB1 implements the PHY-LLC interface specified in IEEE 1394a-2000. This interface is based upon the interface described in informative Annex J of IEEE Std 1394-1995, which is the interface used in older TI PHY devices. The PHY-LLC interface specified in IEEE 1394a-2000 is completely compatible with the older Annex J interface. IEEE 1394a-2000 includes enhancements to the Annex J interface that must be comprehended when using the TSB41AB1 with a non-IEEE 1394a-2000 LLC device. /C0068A new LLC service request was added which allows the LLC to enable and disable asynchronous arbitration accelerations temporarily. If the LLC does not implement this new service request, the arbitration enhancements should not be enabled (see the EAA bit in PHY register 5). /C0068The capability to perform multispeed concatenation (the concatenation of packets of differing speeds) was added in order to improve bus efficiency (primarily during isochronous transmission). If the LLC does not support multispeed concatenation, multispeed concatenation should not be enabled in the PHY (see the EMC bit in PHY register 5). /C0068In order to accommodate the higher transmission speeds expected in future revisions of the standard, IEEE 1394a-2000 extended the speed code in bus requests from 2 bits to 3 bits, increasing the length of the bus request from 7 bits to 8 bits. The new speed codes were carefully selected so that new IEEE 1394a-2000 PHY and LLC devices would be compatible, for speeds from S100 to S400, with legacy PHY and LLC devices that use the 2-bit speed codes. The TSB41AB1 correctly interprets both 7-bit bus requests (with 2-bit speed codes) and 8-bit bus requests (with 3-bit speed codes). Moreover, if a 7-bit bus request is immediately followed by another request (for example, a register read or write request), the TSB41AB1 correctly interprets both requests. Although the TSB41AB1 correctly interprets 8-bit bus requests, a request with a speed code exceeding S400 results in the TSB41AB1 transmitting a null packet (data-prefix followed by data-end, with no data in the packet). More explanation is included in the TI application note IEEE 1394a Features Supported by TI TSB41LV0X Physical Layer Devices, TI literature number SLLA019. using the TSB41AB1 with a lower-speed link layer Although the TSB41AB1 is an S400 capable PHY, it may be used with lower speed LLCs, such as the S200 capable TSB12LV31. In such a case, the LLC has fewer data terminals than the PHY, and some Dn terminals on the TSB41AB1 remain unused. Unused Dn terminals should be pulled to ground through 10-kΩ resistors. The TSB41AB1 transfers all received packet data to the LLC, even if the speed of the packet exceeds the capability of the LLC to accept it. Some lower speed LLC designs do not properly ignore packet data in such cases. On the rare occasions that the first 16 bits of partial data accepted by such an LLC match the bus ID and node ID for that node, spurious header CRC or tcode errors may result. During bus initialization following a bus reset, each PHY transmits a self-ID packet that indicates, among other information, the speed capability of the PHY. The bus manager (if one exists) builds a speed map from the collected self-ID packets. This speed map gives the highest possible speed that can be used on the node-to-node communication paths between every pair of nodes in the network.

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005

40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 using the TSB41AB1 with a lower-speed link layer (continued) In the case of a node consisting of a higher-speed PHY and a lower-speed LLC, the speed capability of the node (PHY and LLC in combination) is that of the lower-speed LLC. A sophisticated bus manager may be able to determine the LLC speed capability by reading the configuration ROM Bus_Info_Block, or by sending asynchronous request packets at different speeds to the node and checking for an acknowledge; the speed map may then be adjusted accordingly. The speed map should reflect that communication to such a node must be done at the lower speed of the LLC, instead of the higher speed of the PHY. However, speed-map entries for paths that merely pass through the node PHY, but do not terminate at that node, should not be restricted by the lower speed of the LLC. To assist in building an accurate speed map, the TSB41AB1 can indicate a speed capability other than S400 in its transmitted self-ID packet. This is controlled by the Link_Speed field in register 8 of the vendor-dependent page (page 7). Setting the Link_Speed field affects only the speed indicated in the self-ID packet; it has no effect on the speed signaled to peer PHYs during self-ID. The TSB41AB1 identifies itself as S400 capable to its peers regardless of the value in the Link_Speed field. Generally, the Link_Speed field should not be changed from its power-on default value of S400 unless it is determined that the speed map (if one exists) is incorrect for path entries terminating in the local node. If the speed map is incorrect, it can be assumed that the bus manager has used only the self-ID packet information to build the speed map. In this case, the node may update the Link_Speed field to reflect the lower speed capability of the LLC and then initiate another bus reset to cause the speed map to be rebuilt. Note that in this scenario any speed-map entries for node-to-node communication paths that pass through the local node’s PHY are restricted by the lower speed. In the case of a leaf node (which has only one active port) the Link_Speed field may be set to indicate the speed of the LLC without first checking the speed map. Changing the Link_Speed field in a leaf node can only affect those paths that terminate at that node. Because no other paths can pass through a leaf node, it can have no effect on other paths in the speed map. For hardware configurations, which can only be a leaf node (all ports but one are unimplemented), it is recommended that the Link_Speed field be updated immediately after power on or hardware reset. power-up reset To ensure proper operation of the TSB41AB1, the RESET terminal must be asserted low for a minimum of 2 ms from the time that PHY power reaches the minimum required supply voltage. When using a passive capacitor on the RESET terminal to generate a power-on reset signal, the minimum reset time is assured if the capacitor has a minimum value of 0.1 µF and also satisfies the following equation: C min /C00430.0077/C0032T /C00410.085 where Cmin is the minimum capacitance on the RESET terminal in µF, and T is the VDD ramp time, 10%–90%, in milliseconds. bus reset In the TSB41AB1, the initiate bus reset (IBR) bit may be set to 1 in order to initiate a bus reset and initialization sequence. The IBR bit is located in PHY register 1, along with the root-holdoff bit (RHB) and gap-count register, as required by IEEE 1394a-2000 (this configuration also maintains compatibility with older TI PHY designs which were based upon the suggested register set defined in Annex J of IEEE Std 1394-1995). Therefore, whenever the IBR bit is written, the RHB and gap count are also necessarily written. (2)

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005 41POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 bus reset (continued) The RHB and gap count may also be updated by PHY-config packets. The TSB41AB1 is IEEE 1394a-2000 compliant, and therefore both the reception and transmission of PHY-config packets cause the RHB and gap count to be loaded, unlike older IEEE Std 1394-1995 compliant PHYs which decode only received PHY-config packets. The gap count is set to the maximum value of 63 after two consecutive bus resets without an intervening write to the gap count, either by a write to PHY register 1 or by a PHY-config packet. This mechanism allows a PHY-config packet to be transmitted and then a bus reset initiated to verify that all nodes on the bus have updated their RHBs and gap-count values, without having the gap count set back to 63 by the bus reset. The subsequent connection of a new node to the bus, which initiates a bus reset, then causes the gap count of each node to be set to 63. Note, however, that if a subsequent bus reset is instead initiated by a write to register 1 to set the IBR bit, all other nodes on the bus have their gap-count values set to 63, while the gap count of this node remains set to the value just loaded by the write to PHY register 1. Therefore, in order to maintain consistent gap counts throughout the bus, the following rules apply to the use of the IBR bit, RHB, and gap count in PHY register 1: /C0068Following the transmission of a PHY-config packet, a bus reset must be initiated in order to verify that all nodes have correctly updated their RHBs and gap-count values, and to ensure that a subsequent new connection to the bus causes the gap count to be set to 63 on all nodes in the bus. If this bus reset is initiated by setting the IBR bit to 1, the RHB and gap-count register must also be loaded with the correct values consistent with the just transmitted PHY-config packet. In the TSB41AB1, the RHB and gap count have been updated to their correct values upon the transmission of the PHY-config packet, and so these values may first be read from register 1 and then rewritten. /C0068Other than to initiate the bus reset which must follow the transmission of a PHY-config packet, whenever the IBR bit is set to 1 in order to initiate a bus reset, the gap-count value must also be set to 63 to be consistent with other nodes on the bus, and the RHB should be maintained with its current value. /C0068The PHY register 1 should not be written to except to set the IBR bit. The RHB and gap count should not be written without also setting the IBR bit to 1.

42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

the operation of the PHY-LLC interface. terminals on the TSB41AB1, as shown in Figure 18. Figure 18. PHY-LLC Interface and sampled on, the rising edge of SYSCLK. between the TSB41AB1 and LLC. operations. When the LLC is in control of the D0–D7 bus, unused Dn terminals are ignored by the TSB41AB1. to the serial bus for packet transmission, read or write PHY registers, or control arbitration acceleration. indicates the power status of the LLC, and may be used to reset the PHY-LLC interface or to disable SYSCLK. either when LPS is inactive or when the PHY register LCtrl bit is zero. terminal is used to enable the output differentiation logic on the CTL0, CTL1 and D0–D7 terminals. these buses only after the LLC has been granted permission to do so by the PHY. to gain control of the serial bus in order to transmit a packet, or to control arbitration acceleration.

The PHY initiates a receive operation whenever a packet is received from the serial bus. The PHY initiates a transmit operation after winning control of the serial bus following a bus request by the LLC. The transmit operation is initiated when the PHY grants control of the interface to the LLC. The encoding of the CTL0−CTL1 bus is shown in Table 10 and Table 11. Table 10. CTL Encoding When PHY Has Control of the Bus 0 1 Status Status information is being sent from the PHY to the LLC. 1 0 Receive An incoming packet is being sent from the PHY to the LLC. 1 1 Grant The LLC has been given control of the bus to send an outgoing packet. Table 11. CTL Encoding When LLC Has Control of the Bus 0 0 Idle The LLC releases the bus (transmission has been completed). is to be transmitted (concatenated) without arbitrating. 1 0 Transmit An outgoing packet is being sent from the LLC to the PHY. voltage level between the hysteresis thresholds of the input buffer so that the previous logic state is maintained. The correspondence between the output logic state and the output signal level is shown in Figure 19. Figure 19. Signal Transformation for Digital Differentiation

44 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

differentiation circuitry on its LREQ terminal. Figure 20. Input/Output Differentiation Logic a serial bit stream on the LREQ terminal as shown in Figure 21. NOTE: Each cell represents one clock sample time, and n is the number of bits in the request stream. Figure 21. LREQ Request Stream The length of the stream varies depending on the type of request as shown in Table 12. Table 12. Request Stream Bit Length

the request. In the descriptions below, bit 0 is the most significant and is transmitted first in the request bit stream. The LREQ terminal is normally low. Encoding for the request type is shown in Table 13. Table 13. Request Type Encoding 000 ImmReq Immediate bus request. Upon detection of idle, the PHY takes control of the bus immediately without arbitration. 001 IsoReq Isochronous bus request. Upon detection of idle, the PHY arbitrates for the bus without waiting for a subaction gap. 010 PriReq Priority bus request. The PHY arbitrates for the bus after a subaction gap, ignores the fair protocol. 011 FairReq Fair bus request. The PHY arbitrates for the bus after a subaction gap, follows the fair protocol. 100 RdReg The PHY returns the specified register contents through a status transfer.

101 WrReg Write to the specified register

110 AccelCtl Enable or disable asynchronous arbitration acceleration

111 Reserved Reserved

For a bus request the length of the LREQ bit stream is 7 or 8 bits as shown in Table 14. Table 14. Bus Request 0 Start bit Indicates the beginning of the transfer (always 1). 1−3 Request type Indicates the type of bus request. See Table 13. 4−6 Request speed Indicates the speed at which the PHY sends the data for this request. See Table 15 for the encoding of this field. 7 Stop bit Indicates the end of the transfer (always 0). If bit 6 is 0, this bit may be omitted. The 3-bit request speed field used in bus requests is shown in Table 15. Table 15. Bus Request

010 S200

100 S400

46 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

For a read register request, the length of the LREQ bit stream is 9 bits as shown in Table 16. Table 16. Read Register Request

0 Start bit Indicates the beginning of the transfer (always 1)

8 Stop bit Indicates the end of the transfer (always 0)

For a write register request, the length of the LREQ bit stream is 17 bits as shown in Table 17. Table 17. Write Register Request For an acceleration control request, the length of the LREQ bit stream is 6 bits as shown in Table 18. Table 18. Acceleration Control Request 4 Control Asynchronous period arbitration acceleration is enabled if 1, and disabled if 0.

5 Stop bit Indicates the end of the transfer (always 0)

an isochronous request only when the serial bus has been won. to send another type of packet. After the interface is released the LLC may proceed with another request.

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005 47POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 PRINCIPLES OF OPERATION LLC service request (continued) The LLC may make only one bus request at a time. Once the LLC issues any request for bus access (ImmReq, IsoReq, FairReq, or PriReq), it cannot issue another bus request until the PHY indicates that the bus request was lost (bus arbitration lost and another packet received), or won (bus arbitration won and the LLC granted control). The PHY ignores new bus requests while a previous bus request is pending. All bus requests are cleared upon a bus reset. For write register requests, the PHY loads the specified data into the addressed register as soon as the request transfer is complete. For read register requests, the PHY returns the contents of the addressed register to the LLC at the next opportunity through a status transfer. If a received packet interrupts the status transfer, then the PHY continues to attempt the transfer of the requested register until it is successful. A write or read register request may be made at any time, including while a bus request is pending. Once a read register request is made, the PHY ignores further read register requests until the register contents are successfully transferred to the LLC. A bus reset does not clear a pending read register request. The TSB41AB1 includes several arbitration acceleration enhancements, which allow the PHY to improve bus performance and throughput by reducing the number and length of interpacket gaps. These enhancements include autonomous (fly-by) isochronous packet concatenation, autonomous fair and priority packet concatenation onto acknowledge packets, and accelerated fair and priority request arbitration following acknowledge packets. The enhancements are enabled when the EAA bit in PHY register 5 is set. The arbitration acceleration enhancements may interfere with the ability of the cycle master node to transmit the cycle start message under certain circumstances. The acceleration control request is therefore provided to allow the LLC to temporarily enable or disable the arbitration acceleration enhancements of the TSB41AB1 during the asynchronous period. The LLC typically disables the enhancements when its internal cycle counter rolls over indicating that a cycle start message is imminent, and then reenables the enhancements when it receives a cycle start message. The acceleration control request may be made at any time, however, and is immediately serviced by the PHY. Additionally, a bus reset or isochronous bus request causes the enhancements to be reenabled, if the EAA bit is set. status transfer A status transfer is initiated by the PHY when there is status information to be transferred to the LLC. The PHY waits until the interface is idle before starting the transfer. The transfer is initiated by the PHY asserting status (01b) on the CTL terminals, along with the first two bits of status information on the D0 and D1 terminals. The PHY maintains CTL = status for the duration of the status transfer. The PHY may prematurely end a status transfer by asserting something other than status on the CTL terminals. This occurs if a packet is received before the status transfer completes. The PHY continues to attempt to complete the transfer until all status information has been successfully transmitted. There is at least one idle cycle between consecutive status transfers. The PHY normally sends just the first four bits of status to the LLC. These bits are status flags that are needed by the LLC state machines. The PHY sends an entire 16-bit status packet to the LLC after a read register request, or when the PHY has pertinent information to send to the LLC or transaction layers. The only defined condition where the PHY automatically sends a register to the LLC is after self-ID, where the PHY sends the physical-ID register that contains the new node address. All status transfers are either 4 or 16 bits unless interrupted by a received packet. The status flags are considered to have been successfully transmitted to the LLC immediately upon being sent, even if a received packet subsequently interrupts the status transfer. Register contents are considered to have been successfully transmitted only when all 8 bits of the register have been sent. A status transfer is retried after being interrupted only if any status flags remain to be sent, or if a register transfer has not yet completed. The definitions of the bits in the status transfer are shown in Table 19, and the timing is shown in Figure 22.

48 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Table 19. Status Bits in IEEE Std 1394-1995). This bit is used by the LLC in the busy/retry state machine. Std 1394-1995). This bit is used by the LLC to detect the completion of an isochronous cycle. 2 Bus reset Indicates that the PHY has entered the bus reset start state. cable-power voltage falling too low, a state time-out, or a port status change. 4−7 Address This field holds the address of the PHY register whose contents are being transferred to the LLC. 8−15 Data This field holds the register contents. Figure 22. Status Transfer Timing

1. Status transfer initiated. The PHY indicates a status transfer by asserting status on the CTL lines along with

data is to be sent in addition to any status information.

1. Status transfer terminated. The PHY normally terminates a status transfer by asserting idle on the CTL lines.

a receive operation. The PHY asserts at least one cycle of idle between consecutive status transfers. in the calculation of CRC or any other data protection mechanisms.

Table 20. Receive Speed Codes

0100 XXXX S200

NOTE: X = Output as 0 by PHY, ignored by LLC. Y = Output as 1 by PHY, ignored by LLC. reception timing diagram for normal packets, and Figure 24 is the reception timing diagram for null packets. Figure 23. Normal Packet Reception Timing

1. Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines.
2. Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more cycles
3. Speed code. The PHY indicates the speed of the received packet by asserting a speed code on the D lines

that which the link is capable of handling, the link should ignore the subsequent data.

1. Receive data. Following the data-on indication (if any) and the speed code, the PHY asserts packet data

on the D lines with receive on the CTL lines for the remainder of the receive operation.

1. Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines.

The PHY asserts at least one cycle of idle following a receive operation.

50 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Figure 24. Null Packet Reception Timing

1. Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines.
2. Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more cycles.
3. Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines.

The PHY asserts at least one cycle of idle following a receive operation. When the LLC issues a bus request through the LREQ terminal, the PHY arbitrates to gain control of the bus. not assert hold before transmit). The PHY asserts data-prefix on the serial bus during this time. high-impedance. The PHY then regains control of the interface bus. a single bus ownership must be of the same speed (since the speed of the packet is set before the first packet). packet data as given in Table 20.

transmission timing diagram for cancelled or null packets. Figure 25. Normal Packet Transmission Timing

1. Transmit operation initiated. The PHY asserts grant on the CTL lines followed by idle to hand over control

(that is, it places its CTL and D outputs in a high-impedance state) following the idle cycle.

1. Optional idle cycle. The link may assert at most one idle cycle preceding assertion of either hold or transmit.

This idle cycle is optional; the link is not required to assert idle preceding either hold or transmit.

1. Optional hold cycles. The link may assert hold for up to 47 cycles preceding assertion of transmit. These

hold cycle(s) are optional; the link is not required to assert hold preceding transmit.

1. Transmit data. When data is ready to be transmitted, the link asserts transmit on the CTL lines along with
2. Transmit operation terminated. The transmit operation is terminated by the link asserting hold or idle on the

or idle before releasing the interface and returning control to the PHY.

1. Concatenated packet speed code. If multispeed concatenation is enabled in the PHY, the link asserts a

link may not concatenate an S100 packet onto any higher-speed packet.

1. After regaining control of the interface, the PHY shall assert at least one cycle of idle before any subsequent

status transfer, receive operation, or transmit operation.

52 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Figure 26. Cancelled/Null Packet Transmission Timing

1. Transmit operation initiated. PHY asserts grant on the CTL lines followed by idle to hand over control of the
2. Optional idle cycle. The link may assert at most one idle cycle preceding assertion of hold. This idle cycle

is optional; the link is not required to assert idle preceding hold.

1. Optional hold cycles. The link may assert hold for up to 47 cycles preceding assertion of idle. These hold

cycle(s) are optional; the link is not required to assert hold preceding idle.

1. Null transmit termination. The null transmit operation is terminated by the link asserting two cycles of idle
2. After regaining control of the interface, the PHY asserts at least one idle cycle before any subsequent status

transfer, receive operation, or transmit operation. of the interface to normal operation.

Table 21. LPS Timing Parameters operates correctly with the TSB41AB1). isolation barrier on the LPS signal (for example, as shown in Figure 14). on the LREQ signal. The timing for interface reset is shown in Figure 27 and Figure 28. Figure 27. Interface Reset, ISO Low

54 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1. Normal operation. Interface is operating normally, with LPS active, SYSCLK active, status and packet data

reception and transmission via the CTL and D lines, and request activity via the LREQ line.

1. LPS deasserted. The LLC deasserts the LPS signal and, within 1 µs, terminates any request or interface

terminate any output signal activity such that signals end in a logic 0 state). signal activity such that signals end in a logic 0 state). The PHY-LLC interface is now in the reset state.

1. Interface restored. After the minimum TRESTORE time, the LLC may again assert LPS active. The minimum

circuits to stabilize and reach a quiescent state if the isolation barrier has somehow become unbalanced. When LPS is asserted, the interface is initialized. Figure 28. Interface Reset, ISO High

56 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1. Normal operation. Interface is operating normally, with LPS active, SYSCLK active, status and packet data

reception and transmission via the CTL and D lines, and request activity via the LREQ line.

1. LPS deasserted. The LLC deasserts the LPS signal and, within 1 µs, terminates any request or interface

terminate any output signal activity such that signals end in a logic 0 state). signal activity such that signals end in a logic 0 state). The PHY-LLC interface is now in the reset state.

1. Interface disabled. If the LPS signal remains inactive for TLPS_DISABLE time, the PHY terminates SYSCLK

Figure 30. Interface Disable, ISO High

1. Normal operation. Interface is operating normally, with LPS active, SYSCLK active, status and packet data

reception and transmission via the CTL and D lines, and request activity via the LREQ line.

1. LPS deasserted. The LLC deasserts the LPS signal and, within 1 µs, terminates any request or interface

bus activity, places its CTL and D outputs into a high-impedance state, and drives its LREQ output low.

1. Interface reset. After TLPS_RESET time, the PHY determines that LPS is inactive, terminates any interface

bus activity, and drives its CTL and D outputs low. The PHY-LLC interface is now in the reset state.

1. Interface disabled. If the LPS signal remains inactive for TLPS_DISABLE time, the PHY terminates SYSCLK

activity by driving the SYSCLK output low. The PHY-LLC interface is now in the disabled state.

7 Cycles

Figure 31. Interface Initialization, ISO Low

58 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1. LPS reasserted. After the interface has been in the reset or disabled state for at least the minimum

the interface is merely reset but not yet disabled.

1. SYSCLK activated. If the interface is disabled, the PHY reactivates its SYSCLK output when it detects that

output is a 50% duty cycle square wave with a frequency of 49.152 MHz ±100 ppm (period of 20.345 ns). is shown in Figure 31 as occurring in the first SYSCLK cycle).

1. Receive indicated. Upon the eighth SYSCLK cycle following reassertion of LPS, the PHY asserts the

high-impedance state after the first cycle).

1. Initialization complete. The PHY asserts the idle state on the CTL lines and logic 0 on the D lines. This

PHY now accepts requests from the LLC via the LREQ line. Figure 32. Interface Initialization, ISO High

/C0084/C0083/C0066/C0052/C0049/C0065/C0066/C0049 /C0073/C0069/C0069/C0069 /C0049/C0051/C0057/C0052/C0097/C0262/C0050/C0048/C0048/C0048 /C0079/C0078/C0069/C0262/C0080/C0079/C0082/C0084 /C0067/C0065/C0066/C0076/C0069 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0047/C0065/C0082/C0066/C0073/C0084/C0069/C0082 SLLS423I − JUNE 2000 − REVISED MARCH 2005 59POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 PRINCIPLES OF OPERATION interface reset and disable (continued) The sequence of events for initialization of the PHY-LLC interface when the interface is in the nondifferentiated mode of operation (ISO terminal is high) is as follows: 1. LPS reasserted. After the interface has been in the reset or disabled state for at least the minimum TRESTORE time, the LLC causes the interface to be initialized and restored to normal operation by reasserting the LPS signal. (In Figure 32, the interface is shown in the disabled state with SYSCLK low inactive. However, the interface initialization sequence described here is also executed if the interface is merely reset but not yet disabled.) 2. SYSCLK activated. If the interface is disabled, the PHY reactivates its SYSCLK output when it detects that LPS has been reasserted. If the PHY has entered a low-power state, it takes between 5.3 ms to 7.3 ms for SYSCLK to be restored; if the PHY is not in a low-power state, SYSCLK is restored within 60 ns. The SYSCLK output is a 50% duty cycle square wave with a frequency of 49.152 MHz ±100 ppm (period of 20.345 ns). During the first seven cycles of SYSCLK, the PHY continues to drive the CTL and D terminals low. The LLC is also required to drive its CTL and D outputs low for one of the first six cycles of SYSCLK but otherwise to place its CTL and D outputs in a high-impedance state. The LLC continues to drive its LREQ output low during this time. 3. Receive indicated. Upon the eighth SYSCLK cycle following reassertion of LPS, the PHY asserts the receive state on the CTL lines and the data-on indication (all ones) on the D lines for one or more cycles. 4. Initialization complete. The PHY asserts the idle state on the CTL lines and logic 0 on the D lines. This indicates that the PHY-LLC interface initialization is complete and normal operation may commence. The PHY now accepts requests from the LLC via the LREQ line.

www.ti.com 21-May-2019 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TSB41AB1GQE LIFEBUY BGA MICROSTAR JUNIOR GQE 80 360 TBD SNPB Level-2A-235C-4 WKS 0 to 70 TSB41AB1 TSB41AB1PAP ACTIVE HTQFP PAP 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 0 to 70 TSB41AB1 TSB41AB1PHP ACTIVE HTQFP PHP 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 0 to 70 TSB41AB1 TSB41AB1PHPG4 ACTIVE HTQFP PHP 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 0 to 70 TSB41AB1 TSB41AB1ZQE-64 LIFEBUY BGA MICROSTAR JUNIOR ZQE 64 360 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR 0 to 70 TSB41AB1S TSB41AB1ZQER-64 LIFEBUY BGA MICROSTAR JUNIOR ZQE 64 2000 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR TSB41AB1S (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

www.ti.com 21-May-2019 Addendum-Page 2 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TSB41AB1ZQER-64 BGA MI CROSTA R JUNI OR PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2019 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TSB41AB1ZQER-64 BGA MICROSTAR JUNIOR ZQE 64 2000 350.0 350.0 43.0 PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2019 Pack Materials-Page 2

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