TSB12LV26 TI | Alldatasheet
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3.3-V and 5-V PCI bus signaling PCI burst transfers and deep FIFOs to 3.3-V supply (core voltage is internally tolerate large host latency regulated to 1.8 Two general-purpose I/Os Serial bus data rates of 100M bits/s, 200M bits/s, and 400M bits/s Fabricated in advanced low-power CMOS process Physical write posting of up to three outstanding transactions Packaged in 100-terminal LQFP (PZT) Serial ROM interface supports 2-wire devices PCI_CLKRUN protocol The Texas Instruments TSB12LV26 device is a PCI-to-1394 host controller compliant with the PCI Local Bus Specification PCI Bus Power Management Interface Specification IEEE Std 1394-1995, and 1394 Open Host Controller Interface Specification The chip provides the IEEE 1394 link function and is compatible with 100M bits/s, 200M bits/s, and 400M bits/s serial bus data rates. As required by the 1394 Open Host Controller Interface Specification (OHCI) and IEEE Std 1394a-2000, internal control registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through configuration cycles specified by PCI and provides plug-and-play (PnP) compatibility. Furthermore, the TSB12LV26 device is compliant with the PCI Bus Power Management Interface Specification per the PC Design Guide requirements. TSB12LV26 device supports the D0, D2, and power states. The TSB12LV26 design provides PCI bus master bursting and is capable of transferring a cacheline of data at 132M bytes/s after connection to the memory controller. Since PCI latency can be large, deep FIFOs are provided to buffer 1394 data. The TSB12LV26 device provides physical write posting buffers and a highly-tuned physical data path for SBP-2 performance. The TSB12LV26 device also provides multiple isochronous contexts, multiple cacheline burst transfers, advanced internal arbitration, and bus-holding buffers on the PHY/link interface. An advanced CMOS process achieves low power consumption and allows the TSB12LV26 device to operate at PCI clock rates up to MHz. NOTE: This product is for high-volume PC
applications
only. For a complete datasheet or more information contact support@ti.com. Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. OHCI-Lynx is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright 2006, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TSB12LV26PZT Active Production TQFP (PZT) | 100 90 | JEDEC TRAY (10+1) Yes NIPDAU Level-4-260C-72 HR 0 to 70 TSB12LV26 F731652A TSB12LV26PZT.A Active Production TQFP (PZT) | 100 90 | JEDEC TRAY (10+1) Yes NIPDAU Level-4-260C-72 HR 0 to 70 TSB12LV26 F731652A (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TSB12LV26 : Addendum-Page 1
www.ti.com 23-May-2025
- Enhanced Product : TSB12LV26-EP NOTE: Qualified Version Definitions:
- Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TRAY L - Outer tray length without tabs KO - Outer tray height W - Outer tray width P1 - Tray unit pocket pitch CW - Measurement for tray edge (Y direction) to corner pocket center CL - Measurement for tray edge (X direction) to corner pocket center Text Chamfer on Tray corner indicates Pin 1 orientation of packed units. *All dimensions are nominal Device Package Name Package Type Pins SPQ Unit array matrix Max temperature (°C) L (mm) W (mm) (µm) (mm) CL (mm) CW (mm) TSB12LV26PZT PZT TQFP 100 90 6 X 15 150 315 135.9 7620 15.4 20.3 21 TSB12LV26PZT.A PZT TQFP 100 90 6 X 15 150 315 135.9 7620 15.4 20.3 21 Pack Materials-Page 1
MTQF012B – OCTOBER 1994 – REVISED DECEMBER 1996 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PZT (S-PQFP-G100) PLASTIC QUAD FLATPACK 4073179/B 11/96 0,13 NOM 0,75 0,45 0,25 0,05 MIN Seating Plane Gage Plane 0,27 0,17 100 SQ SQ 15,80 16,20 14,20 13,80 12,00 TYP 1,20 MAX 1,05 0,95 0,50 M0,08 0,08 0°–7° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026
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