TSB11LV01

TSB11LV01 TI | Alldatasheet

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3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER SLLS232B – MARCH 1996 – REVISED MAY 1997 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Supports Provisions of IEEE 1394-1995 Standard for High Performance Serial Bus† /C0068Fully Interoperable With FireWire Implementation of IEEE 1394-1995 /C0068Provides A Single Fully-Compliant Cable Port at 100 Megabits per Second (Mbits/s) /C0068Cable Port Monitors Line Conditions for Active Connection to a Remote Node /C0068Inactive Port Disabled to Save Power /C0068Cable Inactivity Monitor Output and Power-down Input Provided for Additional Sleep-Mode Power Savings /C0068Internal Bandgap Reference Provided for Setting Stable Operating Bias Conditions /C0068Logic Performs System Initialization and Arbitration Functions /C0068Encode and Decode Functions Included for Data-Strobe Bit-Level Encoding /C0068Incoming Data Resynchronized to Local Clock /C0068Data Interface to Link Layer Controller (Link) Provided Through Two Parallel Signal Lines at 50 Mbits/s /C006825-MHz Crystal Oscillator and PLL Provide Transmit, Receive Data, and Link Layer Controller Clocks at 50 MHz /C0068Digital I/Os are 5 V tolerant /C0068Node Power Class Information Signaling for System Power Management /C0068Cable Power Presence Monitoring /C0068Cable Bias and Driver Termination Voltage Supply /C0068Single 3-V Supply Operation /C0068Separate Multiple Package Terminals Provided for Analog and Digital Supplies and Grounds /C0068High Performance 48-Pin TQFP (PT) Package

description

The TSB11LV01 provides the analog transceiver functions needed to implement a single port node in a cable based IEEE 1394-1995 network. The cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB11LV01 is designed to interface with a link layer controller, such as the TSB12C01A. The TSB11LV01 requires an external 24.576-MHz crystal, which drives an internal phase-locked loop (PLL) generating the required 98.304-MHz reference signal. The 98.304-MHz reference signal is internally divided to provide the 49.152-MHz ±100 ppm system clock signals that control transmission of the outbound encoded strobe and data information. The 49.152-MHz clock signal is also supplied to the associated link for synchronization of the two chips and is used for resynchronization of the received data. The power-down function, when enabled by asserting the PWRDN terminal high, stops operation of the PLL. Data bits to be transmitted are received from the link on two parallel paths and are latched internally in the TSB11LV01 in synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded, and transmitted at 98.304-Mbits/s as the outbound data-strobe information stream. During transmit, the encoded data information is transmitted differentially on the TPB cable pair, and the encoded strobe information is transmitted differentially on the TPA cable pair. NOTE In this document, phy is the physical layer and link is the link layer controller. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  1997, Texas Instruments Incorporated † Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thomson, Limited. FireWire is a trademark of Apple Computer, Incorporated.

3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER SLLS232B – MARCH 1996 – REVISED MAY 1997

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TPA– TPB+ TPB– CPS AV CC AV CC AGND AGND TPBIAS CNA LPS C/LKON PC0 PC1 PC2 LREQ CTL0 CTL1 SYSCLK 17 18 19 20 PLLGND PLLGND XI 47 46 45 44 4348 42 TESTM1 TESTM2 RESET AGND AGND DGND DGND DGND DGND AGND 40 39 3841 21 22 23 24 XO PWRDN PLLFLT DGND PT PACKAGE (TOP VIEW) CCDV CCDV CCAV CCPLLV CCAV CCDVBIAS– 5 V

3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER SLLS232B – MARCH 1996 – REVISED MAY 1997 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description (continued) During packet reception the TPA and TPB transmitters of the cable port are disabled, and the receivers of the port are enabled. The encoded data information is received on the TPA cable pair, and the encoded strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The serial data bits are split into two parallel streams, resynchronized to the local system clock and sent to the associated link. Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the arbitration status. In addition, the TPB channel monitors the incoming cable common-mode voltage for the presence of the remotely supplied twisted-pair bias voltage. The presence or absence of this bias voltage is an indication of cable connection status. The cable connection status signal is internally debounced in the TSB11LV01. The debounced cable connection status signal initiates a bus reset. On a cable disconnect-to-connect, the debounce delay is 335 ms. On a connect-to-disconnect there is minimal debounce. The TSB11LV01 provides a 1.86-V nominal bias voltage for driver load termination. This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. The value of this bias voltage has been chosen to allow interoperation between transceiver chips operating from either 5-V nominal supplies or 3-V nominal supplies. This bias voltage source should be stabilized by using an external filter capacitor of at least 1 µF. The transmitter circuitry is disabled under the following conditions: powerdown, cable not active, reset, or transmitter disable. The receiver circuitry is disabled during powerdown, cable not active, or receiver disable. The twisted-pair bias voltage circuitry is disabled during the powerdown or reset conditions. The power-down condition occurs when the PWRDN input is asserted high. The cable-not-active condition occurs

3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER SLLS232B – MARCH 1996 – REVISED MAY 1997

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description (continued) when the cable connection status indicates no cable is connected and is not debounced. The device reset condition occurs when the RESET input terminal is asserted low. The transmitter disable and receiver disable conditions are determined from the internal logic. The line drivers in the TSB11LV01 operate in the high-impedance current mode and are designed to work with external 112-Ω line matching resistor networks. One network is provided at each end of each twisted-pair cable. Each network is composed of a pair of series-connected 56-Ω resistors. The midpoint of the pair of resistors that are directly connected to the twisted-pair A-package terminals is connected to the TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly connected to the twisted-pair B-package terminals is coupled to ground through a parallel resistance-capacitance (R-C) network with the recommended value of 5 kΩ and 250 pF. The values of the external resistors are designed to meet the IEEE 1394-1995 standard specifications when connected in parallel with the internal receiver circuits (see Figure 3). An internal reference circuit (bandgap) provides stable bias voltages for the TSB11LV01 transceiver circuits. The driver output current, along with other internal operating currents, is set by an external resistor. This resistor is connected between terminals R1 and R0, and has a value of 6 kΩ ±0.5%. Two of the package terminals set up various test conditions used in manufacturing. These terminals, TESTM1 and TESTM2, should be connected to V CC for normal operation. Four package terminals are inputs to set four configuration status bits in the self-identification (Self-ID) packet. These terminals are hardwired high or low as a function of the equipment design. PC0, PC1, and PC2 (corresponds to bits 21, 22, and 23 of the Self-ID packet) are three terminals that indicate either the need for power from the cable or the ability to supply power to the cable. The fourth terminal, C/LKON (corresponds to bit 20 of the Self-ID packet), indicates if a node is a contender for bus manager. C/LKON may also output a 6.114-MHz ±100 ppm signal, indicating reception of a link-on packet. See Table 4-29 of the IEEE 1394-1995 standard for additional details. In order to operate with power supplies as low as 2.7 V, this device is restricted to applications that do not provide When the TSB11LV01 is used in applications with a 5-V link layer controller, such as the TSB12C01A, the BIAS–5V terminal should be connected to the link layer controller 5-V supply. Otherwise, connect this terminal to DV CC . A power-down terminal (PWRDN) is provided to allow most of the TSB11LV01 circuits to be powered down to conserve energy in battery-driven applications. A cable status terminal (CNA) provides a high output when the twisted-pair cable port is disconnected. This output is not debounced. The CNA output can determine when to power the device down. In the power-down mode all circuitry is disabled except the CNA detection circuitry. If the power supply of the TSB11LV01 is removed while the twisted-pair cables are connected, the TSB11LV01 transmitter and receiver circuitry has been designed to present a high-impedance signal to the cable and not load the TPBIAS voltage on the other end of the cable.

3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER SLLS232B – MARCH 1996 – REVISED MAY 1997 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 functional block diagram Link Interface I/O Received Data Decoder/ Retimer Arbitration and Control State Machine Logic CPS LPS CNA SYSCLK LREQ CTL0 CTL1 Cable Port 1 Transmit Data Encoder Crystal Oscillator, PLL System, and Clock Generator Bias Voltage and Current Generator TPBIAS TPA+ TPA– TPB+ TPB– XI XO PLLFLT PC0 PC1 PC2 C/LKON TESTM1 TESTM2 PWRDN RESET

3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER SLLS232B – MARCH 1996 – REVISED MAY 1997

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NAME NO. I/O TYPE DESCRIPTION ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ AGND ÁÁÁ Á Á Á Á Á Á ÁÁÁ 21, 23, 24, 26, ÁÁÁ Á Á Á Á Á Á ÁÁÁ ÁÁÁ Á Á Á Á Á Á ÁÁÁ Supply ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Analog circuit ground. The AGND terminals should be tied to the low-im- pedance circuit board ground plane. ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ AV CC ÁÁÁ Á Á Á Á Á Á Á Á Á ÁÁÁ 22, 28, 29, 44 ÁÁÁ Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á ÁÁÁ Supply ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Analog circuit power. AVCC supplies power to the analog portion of the device. It is recommended that a combination of high-frequency decoupling Lower frequency 10-µF filtering capacitors can also be used. These supply pins are separated internally in the device to provide noise isolation. These terminals should also be tied at a low-impedance point on the circuit board. Individual filtering networks for each is desired. ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ C/LKON ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ I/O ÁÁÁ Á Á Á ÁÁÁ CMOS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Bus manager capable (input). When set as an input, C/LKON is used to specify in the Self-ID packet that the node is bus manager capable. ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁ Á Á Á Á Á Á Á Á Á ÁÁÁ Á Á Á Á Á Á Á Á Á ÁÁÁ Á Á Á Á Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Link-on (output). When set as an output, C/LKON indicates the reception of a link-on message by asserting a 6.114-MHz signal. The bit value program- ming is done by tying the terminal through a 10-kΩ resistor to VCC (high) or to GND (low). Using either the pullup or pulldown resistor allows the LKON output to override the input value when necessary. ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ CNA ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ O ÁÁÁ Á Á Á ÁÁÁ CMOS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Cable not active. CNA is asserted high when the TSB11LV01 port is not connected to another active port. ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ CPS ÁÁÁ Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á ÁÁÁ I ÁÁÁ Á Á Á Á Á Á Á Á Á ÁÁÁ CMOS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Cable power status. CPS is normally connected to the cable power through a 400-kΩ resistor. This circuit drives an internal comparator that detects the presence of cable power. This information is maintained in two internal registers and is available to the link by way of a register read. See the Phy- Link Interface Application Note in the IEEE 1394-1995 standard. ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ CTL0, CTL1 ÁÁÁ Á Á Á ÁÁÁ 8, 9 ÁÁÁ Á Á Á ÁÁÁ I/O ÁÁÁ Á Á Á ÁÁÁ CMOS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Control I/O. The CTL terminals are bidirectional communications control signals between the TSB11LV01 and the link. These signals control the passage of information between the two devices. ÁÁÁÁÁ ÁÁÁÁÁ D0, D1 ÁÁÁ ÁÁÁ 10, 11 ÁÁÁ ÁÁÁ I/O ÁÁÁ ÁÁÁ CMOS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Data I/O. The D terminals are bidirectional and pass data between the TSB11LV01 and the link. ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ DGND ÁÁÁ Á Á Á Á Á Á ÁÁÁ 13, 15, 17, 19, 20, ÁÁÁ Á Á Á Á Á Á ÁÁÁ ÁÁÁ Á Á Á Á Á Á ÁÁÁ Supply ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Digital circuit ground. The DGND terminals should be tied to the low-imped- ance circuit board ground plane. ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ DV CC ÁÁÁ Á Á Á Á Á Á Á Á Á ÁÁÁ 14, 18, ÁÁÁ Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á ÁÁÁ Supply ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Digital circuit power. DVCC supplies power to the digital portion of the de- vice. It is recommended that a combination of high-frequency decoupling Lower frequency 10-µF filtering capacitors can also be used. These supply pins are separated internally in the device to provide noise isolation. These terminals should also be tied at a low-impedance point on the circuit board. Individual filtering networks for each is desired. ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ BIAS–5V ÁÁÁ Á Á Á Á Á Á ÁÁÁ ÁÁÁ Á Á Á Á Á Á ÁÁÁ ÁÁÁ Á Á Á Á Á Á ÁÁÁ Supply ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 5 V bias. BIAS-5V should be connected to the link VCC supply when a 5-V link is connected to the phy. When a 3-V link is used, BIAS-5V should be connected to the phy DVCC . ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ LPS ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ I ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ CMOS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Link power status. This terminal is connected to either the VCC supplying the link or to a pulsed output that is active when the link is powered for the purpose of monitoring the link’s power status. When this input is low for more than 2.56 µs, then the link is considered powered down. When this input is high for more than 80 ns, then the link is considered powered up. If the link is not powered, the phy–link interface is disabled, and the TSB11LV01 performs only the basic repeater functions required for network initialization and operation. ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ LREQ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ I ÁÁÁ Á Á Á ÁÁÁ CMOS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Link request. LREQ is an input from the link that signals the TSB11LV01 of a request to perform some service.

3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER SLLS232B – MARCH 1996 – REVISED MAY 1997 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (continued) TERMINAL I/O TYPE DESCRIPTION NAME NO. I/O TYPE DESCRIPTION ÁÁÁÁÁÁ Á ÁÁÁÁ Á Á ÁÁÁÁ Á ÁÁÁÁÁÁ PC0, PC1, PC2 ÁÁÁ Á Á Á Á Á Á ÁÁÁ 4, 5, 6 ÁÁ ÁÁ ÁÁ ÁÁ I ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ CMOS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Power class indicators. the PC signals set the bit values of the three power class bits in the Self-ID packet (bits 21, 22, and 23). These bits can be pro- grammed by tying the terminals to VCC (high) or to GND (low). ÁÁÁÁÁÁ Á ÁÁÁÁ Á ÁÁÁÁÁÁ PLLFLT ÁÁÁ Á Á Á ÁÁÁ ÁÁ ÁÁ ÁÁ I ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ CMOS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PLL filter. PLLFLT is connected to a 0.1-µF capacitor and then to AGND to complete the internal lag-lead filter. This filter is required for stable opera- tion of the frequency multiplier PLL running off of the crystal oscillator. ÁÁÁÁÁÁ ÁÁÁÁÁÁ PLLGND ÁÁÁ ÁÁÁ 39, 40 ÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁ Supply ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PLL circuit ground. The PLLGND terminals should be tied to the low-imped- ance circuit board ground plane. ÁÁÁÁÁÁ Á ÁÁÁÁ Á Á ÁÁÁÁ Á Á ÁÁÁÁ Á Á ÁÁÁÁ Á ÁÁÁÁÁÁ PLLV CC ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ Supply ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PLL circuit power. PLLVCC supplies power to the PLL portion of the device. It is recommended that a combination of high-frequency decoupling capaci- frequency 10-µF filtering capacitors can also be used. These supply pins are separated internally in the device to provide noise isolation. These ter- minals should also be tied at a low impedance point on the circuit board. Individual filtering networks for each is desired. ÁÁÁÁÁÁ Á ÁÁÁÁ Á ÁÁÁÁÁÁ PWRDN ÁÁÁ Á Á Á ÁÁÁ ÁÁ ÁÁ ÁÁ I ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ CMOS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Powerdown. When asserted high, PWRDN turns off all internal circuitry except the CNA monitor circuits that drive the CNA terminal. ÁÁÁÁÁÁ Á ÁÁÁÁ Á Á ÁÁÁÁ Á ÁÁÁÁÁÁ R1, R0 ÁÁÁ Á Á Á Á Á Á ÁÁÁ 31, 32 ÁÁ ÁÁ ÁÁ ÁÁ ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ Bias ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Current setting resistor. An internal reference voltage is applied to a resistor connected between these two terminals to set the operating current and the cable driver output current. A low TCR 6 kΩ ±5% resistor should be used to meet the IEEE 1394-1995 standard requirements for output voltage limits. ÁÁÁÁÁÁ Á ÁÁÁÁ Á Á ÁÁÁÁ Á ÁÁÁÁÁÁ RESET ÁÁÁ Á Á Á Á Á Á ÁÁÁ ÁÁ ÁÁ ÁÁ ÁÁ I ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ CMOS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reset. When RESET is asserted low (active), a bus reset condition is set on the active cable ports and the the internal logic is reset to the reset start state. An internal pullup resistor, which is connected to VCC , is provided so only an external delay capacitor is required. This input is a standard logic buffer and can also be driven by an open-drain logic output buffer. ÁÁÁÁÁÁ Á ÁÁÁÁ Á ÁÁÁÁÁÁ SYSCLK ÁÁÁ Á Á Á ÁÁÁ ÁÁ ÁÁ ÁÁ O ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ CMOS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ System clock. SYSCLK provides a 49.152-MHz clock signal, which is syn- chronized with the data transfers, to the link. ÁÁÁÁÁÁ ÁÁÁÁÁÁ TESTM1, TESTM2 ÁÁÁ ÁÁÁ 48, 47 ÁÁ ÁÁ I ÁÁÁÁ ÁÁÁÁ CMOS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Test mode control. TESTM1 and TESTM2 are used during manufacturing test and should be tied to VCC . ÁÁÁÁÁÁ ÁÁÁÁÁÁ TPA+ ÁÁÁ ÁÁÁ ÁÁ ÁÁ I/O ÁÁÁÁ ÁÁÁÁ Cable ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Port cable pair A. TPA is the port A connection to the twisted pair cable. Board traces from these terminal should be kept matched and as short as ÁÁÁÁÁÁ ÁÁÁÁÁÁ TPA– ÁÁÁ ÁÁÁ ÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Board traces from these terminal should be ke t matched and as short as possible to the external load resistors and to the cable connector. ÁÁÁÁÁÁ Á ÁÁÁÁ Á ÁÁÁÁÁÁ TPB+ ÁÁÁ Á Á Á ÁÁÁ ÁÁ ÁÁ ÁÁ I/O ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ Cable ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Port cable pair B. TPB is the port B connection to the twisted pair cable. Board traces from these terminal should be kept matched and as short as ÁÁÁÁÁÁ ÁÁÁÁÁÁ TPB– ÁÁÁ ÁÁÁ ÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Board traces from these terminal should be ke t matched and as short as possible to the external load resistors and to the cable connector. ÁÁÁÁÁÁ Á ÁÁÁÁ Á ÁÁÁÁÁÁ TPBIAS ÁÁÁ Á Á Á ÁÁÁ ÁÁ ÁÁ ÁÁ O ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ Cable ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Twisted-pair bias. TPBIAS provides the 1.86-V nominal bias voltage need- ed for proper operation of the twisted-pair cable drivers and receivers and for sending a valid cable connection signal to the remote nodes. ÁÁÁÁÁÁ Á ÁÁÁÁ Á Á ÁÁÁÁ Á ÁÁÁÁÁÁ XO, XI ÁÁÁ Á Á Á Á Á Á ÁÁÁ 37, 38 ÁÁ ÁÁ ÁÁ ÁÁ ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ Crystal ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Crystal oscillator. X0 and X1 connect to a 24.576-MHz parallel resonant fundamental mode crystal. The optimum values for the external shunt ca- pacitors are dependent on the specifications of the crystal used. The sug- gested values of 12 pF are appropriate for a crystal with 15 pF specified loads.

3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER SLLS232B – MARCH 1996 – REVISED MAY 1997

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING OPERATING FACTOR † ABOVE T A = 25°C TA = 70°C POWER RATING PT 1315 mW 10.5 mW/°C 842 mW † This is the inverse of the traditional junction-to-case thermal resistance (RθJA) and uses a board-mounted 95°C/W. recommended operating conditions MIN NOM MAX UNIT ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Supply voltage, VCC(SP) ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ 3.3 ÁÁÁÁ ÁÁÁÁ 3.6 ÁÁÁ ÁÁÁ V ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Supply voltage, VCC(NSP) ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ 2.7‡ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ 3.6 ÁÁÁ ÁÁÁ V ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ High-level input voltage, VIH ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ CMOS inputs ÁÁÁÁ ÁÁÁÁ

0.7 VCC

ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ V ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Low-level input voltage, VIL ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ CMOS inputs ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ

0.2 VCC

ÁÁÁ ÁÁÁ V ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Differential input voltage, VID ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Cable inputs ÁÁÁÁ ÁÁÁÁ 142 ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ 260 ÁÁÁ ÁÁÁ mV ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Common mode input voltage V ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Cable inputs, V CC > 3 V ÁÁÁÁ ÁÁÁÁ 1.165 ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ 2.515 ÁÁÁ ÁÁÁ V ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ C ommon-mo de input voltage, VIC ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Cable inputs, V CC < 3 V ÁÁÁÁ ÁÁÁÁ 1.165 ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ 2.015‡ ÁÁÁ ÁÁÁ V ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Receive input jitter ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ TPA, TPB cable inputs ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ±1.08 ÁÁÁ ÁÁÁ ns ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Receive input skew ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Between TPA and TPB cable inputs ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ± 0.8 ÁÁÁ ÁÁÁ ns ÁÁÁÁÁÁÁÁÁÁÁÁÁ High or low level output current IOL or IOH ÁÁÁÁÁÁÁÁÁÁÁÁ SYSCLK ÁÁÁÁ –16 ÁÁÁ ÁÁÁÁ ÁÁÁ mA ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ High- or low-level output current, IOL or IOH ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ CTL0, CTL1, D0, D1, CNA ÁÁÁÁ ÁÁÁÁ –12 ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ mA ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Output current, IO ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ TPBIAS ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ mA ‡ This parameter is for a node that does not source power (see section 4.2.2.2 in IEEE 1394-1995 standard). electrical characteristics over recommended ranges of operating conditions (unless otherwise noted) driver PARAMETER TEST CONDITION MIN MAX UNIT ÁÁÁÁ ÁÁÁÁ VOD ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Differential output voltage ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ 56-Ω load ÁÁÁ ÁÁÁ 172 ÁÁÁÁ ÁÁÁÁ 265 ÁÁÁ ÁÁÁ mV ÁÁÁÁ ÁÁÁÁ I(DIFF) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Driver difference output current ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Driver enabled ÁÁÁ ÁÁÁ –1.05§ ÁÁÁÁ ÁÁÁÁ 1.05§ ÁÁÁ ÁÁÁ mA ÁÁÁÁ ÁÁÁÁ VD ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Off-state voltage ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ mV § This parameter limits are defined as algebraic sum of TPA+ and TPA– driver currents. These limits also apply to TPB+ and TPA– algebraic sum of driver currents.

3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER SLLS232B – MARCH 1996 – REVISED MAY 1997 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 receiver PARAMETER TEST CONDITION MIN MAX UNIT ÁÁÁ ÁÁÁ IIC ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Common-mode input current ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Driver disabled ÁÁÁ ÁÁÁ –20 ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ µA ÁÁÁ Á Á Á ÁÁÁ zID ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Differential input impedance ÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁ Driver disabled ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ kΩ pF ÁÁÁ ÁÁÁ zIC ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Common-mode input impedance ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Driver disabled ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ kΩ pF ÁÁÁ ÁÁÁ VIT1 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Receiver input threshold voltage ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ –30 ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ mV ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Cable-bias detect threshold, TPB cable input ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Driver disabled ÁÁÁ ÁÁÁ 0.6 ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ V device PARAMETER TEST CONDITION MIN TYP MAX UNIT ÁÁÁÁ ÁÁÁÁ VIT2 ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Power status input threshold voltage (CPS) ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ 400-kΩ resistor ÁÁÁÁÁ ÁÁÁÁÁ 4.7 ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ 7.5 ÁÁÁ ÁÁÁ V ÁÁÁÁ ÁÁÁÁ VOH ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ High-level output voltage ÁÁÁÁÁ ÁÁÁÁÁ IOH = max, ÁÁÁÁÁ ÁÁÁÁÁ VCC = min ÁÁÁÁÁ ÁÁÁÁÁ VCC –0.55 ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ V ÁÁÁÁ ÁÁÁÁ VOL ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Low-level output voltage ÁÁÁÁÁ ÁÁÁÁÁ IOL = min, ÁÁÁÁÁ ÁÁÁÁÁ VCC = max ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ 0.5 ÁÁÁ ÁÁÁ V ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁ Input current (LREQ, LPS, PD, PC0, PC1, PC2) ÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁ VI=VCC or 0 ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ ± 1 ÁÁÁ Á Á Á ÁÁÁ µA ÁÁÁÁ ÁÁÁÁ IOZ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ High-impedance-state output current (CTL0, CTL1, D0, D1, C/LKON) ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ VO = VCC or 0 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ± 5 ÁÁÁ ÁÁÁ µA ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ P ll p inp t c rrent RESET ÁÁÁÁÁ ÁÁÁÁÁ VI =1.5 V ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ –20 ÁÁÁ ÁÁÁ –40 ÁÁÁÁ ÁÁÁÁ –80 ÁÁÁ ÁÁÁ µA ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Pullup input current, RESET ÁÁÁÁÁ ÁÁÁÁÁ VI =0 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ –22 ÁÁÁ ÁÁÁ –45 ÁÁÁÁ ÁÁÁÁ –90 ÁÁÁ ÁÁÁ µA ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Power-up reset time, RESET ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ms ÁÁÁÁ ÁÁÁÁ V(TO)+ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Positive arbitration comparator threshold voltage ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ 168 ÁÁÁ ÁÁÁ mV ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ V(TO)– ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁ Negative arbitration comparator threshold voltage ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ –168 ÁÁÁ Á Á Á ÁÁÁ ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ –89 ÁÁÁ Á Á Á ÁÁÁ mV ÁÁÁÁ ÁÁÁÁ VO TPBIAS output voltage ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ 1.665 ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ 2.015 ÁÁÁ ÁÁÁ V ÁÁÁÁ ÁÁÁÁ ICC Supply current, receiver active VCC = 3.6 V ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ 115 ÁÁÁ ÁÁÁ mA ÁÁÁÁ ÁÁÁÁ ICC(PD) Supply current, power-down mode VCC = 3 V ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ mA thermal characteristics PARAMETER TEST CONDITION MIN TYP MAX UNIT ÁÁÁ R θJA ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Junction-to-free-air thermal resistance ÁÁÁÁÁ Board mounted, ÁÁÁÁÁ No air flow ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ °C/W ÁÁÁ ÁÁÁ R θJA ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Junction-to-case-thermal resistance ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ °C/W switching characteristics PARAMETER ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ MEASURED ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ TEST CONDITION ÁÁÁ ÁÁÁ MIN ÁÁÁÁ ÁÁÁÁ MAX ÁÁÁ ÁÁÁ UNIT ÁÁ ÁÁ Jitter, transmit ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ TPA, TPB ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ± 0.8 ÁÁÁ ÁÁÁ ns ÁÁ ÁÁ Skew time, transmit ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Between TPA and TPB ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ± 0.4 ÁÁÁ ÁÁÁ ns ÁÁ ÁÁ tr Rise time, transmit ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 10% to 90% ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ R L = 55 Ω , C L = 10 pF ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ 3.2 ÁÁÁ ÁÁÁ ns ÁÁ ÁÁ tf Fall time, transmit ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 90% to 10% ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ R L = 55 Ω , C L = 10 pF ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ 3.2 ÁÁÁ ÁÁÁ ns ÁÁ ÁÁ tsu Setup time, D, CTL, LREQ low or high before SYSCLK ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 50% to 50% ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ See Figure 1 ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ns ÁÁ ÁÁ ÁÁ th Hold time, D, CTL, LREQ low or high after SYSCLK ÁÁÁÁÁÁÁ Á ÁÁÁÁÁ Á ÁÁÁÁÁÁÁ 50% to 50% ÁÁÁÁÁÁÁ Á ÁÁÁÁÁ Á ÁÁÁÁÁÁÁ See Figure 1 ÁÁÁ Á Á Á ÁÁÁ ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ns ÁÁ ÁÁ td Delay time, SYSCLK high to D, CTL low or high ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 50% to 50% ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ See Figure 2 ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ns

3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER SLLS232B – MARCH 1996 – REVISED MAY 1997

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION tsu th SYSCLK D, CTL, LREQ 50% 50%50% Figure 1. D, CTL, LREQ Input Setup and Hold Timing Waveforms Figure 2. D and CTL Output Delay Timing Waveforms

APPLICATION INFORMATION

A Cable Pair B 56 Ω 56 Ω 5 kΩ TPBIAS TPA+ TPA– TPB+ TPB– 1 µF TYP TSB11LV01 250 pF 56 Ω 56 Ω Figure 3. Twisted-Pair Cable Interface Connections

3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER SLLS232B – MARCH 1996 – REVISED MAY 1997 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 internal register configuration The accessible internal registers of this device are listed in Table 1. Descriptions of the internal register fields are given in Table 2. Table 1. Accessible Internal Registers

0000 Physical ID R CPS

0001 RHB IBR GC

0010 SPD Rev NP

0011 AStat BStat Ch Con Reserved

0100 Reserved

0101 Reserved

0110 Looplnt CPSlnt CPS IR Reserved

0111 Reserved

1000 Reserved

Table 2. Internal Register Field Descriptions ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ AStat ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ Read only AStat contains the line state of TPA. The status is indicated by the following: 11 = Z 01 = 1 10 = 0 00 = Invalid data state. Power-up reset initializes to this line state. This line state is also output dur- ing transmit and receive operations. The line state outputs are generally valid during arbitration and idle conditions on the bus. ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ BStat ÁÁÁ Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ Read only BStat contains the line state of TPB. The status is indicated by the following: 11 = Z 01 = 1 10 = 0 00 = Invalid data state. Power up reset initializes to this line state. This line state is also output dur- ing transmit and receive operations. The line state outputs are generally valid during arbitration and idle conditions on the bus. ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ Ch ÁÁÁ Á Á Á ÁÁÁ ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ Read only When Ch = 1, the port is a child, otherwise it is a parent. This bit is invalid after a hardware reset or a bus reset until tree-ID processing is completed. ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ Con ÁÁÁ Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ Read only Con indicates the connection status of the port. When Con = 1, the port is connected, otherwise it is disconnected. This bit is set to 1 by a hardware reset and is updated to reflect the actual cable con- nection status of the port during bus reset. The TSB11LV01 contains connection debounce circuitry that prevents a new cable connection on a port from initiating a bus reset until the connection status has been stable for at least 335 ms. Similarly, a cable disconnect must be stable for 1.3 ms before a bus reset is initiated. ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ CPS ÁÁÁ Á Á Á ÁÁÁ ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ Read only Cable power status (CPS) contains the status of the CPS input terminal. When cable power voltage has dropped too low for reliable operation, this bit is reset (0). This bit is included twice in the internal registers to expedite handling of the CPSInt. CPSInt 1 Read/Write CPSint indicates that a cable power status interrupt has occurred. This interrupt occurs whenever the CPS input goes low. The interrupt indicates that the cable power voltage has dropped too low to ensure reliable operation. This bit is cleared (0) by a hardware reset or by writing a 0 to this register. However, if the CPS input is still low, another cable power status interrupt immediately occurs.

3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER SLLS232B – MARCH 1996 – REVISED MAY 1997

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Table 2. Internal Register Field Descriptions (continued) ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ GC ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ Read/Write The gap count (GC) register sets the fair and arb-reset gap times. The gap count may be set to a particular value to optimize bus performance. Typically, the gap count should be set to 2 times the maximum number of hops on the bus and should be set to the same value for all nodes on the bus. The gap count can be set by either a write to this register or by reception or transmission of a PHY_CONFIG packet. The gap count is reset to a 3Fh after a hardware reset or after two consecu- tive bus resets without an intervening write to the gap count register (either a write to the gap count register by the link or a PHY_CONFIG packet). IBR 1 Read/Write When set, initiate bus reset (IBR) causes this node to immediately initiate a bus reset. IBR is cleared (0) after a hardware reset or a bus reset. ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ IR ÁÁÁ Á Á Á ÁÁÁ ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ Read/Write IR indicates that the last bus reset was initiated in this TSB11LV01 phy. This bit is also included in the Self-ID packet. ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ LoopInt ÁÁÁ Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ Read/Write LoopInt indicates that a configuration loop timeout has occurred. This interrupt occurs when the ar- bitration controller waits for too long a period of time during tree-ID. This interrupt can indicate that the bus is configured in a loop. This bit is cleared (0) by a hardware reset or by writing a 0 to this register bit. It should be noted that the TSB11LV01 never generates this interrupt since it has only one available port and, therefore, cannot be part of a loop. ÁÁÁÁÁ ÁÁÁÁÁ NP ÁÁÁ ÁÁÁ 4 ÁÁÁÁ ÁÁÁÁ Read only The number of ports (NP) contains the number of ports implemented in the core logic (not the num- ber of ports actually on the device). For the TSB11LV01, NP is set to 0011. ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ Physical ID ÁÁÁ Á Á Á ÁÁÁ ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ Read only Physical ID contains the physical address of the local node. The physical ID defaults to a 09h after a hardware reset or a bus reset until the Self-ID process has been completed. A complete Self-ID is indicated by an unsolicited status transfer of the register 0 contents to the link. ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ R ÁÁÁ Á Á Á ÁÁÁ ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ Read only R indicates whether this node is the root node or not. This bit is cleared (0) on a hardware reset or a bus reset. This bit is set during tree-ID when this node is root. ÁÁÁÁÁ ÁÁÁÁÁ Rev ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ Read only The revision (Rev) bits indicate the design revision of the core logic. For the TSB11LV01, Rev is set to 01. ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ RHB ÁÁÁ Á Á Á ÁÁÁ ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ Read/Write When set, the root hold-off bit (RHB) instructs the local node to try to become the root during the next bus reset. RHB is reset (0) during a hardware reset and is not affected by a bus reset. ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ SPD ÁÁÁ Á Á Á ÁÁÁ ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ Read only The speed (SPD) bits indicates the top signaling speed of the local port and for the TSB11LV01 is set to 00.

3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER SLLS232B – MARCH 1996 – REVISED MAY 1997 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 DGND DGND BIAS–5 V DGND DGND AGND CNAOUT LINKV DD 10 kΩ BUS MANAGER LKON POWER-CLASS PROGRAMMING LINK LAYER CONTROLLER INTERFACE VCC LINKV CC VCC VCC TPBIAS VCC 400 kΩ CABLE POWER 6 kΩ TP CABLES 12 pF 12 pF VCC 0.1 µF POWER DOWN VCC VCC 0.1 µF CNA LPS C/LKON PC0 PC1 PC2 LREQ CTL0 CTL1 SYSCLK TESTM1 DVCC DV CC DGND AVCC AGND AGND TPBIAS AGND AGND AV CC AV CC CPS TPB– TPB+ TPA– TPA+ TESTM2 RESET DVCC AVCC PWRDN PLLFLT PLLVCC PLLGND PLLGND XI XO TSB11LV01 1 µF

24.576 MHz

Figure 4. External Component Connections

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The TSB11LV01 is designed to operate with a link layer controller such as the Texas Instruments TSB12C01A. These devices use a direct-connect interface such as described in Annex J of the IEEE 1394-1995 standard. following paragraphs describes the operation of the phy-link interface. the exception of the request operation, all actions are initiated by the phy. When the phy has control of the bus, the CTL0 and CTL1 lines are encoded as shown in Table 3. Table 3. CTL Status When Phy Has Control of the Bus Table 4. CTL Status When Link Has Control of the Bus is the most significant, and is transmitted first. The LREQ terminal is required to idle low. Table 5. Link Bus Request or Register Access Request Bit Length

3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER SLLS232B – MARCH 1996 – REVISED MAY 1997 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION For a Bus Request the length of the LREQ data stream is 7 bits and is shown in Table 6. Table 6. Link Bus Request ÁÁÁÁÁ ÁÁÁÁÁÁ Start Bit ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ This bit indicates the beginning of the transfer (always 1). ÁÁÁÁÁ ÁÁÁÁÁ 1–3 ÁÁÁÁÁÁ ÁÁÁÁÁÁ Request Type ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ These bits indicate the type of bus request (see Table 9 for the encoding of this field). ÁÁÁÁÁ ÁÁÁÁÁ 4–5 ÁÁÁÁÁÁ ÁÁÁÁÁÁ Request Speed ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ These bits should always be 00 for TSB11LV01 100 Mbits/s speed. ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ Stop Bit ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ This bit indicates the end of the transfer (always 0). For a Read Register Request the length of the LREQ data stream is 9 bits and is shown in Table 7. Table 7. Link Read Register Access ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ Start Bit ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ This bit indicates the beginning of the transfer (always 1). ÁÁÁÁÁ ÁÁÁÁÁ 1–3 ÁÁÁÁÁÁ ÁÁÁÁÁÁ Request Type ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ These bits are always 100 indicating that this is a read register request. ÁÁÁÁÁ ÁÁÁÁÁ 4–7 ÁÁÁÁÁÁ ÁÁÁÁÁÁ Address ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ These bits are the address of the phy register to be read. ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ Stop Bit ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ This bit indicates the end of the transfer (always 0). For a Write Register Request the length of the LREQ data stream is 17 bits and is shown in Table 8. Table 8. Link Write Register Access ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ Start Bit ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ This bit indicates the beginning of the transfer (always 1). ÁÁÁÁÁ 1–3 ÁÁÁÁÁÁ Request Type ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ These bits are always 101 indicating that this is a write register request. ÁÁÁÁÁ ÁÁÁÁÁ 4–7 ÁÁÁÁÁÁ ÁÁÁÁÁÁ Address ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ These bits are the address of the phy register to be written to. ÁÁÁÁÁ ÁÁÁÁÁ 8–15 ÁÁÁÁÁÁ ÁÁÁÁÁÁ Data ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ These bits are the data that is written to the specified register address. ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ Stop Bit ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ This bit indicates the end of the transfer (always 0). The 3-bit Request Type fields are described in Table 9. Table 9. Link Bus Request Type ÁÁÁÁÁ ÁÁÁÁÁ 000 ÁÁÁÁÁÁ ÁÁÁÁÁÁ ImmReq ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Immediate request. When an idle is detected, take control of the bus immediately (no arbitration). ÁÁÁÁÁ ÁÁÁÁÁ 001 ÁÁÁÁÁÁ ÁÁÁÁÁÁ IsoReq ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Isochronous request. Arbitrate for the bus with no gaps. ÁÁÁÁÁ ÁÁÁÁÁ 010 ÁÁÁÁÁÁ ÁÁÁÁÁÁ PriReq ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Priority request. Arbitrate after a subaction gap and ignore fair protocol. ÁÁÁÁÁ ÁÁÁÁÁ 011 ÁÁÁÁÁÁ ÁÁÁÁÁÁ FairReq ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Fair request. Arbitrate after a subaction gap and use fair protocol. ÁÁÁÁÁ ÁÁÁÁÁ 100 ÁÁÁÁÁÁ ÁÁÁÁÁÁ RdReg ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Read register. Return the specified register contents through a status transfer ÁÁÁÁÁ 101 ÁÁÁÁÁÁ WrReg ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Write register. Write to the specified register. ÁÁÁÁÁ ÁÁÁÁÁ 110, 111 ÁÁÁÁÁÁ ÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved

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NOTE A: Each cell in this timing diagram represents one clock sample time. Figure 5. LREQ Timing requesting the bus. The link then reissues the request one clock after the next interface idle. the reception of a cycle start packet. allowed to proceed with another request. acknowledgment packet (this is handled by the higher-layer protocol). to the link, the phy continues to attempt to transfer the contents of the register until it is successful. has been completed. The link is allowed to request register read or write operations at any time.

3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER SLLS232B – MARCH 1996 – REVISED MAY 1997 17POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION status A status transfer is initiated by the phy when it has status information to transfer to the link. The phy waits until the interface is idle before starting the transfer. The transfer is initiated by asserting the following on the the control terminals: CTL0 and CTL1 = 01 along with the first two bits of status information on the D0 and D1 terminals. The phy maintains CTL0 and CTL1 = 01 for the duration of status transfer. The phy may prematurely end a status transfer by asserting something else other than CTL0 and CTL1 = 01 on the control terminals. This could be caused by an incoming packet from another node. The phy continues to attempt to complete the transfer until the information has been successfully transmitted. There must be at least one idle cycle in between consecutive status transfers. The phy normally sends just the first four bits of status to the link. These bits are status flags that are needed by the link state machines. The phy sends an entire status packet to the link after a request transfer that contains a read request, or when the phy has pertinent information to send to the link or transaction layers. The only defined condition where the phy automatically sends a register to the link is after Self-ID, when it sends the Physical-ID register, which contains the new node address. The descriptions of the bits in the status transfer are listed in Table 10 and the timing is shown in Figure 6. Table 10. Status Transfer Bit Description ÁÁÁÁÁÁ Á ÁÁÁÁ Á ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Á ÁÁÁÁÁ Á ÁÁÁÁÁÁÁ Arbitration Reset Gap ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ This bit indicates that the phy has detected that the bus has been idle for an arbitration reset gap time (this time is defined in the IEEE 1394-1995 standard). This bit is used by the link in its busy/retry state machine. ÁÁÁÁÁÁ Á ÁÁÁÁ Á Á ÁÁÁÁ Á ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Á ÁÁÁÁÁ Á Á ÁÁÁÁÁ Á ÁÁÁÁÁÁÁ Subaction Gap ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ This bit indicates that the phy has detected that the bus has been idle for a subaction gap time (this time is defined in the IEEE 1394-1995 standard). This bit is used by the link to detect the completion of an isochronous cycle. ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Bus Reset ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ This bit indicates that the phy has entered the bus reset state. ÁÁÁÁÁÁ Á ÁÁÁÁ Á ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Á ÁÁÁÁÁ Á ÁÁÁÁÁÁÁ CPS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ This bit indicates that the cable power has dropped below the threshold for reliable op- eration. ÁÁÁÁÁÁ ÁÁÁÁÁÁ 4–7 ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Address ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ These bits hold the address of the phy register whose contents are transferred to the link. ÁÁÁÁÁÁ ÁÁÁÁÁÁ 8–15 ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Data ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ These bits contain the data that is to be sent to the link. 00 01 01 01 00 00 Phy CTL0, CTL1

00 S[0,1] 00 00

Figure 6. Status Transfer Timing

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when it is ready to transmit as soon as bus ownership is granted. it releases control of the interface. informing the network of a change in speed. Figure 7. Transmit Timing Waveforms

When data is received by the phy from the serial bus, the phy transfers the data to the link for further processing. completely transferred, the phy asserts idle on the CTL terminals, which completes the receive operation. The speed is a phy-link protocol and not included in the CRC.

11 SPD D0 D1Phy

Figure 8. Receive Timing Waveforms Table 11. Speed Code For the Receiver

100 Mbits/s

Table 12. Self-ID Packet Power Field Bit Description 000 Node does not need power and does not repeat power. 001 Node is self powered and provides a minimum of 15 W to the bus. 010 Node is self powered and provides a minimum of 30 W to the bus. 011 Node is self powered and provides a minimum of 45 W to the bus. 100 Node may be powered from the bus and is using up to 1 W. 101 Node may be powered from the bus and is using up to 1 W. An additional 2 W is needed to enable the link and higher layers. 110 Node may be powered from the bus and is using up to 1 W. An additional 5 W is needed to enable the link and higher layers. 111 Node may be powered from the bus and is using up to 1 W. An additional 9 W is needed to enable the link and higher layers.

3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER SLLS232B – MARCH 1996 – REVISED MAY 1997

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PT (S-PQFP-G48) PLASTIC QUAD FLATPACK 4040052/C 11/96 0,13 NOM 0,17 0,27 SQ 6,80 7,20 5,50 TYP 0,25 0,45 0,75 0,05 MIN SQ9,20 8,80 1,35 1,45 1,60 MAX Gage Plane Seating Plane 0,10 0°–7° 0,50 M0,08 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 D. This may also be a thermally enhanced plastic package with leads conected to the die pads.

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