TSA0801

TSA0801 STMICROELECTRONICS | Alldatasheet

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Technical content

n 8-bit A/D converter in deep submicron CMOS technology n Single supply voltage: 2.5V n Input range: 2Vpp differential n 40Msps sampling frequency n Ultra low power consumption: 40mW @ 40MHz (10mW @ 5Msps) n ENOB=7.9 @ Nyquist n SFDR typically up to 67dB @ Fs=40Msps, Fin=5MHz n Built-in reference voltage with external bias capability n STMicroelectronics 8, 10, 12 and 14-bits ADC pinout compatibility

DESCRIPTION

The TSA0801 is an 8-bit, 40MHz sampling fre- quency Analog to Digital converter using a deep submicron CMOS technology combining high per- formances and very low power consumption. The TSA0801 is based on a pipeline structure and digital error correction to provide excellent static linearity and go beyond 7.9 effective bits at Fs=40Msps, and Fin=10MHz. A voltage reference is integrated in the circuit to simplify the design and minimize external compo- nents. It is nevertheless possible to use the circuit with an external reference. Differential or single-ended analog inputs can be applied to the converter. A tri-state capability is available on the outputs. The output data can be coded into two different formats. A Data Ready signal is raised as the data is valid on the output and can be used for synchronization purposes. The TSA0801 is available in commercial (0 to +70°C) and extended (-40 to +85°C) temperature range, in a small 48 pins TQFP package.

APPLICATIONS

n Hand-held instrumentation n Camcorders n Computer scanners n Digital communication ORDER CODE PIN CONNECTIONS (top view) PACKAGE Part Number Temperature Range Package Conditioning Marking TSA0801CF 0 °C to +70°C TQFP48 Tray SA0801C TSA0801CFT 0 °C to +70°C TQFP48 Tape& Reel SA0801C TSA0801IF -40 °C to +85°C TQFP48 Tray SA0801I TSA0801IFT -40 °C to +85°C TQFP48 Tape& Reel SA0801I EVAL0801/AA Evaluation board 7 × 7 mm TQFP48 VREFM VREFP NC NC D0(LSB) VINB AGND AGND index corner 13 14 15 16 17 18 19 20 21 22 23 24 48 44 43 42 41 40 39 38 3746 45 AGND VIN D6AVCC AVCC AGND IPOL INCM NC NC AVCC DR NC OEB AGND AVCC DFSB VCCB GNDB NC NC VCCB GNDB GNDB DGND DVCC CLK DGND VCCB NC OR DGND DVCC D7 (MSB) NC TSA0801 TSA0801 8-BIT, 40MSPS, 40mW A/D CONVERTER October 2000

Symbol Parameter Values Unit AVCC Analog Supply voltage1) 0 to 3.3 V DVCC Digital Supply voltage1) 0 to 3.3 V VCCB Digital buffer Supply voltage1) 0 to 3.3 V IDout Digital output current -100 to 100 mA Tstg Storage temperature +150 °C ESD Electrical Static Discharge: - HBM - CDM-JEDEC Standard 1.5 KV 1) All voltages values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages must never exceed -0.3V or VCC+0V Symbol Parameter Test conditions Min Typ Max Unit AVCC Analog Supply voltage 2.25 2.5 2.7 V DVCC Digital Supply voltage 2.25 2.5 2.7 V VCCB Digital buffer Supply voltage 2.25 2.5 2.7 V VREFP Forced top voltage reference 1.16 - AVCC V VREFM Forced bottom reference voltage 0 0 0.5 V stage stage stage 12 n Reference Timing circuit Sequencer-phase shifting Digital data corr ection Buffers IPOL VREFM VREFP CLK +2.5V VIN VINB DFSB OEB DR DO TO OR INCM GND GNDA

PIN CONNECTIONS (top view) PIN DESCRIPTION VREFM VREFP NC NC D0(LSB) VINB AGND AGND index corner 13 14 15 16 17 18 19 20 21 22 23 24 48 44 43 42 41 40 39 38 3746 45 AGND VIN D6AVCC AVCC AGND IPOL INCM NC NC AVCC DR NC OEB AGND AVCC DFSB VCCB GNDB NC NC VCCB GNDB GNDB DGND DVCC CLK DGND VCCB NC OR DGND DVCC D7 (MSB) NC TSA0801 Pin No Name Description Observation Pin No Name Descri ption Observ ation 1 IPOL Analog bias curr ent input 25 D6 Digital output CMOS output (2.5V) 2 VREFP Top voltage reference 1V 26 D5 Digital output CMOS output (2.5V) 3 VREFM Bottom voltage referen ce 0V 27 D4 Digital output CMOS output (2.5V) 4 AGND Analog ground 0V 28 D3 Digital output CMOS output (2.5V) 5 VIN Analog input 1Vpp 29 D2 Digital output CMOS output (2.5V) 6 AGND Analog ground 0V 30 D1 Digital output CMOS output (2.5V) 7 VINB Inverted analog input 1Vpp 31 D0(LSB) Digital output CMOS output (2.5V)

8 AGND Analog ground 0V 32 NC Non conne cted

9 INCM Input common mode 0.5V 33 NC Non conne cted

10 AGND Analog ground 0V 34 NC Non conne cted

11 AVCC Analog power supply 2.5V 35 NC Non conne cted 12 AVCC Analog power supply 2.5V 36 NC Non conne cted 13 DVCC Digital power supply 2.5V 37 NC Non conne cted 14 DVCC Digital power supply 2.5V 38 DR Data Ready output CMOS output (2.5V) 15 DGND Digital ground 0V 39 VCCB Digital Buffer power supply 2.5V 16 CLK Clock input 2.5V compati ble CMOS input 40 GNDB Digital Buffer ground 0V 17 DGND Digital ground 0V 41 VCCB Digital Buffer power supply 2.5V

18 NC Non connected 42 NC Non conne cted

19 DGND Digital ground 0V 43 NC Non conne cted

20 GNDB Digital buffer ground 0V 44 OEB Output Enable input 2.5V compatib le CMOS input 21 GNDB Digital buffer ground 0V 45 DFSB Data Format Select input 2.5V compatib le CMOS input 22 VCCB Digital buffer power supply 2.5V 46 AVCC Analog power supply 2.5V 23 OR Out Of Range output CMOS outp ut(2.5V) 47 AVCC Analog power supply 2.5V 24 D7(MSB) Most Significa ntBit output CMOS outp ut(2.5V) 48 AGND Analog ground 0V

ELECTRICAL CHARACTERISTICS

AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin=1MHz, Vin@ -1.0dBFS, VREFM = 0V Tamb = 25°C (unless otherwise specified) TIMING CHARACTERISTICS TIMING DIAGRAM Symbol Parameter Test conditions Min Typ Max Unit FS Sampling Frequency 0.5 40 MHz DC Clock Duty Cycle 45 50 55 % TC1 Clock pulse width (high) 11 12.5 ns TC2 Clock pulse width (low) 11 12.5 ns Tod Data Output Delay (Fall of Clock to Data Valid) 10pF load capacitance 5n s Tpd Data Pipeline delay 6.5 cycles Ton Falling edge of OEB to digital output valid data 1n s Toff Rising edge of OEB to digital output tri-state 1n sN-1 N N+1 N+6 N+7N+2 N+5 N+3 N+4 N+8 N N+1N-2N-3N-4N-5N-6N-7N-8 CLK DR Tod TonToff 6.5 clk cycles HZ state DATA OUT OEB

AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin= 1MHz, Vin@ -1.0dBFS, VREFM= 0V Tamb = 25°C (unless otherwise specified) ANALOG INPUTS REFERENCE VOLTAGE Symbol Parameter Test conditions Min Typ Max Unit VIN-VINB Full scale reference voltage 2.0 Vpp Cin Input capacitance 7.0 pF BW Analog Input Bandwitdh Vin@-1dBFS, FS=40Msps 100 MHz ERB Effective Resolution Bandwidth1) 60 MHz 1) See parameters definition for more information Symbol Parameter Test conditions Min Typ Max Unit VREFP Top internal reference voltage 0.89 1.03 1.16 V Tmin= -40°C to Tmax= 85°C 1) 0.88 1.16 V Vpol Analog bias voltage 1.19 1.27 1.35 V Tmin= -40°C to Tmax= 85°C 1) 1.18 1.36 V Ipol Analog bias current Normal operating mode 50 70 100 µA Ipol Analog bias current Shutdown mode 0 µA VINCM Input common mode voltage 0.46 0.57 0.66 V Tmin= -40°C to Tmax= 85°C 1) 0.46 0.66 V 1) Not fully tested over the temperature range. Guaranted by sampling.

AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps, Fin= 1MHz, Vin@ -1.0dBFS, VREFP=1V, VREFM= 0V Tamb = 25°C (unless otherwise specified) POWER CONSUMPTION DIGITAL INPUTS AND OUTPUTS ACCURACY Symbol Parameter Test conditions Min Typ Max Unit ICCA Analog Supply current 1) 15.8 20 mA Tmin= -40°C to Tmax= 85°C 2) 21 mA ICCD Digital Supply Current 1) 1.3 2 mA Tmin= -40°C to Tmax= 85°C 2) 2m A ICCB Digital Buffer Supply Current 1) 2.1 5 mA Tmin= -40°C to Tmax= 85°C 2) 5m A ICCBZ Digital Buffer Supply Current in High Impedance Mode 50 110 µA Pd Power consumption in normal operation mode 1) 48 60 mW Tmin= -40°C to Tmax= 85°C 2) 62 mW PdZ Power consumption in High Impedance mode 43 55 mW Rthja Junction-ambient thermal resis- tor (TQFP48) 80 °C/W Rthjc Junction-case thermal resistor (TQFP48) 18 °C/W 1) Rpol= 18KΩ. Equivalent load: Rload= 470Ω and Cload= 6pF 2) Not fully tested over the temperature range. Guaranted by sampling. Symbol Parameter Test conditions Min Typ Max Unit Digital inputs VIL Logic ”0” voltage 0.8 V VIH Logic ”1” voltage 2.0 V Digital Outputs VOL Logic ”0” voltage Iol=10 µA 0.4 V VOH Logic ”1” voltage Ioh=10 µA 2.4 V IOZ High Impedance leakage current OEB set to VIH -1.5 1.5 µA C L Output Load Capacitance 15 pF Symbol Parameter Test conditions Min Typ Max Unit OE Offset Error mV DNL Differential Non Linearity -0.5 +0.5 LSB INL Integral Non Linearity -1 +1 LSB - Monotonicity and no missing codes Guaranted

AVCC = DVCC = 2.5V, Fs= 40Msps, Vin@ -1.0dBFS, VREFP=1V, VREFM= 0V Tamb = 25°C (unless otherwise specified) DYNAMIC CHARACTERISTICS Symbol Parameter Test conditions Min Typ Max Unit SFDR Spurious Free Dynamic Range Fin= 5MHz Fin= 10MHz 1) Fin= 24MHz 67.7 dBc Fin= 5MHz Fin= 10MHz Fin= 24MHz 59.8 dBc SNR Signal to Noise Ratio Fin= 5MHz Fin= 10MHz 1) Fin= 24MHz 48.8 48.8 48.8 dB Fin= 5MHz Fin= 10MHz Fin= 24MHz dB THD Total Harmonic Distortion Fin= 5MHz Fin= 10MHz Fin= 24MHz 72.5 72.5 dB Fin= 5MHz Fin= 10MHz Fin= 24MHz dB SINAD Signal to Noise and Distortion- Ratio Fin= 5MHz Fin= 10MHz 1) Fin= 24MHz 48.7 48.7 48.7 dB Fin= 5MHz Fin= 10MHz Fin= 24MHz dB ENOB Effective Number of Bits Fin= 5MHz Fin= 10MHz Fin= 24MHz 7.8 7.8 7.8 7.97 7.97 7.96 bits Fin= 5MHz Fin= 10MHz 2) Fin= 24MHz 7.8 7.8 7.8 bits 1) Rpol= 18K Ω. Equivalent load: Rload= 470Ω and Cload= 6pF 2) Tmin= -40°C to Tmax= 85°C. Not fully tested over the temperature range. Guaranted by sampling.

DEFINITIONS OF SPECIFIED PARAMETERS STATIC PARAMETERS Static measurements are performed through method of histograms on a 2MHz input signal, sampled at 40Msps, which is high enough to fully characterize the test frequency response. The input level is +1dBFS to saturate the signal. Differential Non Linearity (DNL) The average deviation of any output code width from the ideal code width of 1LSB. Integral Non linearity (INL) An ideal converter presents a transfer function as being the straight line from the starting code to the ending code. The INL is the deviation for each transition from this ideal curve. DYNAMIC PARAMETERS Dynamic measurements are performed by spectral analysis, applied to an input sinewave of various frequencies and sampled at 40Msps. Spurious Free Dynamic Range (SFDR) The ratio between the amplitude of fundamental tone (signal power) and the power of the worst spurious signal (not always an harmonic) over the full Nyquist band. It is expressed in dBc. Total Harmonic Distortion (THD) The ratio of the rms sum of the first five harmonic distortion components to the rms value of the fundamental line. It is expressed in dB. Signal to Noise Ratio (SNR) The ratio of the rms value of the fundamental component to the rms sum of all other spectral components in the Nyquist band (f s/2)excluding DC, fundamental and the first five harmonics. SNR is reported in dB. Signal to Noise and Distorsion Ratio (SINAD) Similar ratio as for SNR but including the harmonic distortion components in the noise figure (not DC signal). It is expressed in dB. From the SINAD, the Effective Number of Bits (ENOB) can easily be deduced using the formula: SINAD= 6.02× ENOB + 1.76 dB. When the applied signal is not Full Scale (FS), but has an A 0 amplitude, the SINAD expression becomes: SINAD= 6.02× ENOB + 1.76 dB + 20 log (2A0/FS) The ENOB is expressed in bits. Analog Input Bandwidth The maximum analog input frequency at which the spectral response of a full power signal is reduced by 3dB. Higher values can be achieved with smaller input levels. Effective Resolution Bandwidth (ERB) The band of input signal frequencies that the ADC is intended to convert without loosing linearity i.e. the maximum analog input frequency at which the SINAD is decreased by 3dB or the ENOB by 1/2 bit. Pipeline delay Delay between time when the analog input is initially sampled and time when the corresponding digital data output is valid on the output bus. Also called data latency. It is expressed as a number of clock cycles.

Static parameter: Integral Non Linearity Fs=40MSPS; Fin=1MHz; Icca=11mA; N=65536pts Static parameter: Differential Non Linearity Fs=40MSPS; Fin=1MHz; Icca=11mA; N=65536pts Linearity vs. AVcc Fs=40MSPS; Icca=11mA; Fin=1MHz Distortion vs. AVcc Fs=40MSPS; Icca=11mA; Fin=1MHz -0 .1 5 -0.1 -0 .0 5 0.05 0. 1 0 50 100 150 200 250 Output Code INL (LSBs) -0 .1 -0.08 -0.06 -0.04 -0.02 0. 02 0. 04 0. 06 0. 08 0 50 100 150 200 250 Output Code DNL (LSBs) -70 -69.5 -69 -68.5 -68 -67.5 -67 AVCC (V) Dynamic Parameters(dB) SFDR THD 48.6 48.7 48.8 48.9 49.1 49.2 49.3 49.4 AVCC (V) Dynamic parameters (dB) 7.95 7.955 7.96 7.965 7.97 7.975 7.98 7.985 7.99 7.995 ENOB (bits) SINAD ENOB SNR

Linearity vs. DVcc Fs=40MSPS; Icca=11mA; Fin=1MHz Linearity vs. VccB Fs=40MSPS; Icca=11mA; Fin=1MHz Linearity vs. Fs Icca=11mA; Fin=5MHz Distortion vs. DVcc Fs=40MSPS; Icca=11mA; Fin=1MHz Distortion vs. VccB Fs=40MSPS; Icca=11mA; Fin=1MHz Distortion vs. Fs Icca=11mA; Fin=5MHz 48.5 48.7 48.9 49.1 49.3 49.5 49.7 49.9 DVCC (V) Dynamic parameters 7.9 7.91 7.92 7.93 7.94 7.95 7.96 7.97 7.98 7.99 ENOB (bits)SINAD EN0B SNR 49.1 49.2 49.3 49.4 49.5 49.6 49.7 49.8 49.9 VCCB (V) Dynamic parameters (dB) 7.9 7.91 7.92 7.93 7.94 7.95 7.96 7.97 7.98 7.99 ENOB (bits) SINAD ENOB SNR 47.5 48.5 49.5 50.5 51.5 20 30 40 50 60 Fs (MHz) Dynamic parameters (dB) 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 ENOB (bits) ENOB SNR SINAD -75 -73 -71 -69 -67 -65 -63 -61 DVCC (V) Dynamic parameters (dB) SFDR THD -75 -74 -73 -72 -71 -70 -69 -68 -67 -66 -65 VCCB (V) Dynamic parameters (dB) THD SFDR -80 -75 -70 -65 -60 -55 -50 20 30 40 50 60 Fs (MHz) Dynamic parameters (dB) THD SFDR

Linearity vs. Fs Icca=11mA; Fin=15MHz Linearity vs. Fin Fs=40MSPS; Icca=11mA Linearity vs. Temperature Fs=40MSPS; Icca=11mA; Fin=5MHz Distortion vs. Fs Icca=11mA; Fin=15MHz Distortion vs. Fin Fs=40MSPS; Icca=11mA Distortion vs. Temperature Fs=40MSPS; Icca=11mA; Fin=5MHz; -85 -80 -75 -70 -65 -60 -55 -50 20 30 40 50 60 Fs (MHz) Dynamic parameters (dB) THD SFDR 48.4 48.6 48.8 49.2 49.4 49.6 49.8 0 2 04 06 0 Fin (MHz) Dynamic parameters (dB) 7.7 7.75 7.8 7.85 7.9 7.95 ENOB (bits) ENOB SNR SINAD 48.2 48.4 48.6 48.8 49.2 49.4 49.6 49.8 -50 0 50 100 Temperature (°C) Dynamic Parameters(dB) 7.8 7.85 7.9 7.95 SINAD ENOB SNR 20 30 40 50 60 Fs (MHz) Dynamic parameters (dB) 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 ENOB (bits) ENOB SNR SINAD -75 -70 -65 -60 -55 -50 0 2 04 06 0 Fin (MHz) Dynamic parameters (dB) TH D SFDR -50 0 50 100 Temperature (°C) Dynamic Parameters(dB) SFDR TH D

Fs=40MSPS - Icca=11mA - Fin=1MHz Power spectrum Fs=40MSPS - Icca=11mA - Fin=10MHz Power spectrum Fs=40MHz - Icca=11mA - Fin=50MSPS Frequency (MHz) 02468 10 12 14 16 18 -20 -40 -60 -80 -100 Power spectrum (dBm) Frequency (MHz) 02468 10 12 14 16 18 -20 -40 -60 -80 -100 Power spectrum (dBm) Frequency (MHz) 02468 10 12 14 16 18 -20 -40 -60 -80 -100 Power spectrum (dBm)

The TSA0801 is a High Speed analog to digital converter based on a pipeline architecture and the latest deep submicron CMOS process to achieve the best performances in terms of linearity and power consumption. The pipeline structure consists of 9 internal con- version stages in which the analog signal is fed and sequentially converted into digital data. Each 8 first stages consists of an Analog to Digital converter, a Digital to Analog converter, a Sample and Hold and a gain of 2 amplifier. A 1.5bit conver- sion resolution is achieved in each stage. The lat- est stage simply is a comparator. Each resulting LSB-MSB couple is then time shifted to recover from the conversion delay. Digital data correction completes the processing by recovering from the redundancy of the (LSB-MSB) couple for each stage. The corrected data are outputted through the digital buffers. Signal input is sampled on the rising edge of the clock while digital outputs are delivered on the fall- ing edge of the Data Ready signal. The advantages of such a converter reside in the combination of pipeline architecture and the most advanced technologies. The highest dynamic per- formances are achieved while consumption re- mains at the lowest level. Some functionalities have been added in order to simplify as much as possible the application board. These operational modes are described in the following table. The TSA0801 is pin to pin compatible with the 10bits/25Msps TSA1001, the 10bits/50Msps TSA1002 and the 12bits/50Msps TSA1201. This ensures a conformity within the product family and above all, an easy upgrade of the application. OPERATIONAL MODES DESCRIPTION Data Format Select (DFSB) When set to low level (VIL), the digital input DFSB provides a two’s complement digital output MSB. This can be of interest when performing some fur- ther signal processing. When set to high level (VIH), DFSB provides a standard binary output coding. Output Enable (OEB) When set to low level (VIL), all digital outputs remain active and are in low impedance state. When set to high level (VIH), all digital outputs buffers are in high impedance state. This results in lower consumption while the converter goes on sampling. When OEB is set to low level again, the data is then valid on the output with a very short Ton delay. The timing diagram summarizes this operating cycle. Out of Range (OR) This function is implemented on the output stage in order to set up an ”Out of Range” flag whenever the digital data is over the full scale range. Typically, there is a detection of all the data being at ’0’ or all the data being at ’1’. This ends up with an output signal OR which is in low level state (VOL) when the data stay within the range, or in high level state (VOH) when the data are out of the range. Inputs Outputs Analog input differential level DFSB OEB OR DR Most Significant Bit (MSB) (VIN-VINB) > RANGE H L H CLK D9 -RANGE > (VIN-VINB) H L H CLK D9 RANGE> (VIN-VINB) >-RANGE H L L CLK D9 (VIN-VINB) > RANGE L L H CLK Complemented D9 -RANGE > (VIN-VINB) L L H CLK Complemented D9 RANGE> (VIN-VINB) >-RANGE L L L CLK Complemented D9 XX H H Z H Z H Z

Figure 10 :TSA0801 evaluation board schematic Vin 100pF 330pF 470nF 10nF 330pF 10nF 470nF 330pF 10nF C10 470nF C11 330pF C12 10nF C13 470nF C14 330pF C15 10nF C16 470nF Raj1 47K C17 330pF C18 10nF C19 470nF CLJ/SMB C24 10µ OEB1 D02 D13 D24 D35 D46 D57 D68 D79 GND10 LE 11 Q0 19 Q1 18 Q2 17 Q3 16 Q4 15 Q5 14 Q6 13 Q7 12 VCC 20 74LCX573 OEB1 D02 D13 D24 D35 D46 D57 D68 D79 GND10 LE 11 Q0 19 Q1 18 Q2 17 Q3 16 Q4 15 Q5 14 Q6 13 Q7 12 VCC 20 74LCX573 R10 47K R11 47K R12 47K R14 47K R15 47K C25 330pF C27 10nF C28 470nF C29 10µ F DO D10 D11 D12 R13 47K C30 330pF C31 10nF C32 470nF J12 AVCC J17 VDDBUFF3V J18 VccB1 C34 47µ C35 47µ VrefP VrefM Regl com mode Mes com Mode AVCC AVCC VCCB1 VCCB 1 DFSB J10 OEB J11 J13 C26 330pF C39 10nF C37 470nF VCCB2 C33 330pF C40 10nF C38 470nF D13 J19 AGND J20 DGND J21 GndB2 J22 GndB1 C41 10µ F + C42 47µ F Ipol1 VrefP2 VrefM3 AGND4 Vin5 AGND6 VINB7 AGND8 INCM9 AGND10 AVCC11 AVCC12 DVCC 13 DVCC 14 DGND 15 CL K 16 DGND 17 NC 18 DGND 19 GNDBUFF20 GNDBUFF21 2.5VCC BUFF22 OR 23 D13 24 D12 25D11 26D10 27D9 28D8 29D7 30D6 31D5 32D4 33D3 34D2 35D1 36 D037 DR38 2.5VCCBU FF39 GNDBUFF40 2.5VCCBU FF41 NC42 NC43 OEB44 DFSB45 AVCC46 AVCC47 AGND48 8-14bits ADC TSA0801 OR R16 47K R17 47K R18 47K R19 47K DR 1 32PIN J16 CON2 C20 330pF C21 10nF C22 470nF C23 10µ 1 J15 DVCC + C36 47µ 4 3 T2-AT1-1WT 6T2 T2-AT1-1WT

Figure 11 :circuit board - Top side silkscreen Printed circuit board - List of components Par t Des ig n Footp r i n t Par t Desi g n Foot p r i nt P a r t Des ig n Footp r i n t P a r t Des i g n Footp r i nt Type ator Ty p e ato r Ty p e ator Ty p e ato r 10 u F C 2 4 1210 330pF C33 603 470nF C7 805 A VCC J1 2 F I CHE2M M 10 u F C 2 3 1210 330pF C20 603 470nF C1 6 805 C LJ/SM B J4 SM B /H 10 u F C 4 1 1210 330pF C8 603 470nF C1 9 805 A GND J1 9 F I CHE2M M 10 u F C 2 9 1210 330pF C2 603 470nF C3 805 D FSB J9 F I CHE2M M 1 00pF C1 603 330pF C5 603 47 K Ω R1 2 603 D GND J20 F I CHE2M M 1 0nF C1 2 603 330pF C1 1 603 47 K Ω R1 4 603 D VCC J1 5 F I CHE2M M 1 0nF C39 603 330pF C30 603 47 K Ω R1 1 603 Gn d B1 J 22 FI CHE2MM 1 0nF C1 5 603 330pF C1 7 603 47 K Ω R a j1 VR 5 G ndB 2 J2 1 F IC H E 2 M M 1 0nF C40 603 330pF C1 4 603 47 K Ω R1 0 603 M e s com mod e J 8 FI CHE2MM 1 0nF C27 603 47 uF C36 CAP 47 K Ω R1 9 603 OE B J 1 0 FI CHE2MM 1 0nF C4 603 47 uF C34 CAP 47 K Ω R1 3 603 R egl com mode J7 F I CHE2M M 1 0nF C21 603 47 uF C35 CAP 47 K Ω R1 5 603 T2 - AT1 - 1 WT T2 ADT 1 0nF C31 603 47 uF C42 CAP 47 K Ω R1 6 603 T2 - AT1 - 1 WT T1 ADT 1 0nF C6 603 470nF C22 805 47 K Ω R1 7 603 VccB1 J1 8 F I CHE2M M 1 0nF C9 603 470nF C32 805 47 K Ω R1 8 603 VDDBU FF3V J 1 7 FI CHE2MM 1 0nF C1 8 603 470nF C37 805 50 Ω R3 603 Vi n J1 SM B /H 1K Ω R2 603 470nF C38 805 50 Ω R1 603 VrefM J5 F I CHE2M M 32P I N J6 I DC32 470nF C1 3 805 74LCX573 U3 TSSOP 20 VrefP J2 F I CHE2M M 330pF C25 603 470nF C28 805 74LCX573 U2 TSSOP 20 T SA0801 U1 T QF P 48 330pF C26 603 470nF C1 0 805 C ON2 J1 6 SIP 2

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Dim. Millimeters Inches A 1.60 0.063 A1 0.05 0.15 0.002 0.006 C 0.09 0.20 0.004 0.008 D 9.00 0.354 D1 7.00 0.276 D3 5.50 0.216 e 0.50 0.0197 E 9.00 0.354 E1 7.00 0.276 E3 5.50 0.216 L1 1.00 0.039 K0 ° (min.), 7° (max.) 48 37 e 13 24 12 25 c A D EL K 0,25 mm .010 inch GAGE PLANE 0,10 mm .004 inch SEATING PLANE B