TS7515CP

STMicroelectronics

SINGLE CHIP DPSK AND FSK MODEM Jun-1995

Manufacturer: STMicroelectronics

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/, MICROELECTRONICS TS7515 ETS SINGLE CHIP DPSK AND FSK MODEM ee OT eae MONOLITHIC DEVICE (INCLUDES BOTH — *Overspeed selection in character asynchro- TRANSMIT AND RECEIVE FILTERS) nous format mode " MIXING ANALOG AND DIGITAL TECHNICS * Scrambler selection "STANDARD LOW COST CRYSTAL _= 1800Hz guard tone selection in V.22 (4.9152MHz) * Test loop selection (Digital/Analog) "AVAILABLE CLOCK FOR MICROPROCES- SOR AT 4.9152MHz * LOW POWER DISSIPATION > (CMOS technology) : See il \\ "= SHARP ADJACENT CHANNEL REJECTION Real iy) "FIXED COMPROMIZE EQUALIZATION IN a WwW TRANSMITTER AND RECEIVER "TEST LOOPS (local analog, local digital and pips remote digital loopbacks) (Plastic Package) * CARRIER DETECTION OUTPUT "= CCITT AND BELL SIGNALING TONE ; = 1200BPS AND 600BPS BIT SYNCHRONOUS — ORDERING INFORMATION FORMAT IN DPSK Temperati "1200BPS AND 600BPS +1%, -2.5% OR Part Number | Range | Package +2.3%, -2.5% CHARACTER ASYNCHRO- | Ts7st6Gp 0104700 Dips __|f NOUS FORMAT (8, 9, 10 or 11 bits) IN DPSK 2516 s050 pipes] "0 TO 300BPS IN FSK s . * AUTOMATIC DIAL LINE MONITORING CAPA piw CONNECTIONS " BREAK SIGNAL SUPERVISION ay, "EXTERNAL VOICE BAND TONE FILTERING ve 28 |] xraL our AVAILABLE (i.e. 550Hz or DTMF) wie fe 27 [7] tain "= CMOS AND TTL COMPATIBLE a = DIRECT INTERFACE TO STANDARD MICRO- eee ae | J cux PROCESSOR FAMILIES ws (4 25 [| txscix DESCRIPTION nas a4) ox ‘The TS7515 is a single chip DPSK and FSK voice- ose [fe 23} J x0 band modem, compatible with the BELL 103, 2124 sas (]7 22] | Ris and CCITT V.22 A/B recommended standards. ro [a ahs MAIN OPERATING MODES pyc [} 9 20 |] Gnp " Standard selection (Bell 212A/Bell 103/V.22) test (] 10 19 [| No = Answer tone selection (2100 or 2225Hz) bop 4 18 LJ] RA = Low speed mode selection * Channel selection (answer/originate) as C12 7 Pex = Synchronous/asynchronous mode selection Ro [J 13 16 [_] ato 8 bits to 11 bits word length selection in char- nro [| 14 spv. I acter asynchronous format mode H June 1995 W14 ee @™ 7929237 0063163 6T2 508

wane [Fm] [Fame | tuetton | ; COMMON SECTION (supply, clock, handshaking and mode selection) ve [1 [1 | Positive PowerSupy [sV [v= [1 [45 | Negative Power Suppy [SV This pin corresponds to the input of the oscillator. It is normally XIN 7 Oscillator In connected fo an external crystal but may also be connected to a il put pulse, ganerator. ‘The nominal frequency of the oscillator is 4.9152MH2. __ __ | This pin corresponds to the output of an inverter with sufficient I XOUT Lo | 28 | _Osellator Output __| Gain fo stat and maintain the erystaloscaing. eer This pin delivers a clock signal, the frequency of which isthe crystal cuk | 0 | 26 Clock iTequency. may be used as a bufered dock a microcontroler. | ce | | 3. | CCITTBELL Selection This. three: State input selects the features corresponding to CCITT . ‘This three-state input selects the synchronous bit format or the 4 pay anon US ion | a8yfichronous character format mode in DPSK transmission. This yn input allows also character length selection (refer to table 8). This input selects the character length in conjunction with A/S input cis [| 12 Character Length | (eter to table 8). “on | This input selects the over-epeedin asynchronous character format | ose | 1 | | Over-speed Selection | Togs fequirod by COTTT revommandation (refer to table 8). ‘A Logic*0" on this input turns chip on1200 bps sate. A logic "1" tums BRS 7 _| Binary Rate Selection | the chip on 600bps or 0-300bps onarding CB selection. - , “on | A logic °0" on this input turns the chip on answer mode. A logic "1" nO 19 | Answer/Orig, Selection | tums the chip on originate mode. [_7c_[ 1 | 5 | TestLoop Selection _| This three-state input, selects the test loops mode (refer to table 6). ‘TRANSMIT SECTION Data bits to be transmitted are serially presented on, this input. A xD 23 ‘Transmit Data _ | Matk corresponds toa logic "1" and a space toa logic". This data x determines which phase or frequency appears at any instant at the _| ATO pin in DPSK or FSK modes. “The analog output is the modulated carrier or the answer tone tobe ATO 16 | Analog Transm | conaitionned ‘ahd sent over the phone line mixed withthe fitered _ | put | signal from EX This analog input allows external tone to be fitered by an internal beta [| 17 | External Tone Input _| (Quepasa Aor Perea signal appears at ATO whatever BTS. — ‘A logic "0" on this inputinstructs the chip to enter answer ‘signaling RE ‘Answer Tone Enable | tone mode according C/B selection. A logic "1" tums the chip on tranemit data mode Geter to fable 8). sa Scrambler Enable | A logic *0" on this input enables the intemal sorambler. | input | Alogic “1” instructs the chip to bypass the scrambler. ; This output delivers a transmit bit clock generated by chip in | TxCLK Transmit Clock 1S OL oe nes TROCLK i used TROLK Is ocked on TXSCLK. This output generates a logic “1” in asynchronous mode. , This input receives a bit clock supplied by the DTE. This clock TxSCLK Transmit Clock | synchronizes the internal *Faneeh clock of the chip. In ine - monitoring mode this input receives the fiters clock. / When a logic 0" is present on this input, the chip delivers on ATO | Hiren oo consis signaling one and the tered signa rom | we ze | aquesttogend | EX! When a loge tig prant on fas nput, ATO delivers oly ‘erminal the filtered signal from EX! lie ara a oe tao input the receive section may be used for line monitoring and ATO delivers only the ftered signal trom EX. 24 1 ——— 510 M@™@ 792923? OOb31b4 735

PIN DESCRIPTION (continued) [mee AB | ree [ed RECEIVE SECTION iT This analog Sutput is the signal yeceived on Bal once filtered, we | iy receive filter also. izes the sic ir adaptation to most existing RFO 14 | Receive Filter Output | tings, This outputs Be connectod ADI through Capactor to | Receive Demodulator | This pin is the input of the carrier detection logic and of the ROI 13 Input demodulator — | | A logic *0* on this output indicates that a valid carrier signal is DbcD | Oo W Data Carrier Detect present on RAl. A logic "1" means that no valid signal is being | | received. The hysteresis meet standards recommendation. | RxD | 0 | 8 | Receive Data | Data bits demodulated are available seraly at this output. ‘| . This output delivers a receive bit clock generated Py. the chip. In RxCLK | O 9) Receive Clock asynchronous mode this clock is 16 times the modulation rate. in synchronous mode the clock is equal to the bit rate. é This output is an intermediate demodulator output intended for rest | 0 | w | ret [tpn OOM oo noo | 2 The TS7515 is a general purpose monolithic DPSK - Bell 212A with its low speed mode and FSK modem implemented with double poly —- Bell 103 CMOS process, Allfitering functions required for frequency genera- It is capable of generating and receiving phase tion, out-of-band noise rejection and demodulation modulated signals at data rates of 1200bps or are performed by on-chip switched capacitor filers, 600bps as well as frequency modulated signals at ; data rates up to 300bps on Voice-grade telephone _In phase modulation the modem provides all data lines. buffering and scrambling functions necessary for ; z . bit synchronous format and asynchronous charac- It is offered in a 28 or 44 in plastic package and is able to operate in full-duplex mode according to _*ef format modes of operation. ‘three pin selectable standards : Internal frequencies are generated from a - CCITT V.22 A-B 4.9152MHz crystal reference. $cs- ana Mi 7929237 0063165 675 a sn

“ASYNCHRONOUS 7 couPrOMise Eaiauetton StGNAL NE ONE GENERATOR TScLk p25} RECEIVE FILTER {is} RAL noah — Sa be necovery recovery [* | USS" mere ——_| i _ {i}—ave xraLin@ Pa 2 | CONTROL AND MODE SELECTION a—aNo mace eos] [___commamoncorsnacron ae | om

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cu AIS ors AO Th ATE Ge As cs Ose i ABSOLUTE MAXIMUM RATINGS _ [[Symbot [Parameter Vatu Tit] Supply Votage ‘Supply Voltage Vn | Analoginput Vi <Vn<V* v _M Digital Input (except three-state inputs) GND<V,<V* v Tam | Operating Temperature 01070 ‘Storage Temperature 55, 125 ' in Temperature (soldering, 10s) [00 ee ‘Szesses above thos listed under “Aboolute maximum ratings’ may cause permanent damage tothe device. This eess rating only and fonctonal operation af the device at these ‘or any other concittons for extended panods nay afeet coves: ‘reliability. Standard Gira handing procedures should be employed to avoid possible damage to device. — ITA $GS-THOMSON —— ooo 512 mm 7929237 OOb31bb SOL

ELECTRICAL OPERATING CHARACTERISTICS | Svmbot [Parametor in. Typ. [Max | Unit v= | Postve Sup Voage ; [az [5 [525] v_| Negative Supply Voltage r V™ Operating Current 7 [| = | m ]? D.C. AND OPERATING CHARACTERISTICS Ta =0°C to +70°C, V* = +5V 45%, V = -5V 45%, GND = OV DIGITAL INTERFACE [k [Input Current (Varnin < Vi < Vw max) so [| - | HA [le _| Output Low Level Current (Vo. = 0.4V) 800 [= | HA [tor | Output High Level Curent Vor=24yy SY WA [Vu _[inputtowVotage NO | = os | | [__Wa | tnputFighVotege ee ve L__va _[inputNegatveVotage TT a | ANALOG INTERFACE, FILTERS INPUTS AND OUTPUTS (RAL-RFO, EXI-ATO) [| inputioakage Curent CaVeVwerayy to T= [0 Ta | [__Fi__[inputResistance TT | | Vn__[inputVotage Swing | Vor | OutputOfisetVotiage | 500 [=| 500 [mv Output Voltage Swing (Ri > 10k) _ Sr ©, | Lead Capacitance | - [=| 20 | oF Load Resistance a ANALOG INTERFACE, TRANSMIT OUTPUT (ATO) EX! CONNECTED TO GND Oulu Get Vonage — 0 [emo mv | ve | ‘Output Voltage Swing (RUT0KQ, C. = 20pF) lel | Vo > Carriers y, ~ Guard Tone 1800H2/Data Signal 7 eB FS Atenution TPs =e ANALOG INTERFACE, RECEIVE DEMODULATOR INPUT (RDI) [_ Glink ** | Serial Capacitor trom AFO # te] |__| Maximum Detection Levelto Val DOD Output T= || 85 _| Vas | _N2__| minimum Detection Level to Valid DCD Output fat f= =| mvs | 1 Typical values are fr Tan = 25°C and nominal power supply valuos. ‘capacitor must be unpolarized type capacitor mm 7929237 O0b31b7 44d 513

RECEIVE FILTER TRANSFER CHARACTERISTICS IN DSPK [symbol [Parameter |i, | Typ.* | Max. | Unit] Low Channel GA__[ Absolute PassbandGainat: SS T200Hz | - [vos | | a8 | Relative Gain to GA at eooHz| — | 45 | - | oB gooz | = | os | - | 08 l a 2aoorz | = [65 _| | | High Channel GA__| Absolute PassbandGainat: - zaooHz| — | +05 | - | B | Relative Gain to GA at : 2100Hz [02 [| «8 | GR zroonz | | 407 | = | a8 | wwoot as [= et | teooiiz | =| [= | 8 8 RECEIVE FILTER TRANSFER CHARACTERISTICS IN FSK In FSK the receive filter is the same as in DSPK but the sampling frequency is multiplied be a 14/15 ra- tio (,e. 2400Hz in DSPK becomes 2240Hz in FSK). (Symbol [Carmenere i in [Ty | Max | Ui | Low Channel GA__| Absolute Passband Gain at : 120Hz| - | 95 - | #8] High Channel é GA [Absowe Passband Gamat: ———SCSCS~S~SRT = [ws | YE * Typical values are for Tere = 25°C and nominal power supply values. DEVICE OPERATION Transmitter ted is converted into two 300 dibits per second The transmitter consists of two analog signal gen- streams which modulate alternatively two inde- erators followed by switched capacitorandcontinu- Pendant carriers. Consequently the base band cousfilters. In phase modulation operationmodethe Shaping is included is a 5-bit address ROM which DPSK signal generators preceded by aselectable generates samples for a 8-bit switched capacitor scrambler and an asynchronous to synchronous DAC at a frequency equals to 8 times the carrier converter is included in character asynchronous —_—frequency. format mode. Table 1: DPSK Modulation Tone allocation : the modem on the end of the line = which initiates the call is called the originate mo- prs [|__| dem. In normal transmission operation it transmits | [aca [a] Phase Shift in low channel and receives in high channel. The other modem is the answer modem which trans- cs ee ce mits in high channel and receives in low channel. i a = DPSK modulator : the phase modulation type is | + | x: 2 490° differential quadrature four phase shift keying (see 1 4270" Table 1). The 1200bps data stream to be transmit-* x: don't care. eng ss-tHomson 514 (m™™ 7929237 OOb31b8 384 a

FKS modulator and tone generator: frequency _out of lock on certain continuous repetitious data synthesizer provides accurate clocks toa switched pattems. capacitor sine wave generator (see Table2).Phase This scrambler may be disabled during handshak- continuity is maintained when a frequency shift ing procedures. In V.22 a special unlocking se- ocours, quence is performed on 64 spaces pattem at Table 2 : FSK Modulation (BELL 103) scrambler output. Ao ae Standard paenc Asynchronous To Synchronous Converter oo | O2SHe The DPSK signal is synchronous in nature but the [i | 2ea6Hz | modem has both an asynchronous as well as a [oo | 1070H2 synchronous mode of operation in DPSK. Soa data | 1270Hz buffer is necessary to convert variable rate asyn- chronous character data to an equivalent bit ori- Transmit Filters ented synchronous data stream. This is done by inserting or deleting stop bits. If serial input data toed eae reopen tah, be contains a break signal through one character (in- maintain the level of spurious out-of-band signals Uding dioatleast? Me abe brake Ne transmitted to the telephone line below the limits the number of teneritied biveharacten). re Ni specified by administrations (see figure 1) and to ° Complete statistical amplitude and phase equaliza- Figure 1 : Transmitted Signal Template tion, the analog signals are processed by ten poles sharp pass-band switched capacitor filters. The =m response of these filters depends on the selected channel (Answer/Originate) and the selected ° standard (BELL 212 - V.22 BELL 103). Acontinuous filter eliminates parasitic sampling effects. An addi- | tional low-pass filter input is provided. This allows to mix and filter such tones as DTMF signals or —_| 23 | special guard tones (550Hz) to the transmitted — | 27 - signal. Seeing Scrambler | || The scrambler used during phase modulation en- [#0 J s sures the transmission of a continuously changing ver) se 8 pattern. This avoids the receiving modem to drop tert) | Table 3 : Output Frequency Deviation ‘Standard Frequer ! ‘% Deviation vena: om Sunde Moe 1070H2 1066.7Hz 0.3% BELL 103 Originate _ 1200Hz 1200Hz BELL 212A or V22, Originate | —teroviz | eats | as [BELL 103 Ornate Guard Tone V.22 [_2oastig | aoettiz | 02% | Bet toa Answer SSCS 2225H2 2226.1Hz 40.05% 2400Hz 2400Hz tt BELL 212A or V.22, Answer Se er sisstomson WM 7929237 0063169 210 515

RECEIVER FSK demodulator : the zero crossing detector The receiver includes two band-pass filters fol: output is passed through a shift register whose lowed by an amplifier and a hard limiter. Depending 'ength depends on the operating mode (An- ‘onselected standard, the detector outputis passed sWer/Originate). The output of the shift register and through a DPSK demodulator ora FSK demodula- __the detector are mixed into an exlusive Or. Then tor. The DPSK demodulator is followed by a de- _they are processed through a four poles Bessel scrambler and a selectable synchronous to __ filter and a slicer. asynchronous converter. In addition a carrier de- tector monitors the level of the received signal. Test Output Tone allocation : in normal transmission operation Once demodulated DPSK data are generally proc- the originate modem receives in high channel and —_ essed (cf next paragraph) but during call set-up transmits in low channel. The answer modem re- procedures or data set testing itis of importante to ceives in low channel and transmits in high channel. monitor the demodulator output. So in DPSK mode demodulated data are available on TEST pin. Receive Filters The signal delivered by the hybrid to the receive Descrambler and Synchronous to analog input is a mixture of transmitted signal, | ASynchronous Converter received signal and noise with a level in the range Data coming from the DPSK demodulator are un- from ~48dBm to -OdBm. Depending on the operat- scrambled. In V.22 the unlocking sequence is de- | ing mode and the selected standard the 20 poles _tected at descrambler input and the original data receive switched capacitor band-pass filter selects are decoded before descrambling. In asynchro- ‘the frequency band of the low channel or the high nous character format mode of operation a data channel. A ratio of 14/15 is applied on the sampling _bufferis able to detect missing stop bits and reinsert clock frequency between FSK and DPSK in the them. The converter is able to recognize the break same operating mode (Answer/Originate). These _signal and transmits it without modification. filter reject out-of-band transmission noise compo- nents and undesirable adjacent channel echo sig- Carrier Detector nals which can be fed from the transmit section into ~~ Whenever valid signals are being received at the the receive section. Fixed equalization is included —_input of the demodulator and are acceptable for in order to assure low error rate. demodulation, carrier detect output is pulled down. A delay is timed out before the carrier received or Amplifier And Hard Limiter carrier lost signal changes carrier detect output to Once filtered the received signal is amplified and _ provide immunity against noise bursts. The modem fed to the carrier detector. In order to limit analog also provides at least 2dB of hysteresis between parts in the design all the demodulator techniques __ the carrier ON and the carrier OFF thresholds (see used in the TS7515 are based on zero crossing Figure 2). detection. So the received signal is just limited before entering demodulator. Figure 2 Demodulators e4ene DPSK demodulator : a DPLL is used to recover ~ the carrier signal. This DPLL has a lock range of . ] +2Hz but as the incoming carrier may present an af | HM I Ninn “ offset of 7Hz a second loop allows the first DPLL_ |" “if mA to lock on the exact frequency of the carrier with an. | | | | | accuracy of +1Hz and to follow its slow variations 1 in 1200 bands mode only. Thenthe limited received a signal is mixed through exclusive-Or with the recov- cy ered carrier and with the 90 degrees phase shifted recovered carrier. The results are processed through four poles Bessel filters wich provide a good amplitude propagation time compromise. The [..| received sampling clock recovered from these base and data with a simple DPLL. The received : data are sampled by this clock and then converted in ppsk mode 105ms <ty <205ms, 10ms <te<24ms into a serial synchronous bit stream. In PSK mode 105ms <t, ¢205ms. 25ms <te = 75ms Bn4 516 mm 792923? 0063170 T32

LOOP TEST Oscillator Output Loop 3 The buffered master clock (4.9152MHz) is made This loop is called the analog loop. When it is _aVailable at output CLK. It can be used as a clock selected the receive filters and the modulators are for a microcontroller. configured to process the same channel as the transmit section. The transmit carrier has to be Voltage Reference looped back externally to the receive analog input. A temperature compensated voltage reference This loop allows the user or the DTE to check the build with a zener is included in the chip. This satisfactory working of the local DCE. vol-tage is used to calibrate transmit levels and to generate the carrier detection thresholds. Loop 2 This loop is called the digital loop. When it is selected received data, receive clock and data LINEMONITORING = ; carrier detect signals are respectively and internally Aspecial mode has been included in the TS7515 looped back on transmit data, transmit clock from t© monitor the line during an automatic call. When terminal and request to send. This loop allows the _this mode is selected (A/S = 0, RTS = -1) receive user or the DTE to check the satisfactory working __ filters clock is directly derived from TxSCLK which of the line and the remote DCE. allows the user to precisely observe broad fre- quency bands. Furthermore the DCD performs a Clocks fast carrier detection equivalent to an envelope detection. As the center frequency of the receive In synchronous mode of operation TxCLK, TxSCLK detect , ecelv and PXCLK are respectively working as the V.24 __ filters is proportional to TxSCLK frequency in this circuits C114, C13 and C15. In asynchronous Mode itis possible to tune the passband according mode of operation RxCLK can be used as baud _© the frequency to be detected (see Table 5). rate clock to synchronize the transmit and the TxSCLK:must be created from the TS7515 master receive sections of a UART (see table 4). lock (4.9152MHz). Table 4 : Clock Operation RxCLK _ Mode 4 0 rake ze oo [4 9.6Ktz Asynchronous | o | BELL 212A J+ FES [4 [aan] | Asynchronous and BELL 103 | o | | r200rtz | “t20082 | v.22 1 | e00H2 | 6ooH2 | Synchronous Pe ee ee BELL 212A 1 [4 [ants] |_ Synchronous and BELL 103 * Table 5 TxSCLK Center Passband Center Passband Application Frequency | at 3dB Frequency | _ at 3dB 7 210kKHz 2400Hz __+400Hz 1200Hz +400Hz Voice Detection a5kit2 _——DloHe _#85Hz | 440Hz Detection i 260Hz +85Hz 330Hz Detection Dial Tone and Bu: oe 5-1 od mm 792923? 0063171 975 mm 7

APPLICATION INFORMATION

In a typical application a microcontroller provides __ direct. Ground loops should be avoided. control and interface to the Data Terminal Equip- Coupling between analog inputs and digital lines ment (DTE), and a Direct Access Arrangement should be minimized by careful layout. The RDI provides connection to the telephone line. Thenthe —_ input (Pin 13) is extremely sensitive to noise. TS7515 can communicate with the most popular © The connection between this point and RFO modems (BELL 103 and BELL 212A) in countries (Pin 14) through a ceramic type capacitor should under BELL standards and popular modems (V.22) _be as short as possible and coupling between this, in countries under CCITT recommendations. connection and digital signals should be minimized by careful layout. Power Supplies Decoupling and Layout Con- siderations Carrier Recovery Loop Power supplies to digital systems may contain high The carrier recovery loop utilizes a digital phase amplitude spikes and other noise. To optimize per- lock loop. Performances of the TS7515 depend formances of the TS7515 operating in close prox- directly on this DPLL which needs to be resetted imity to digital systems, supply and ground noise _before receiving a DPSK carrier. should be minimized. This involves attention to Three ways of resetting the DPLL exist on the power supply design and circuit board layout. TS7515: The power supplies should be bypassed with tan- _- Attrailing edge on DCD. talum or electrolytic capacitors to obtain noise free - Changing FSK mode to DPSK mode or reversely. operation. These capacitors should be located —_- Changing receive channel | close to the TS7515. The electrolytic type capaci- These three ways of resetting the DPLL should be tors should be bypassed with ceramic capacitors —_ used in the software included in the microcontroller for improved high frequency performance. to perform the various set-up procedures and Power supplies connections should be short and —_ handshakes, Figure 3 : Examples V.22-V.25 received signals in Originate mode Line — () ( () —— [2t00Hz]—— [unscrambled marks 2400Hz] (data... ‘DeD J The DPLL is automatically resetted Bell 212A received signals in Originate mode Line — () () ( —— [2225Hz] [scrambled marks 2400Hz] (data... Tt J This transition to "1" is needed to reset the DPLL z TYPICAL PERFORMANCES The typical performances listed below are achieved 300.bps operation with the environment described in the previous 7 BER 10, fora 3 ‘ ae paragraph. Specific DPSK p : . - performances Dynamic range : OdBim to - 45dBm. Phase hits sensitivity © 25degres ~] BER ~ BER performances : Phase Jitter 1 3Sdegree _|< 10° Conditions: Xmit level = - 10dBm, ‘Amplitude hits sensiti : +1008 Rec level = - 25dBm, piu vily i ¢ Message 511 bits on CCETT lines 1, 2, Offset carrier sensitivity: SNR increase < +1dB 3, 4 and CNET lines QN and 3 VHF and 1800Hz guard tone : SNR increase < +2dB US lines C4, C2, and CO. sensitivity 1200 bps operation - Specific FSK performances "BER G0 Terao SN Blas Distortion: los than 5 % Jitter : less than 12% 518 mm 7929237 OOb3172 405

7/1) BELL 212A APPLICATION (synchronous) 9 § AS -¢ i : eo a Boas a 2 g 28 a ral Et yy! sos 8 FORME w j | & FI % & Fis ptossGad ies, Ekeetacs sept) f8HEH=HeHSHSHAHEH ec . T | ~ ;)$ssss al 5 |) e8as | = | life: T i ; | ty ima {HH} {HH —CHH+ sod ii PEESEECE REEPE FE Fy), aad LT] Bo & Lines i WLoeDor Lo La g8 sot) , > Wl Teeeea peezee32" ( , | OH re PULL es | Cl | gL) ES : i fe 2 S48

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V.22 (asynchronous, 10 bits, 1200bps) f—). ASO-4 <8 5335 9 101 = avo 3 5 nate a « aH FH g Po cor ot Gy (> & Ea & 2 Sm ILE g ° Ey saree honor a | e FI S oe o 2 . ik 7 zw lesesisdigei, Eeseeees skh e” HEHeHeHsHsH HEH s+ fZHSHEHEHeHSH=H=Hah ¥ ic | PERE EEE REREEEE BY ade HIS Es Loops WLoeoor Lo ¢8 soF 9 os = eae: gegugga3" i pl) GET I, i a L i aw wv YA Yl : [_ewanao | I ese 8 geg2 8 feng g-gn 520 me 7929237 0063174 688 Ml

‘SELECTION MODE TABLES SYNTHESIS OF DIFFERENT MODES FOR RECEIVE SECTION Table 6 com ca Receive —~S«d;S:*«éMode DPSK Originate Loop 3 oo | __0 | | DSK Answer Loop 2 v2e [1 |_| BPSK Originate Loop 2 | [0 | | DPSK Answer | [1 |_| OPSK Originate i 4 | _0 |_| DPSK Originate Loop 3 | 1 |_| DPSK Answer Loop 3 | 0 |_| DPSK Answer Loop 2 DPSK Originate Loop 2 DPSK Answer BELL 212A <a ‘naling [0° | a [0] FSiAnswer Loop 2 [1 |__| F8k Originate Loop 2 | | o | | Fsk answer H | 1 | [Fskoriginato 3: Jo tteb2: Blac SYNTHESIS OF DIFFERENT MODES FOR TRANSMIT SECTION Table 7 [are | ce | eras [ao | [Transmit | Moe eS ea [2iooHz anger Tone DPSK 1200bps Originate V.22 without ; a Guard Tone 1 i 1 DPSK 600bps Originate o -_ C4 DPSK 1200bps Originate 10nee et 0 | | DPSK600bps Answer Tone 1 DPSK 600bps Originate a . Po fo [eet toe 1 |_1__} | DPSK 1200bps Originate | BELL212A | [0 | | FSK0-300bps Answer £ [4 | __ [SK 0-300bps Originate z Answer : Receive in high channel ‘Onginate : Receive n low channel Wm 7929237 0063175 Sly me 521

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1 550H: small added to the Ex. “sPoatuos Of so are avenabe nBELL icone. All these differences are taken nto consideration inside the TS7515. I SES THOMSON 622 Mm 7929237 0063176 450 me

Product Information

TS7515CP specifications and overview.

Summary

SINGLE CHIP DPSK AND FSK MODEM Jun-1995

Description

SINGLE CHIP DPSK AND FSK MODEM Jun-1995

Source title TS7515CP Datasheet(PDF) - STMicroelectronics

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