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© 2013 Touchstone Semiconductor, Inc. All rights reserved.
FEATURES
Pin-for-pin, 1.5x Faster Upgrade to AD7887 Single-supply Operation: +2.7V to +3.6V INL: ±1LSB One or Two Single-ended Analog Inputs Internal Wide-bandwidth Track-and-Hold Integrated +2.5-V Reference Flexible Power/Throughput-Rate Management 0.85mA at 187.5ksps (Internal VREF ON) 0.7mA at 187.5ksps (Internal VREF OFF) Shutdown-mode Supply Current: 1μA (max) SPI®/QSPI™/MICROWIRE™/DSP-Compatible Serial Interfaces1 Operating Temperature Range: -40ºC to +85ºC 8-pin MSOP Packaging
APPLICATIONS
Instrumentation and Control Systems High-Speed Modems Battery-powered systems: Personal Digital Assistants, Medical Instruments, Mobile Communications 1 SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation
DESCRIPTION
The TS7001 – a pin-for-pin, 1.5x f aster alternate to the AD7887 - is a self-contained, 2 -channel, high- speed, micropower, 12-bit analog -to-digital converter (ADC) that operates from a single +2.7V to +3.6V power supply. The TS7001 is capable of a 187.5-ksps throughput rate with an external 3MHz serial clock and draws 0.85mA supply current. The wideband input track-and-hold acquires signal s in 500 ns and features a single -ended sampling topology. Output data coding is straight binary and the ADC is capable of converting full power signals up to 10 MHz. The ADC also contains an integrated 2.5V reference or the V REF pin can be over driven by an external reference. The TS7001’s provides one or two analog inputs each with an analog input range from 0 to V REF. In two-channel operation, the analog input range is 0V to VDD. Efficient circuit design ensures low power consumption of 2mW (typical) for normal opera tion and 3μW in power-down operation. The TS7001 is fully specified from -40ºC to +8 5ºC and is available in 8-pin MSOP package. A Micropower, 2-channel, 187.5-ksps, Serial-Output 12-bit SAR ADC FUNCTIONAL BLOCK DIAGRAM The Touchstone Semiconductor logo is a registered trademark of Touchstone Semiconductor, Incorporated.
Lead Temperature, Soldering Electrical and thermal stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not implied. Exposure to any absolute maximum rating conditions for extended periods may affect device reliability and lifetime. PACKAGE/ORDERING INFORMATION ORDER NUMBER PART MARKING CARRIER QUANTITY TS7001IM8TP TADF Tube 50 TS7001IM8T Tape & Reel 2500 Lead-free Program: Touchstone Semiconductor supplies only lead-free packaging. Consult Touchstone Semiconductor for products specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
VDD = +2.7V to +3.6V; VREF = 2.5V External/internal reference unless otherwise noted; fSCLK = 3 MHz; TA = TMIN to TMAX, unless otherwise noted. Parameter Limit1 Unit Test Conditions/Comments DYNAMIC PERFORMANCE Signal to Noise + Distortion Ratio (SNR)2 71 dB (typ) fIN = 10 kHz sine wave, fSAMPLE = 187.5ksps Total Harmonic Distortion (THD) −80 dB (typ) fIN = 10 kHz sine wave, fSAMPLE = 187.5ksps Peak Harmonic or Spurious Noise −80 db (typ) fIN = 10 kHz sine wave, fSAMPLE = 187.5ksps Intermodulation Distortion (IMD) Second-Order Terms −80 dB (typ) f1 = 9.983 kHz, f2 = 10.05 kHz, fSAMPLE = 187.5ksps Third-Order Terms −80 dB (typ) f1 = 9.983 kHz, f2 = 10.05 kHz, fSAMPLE = 187.5ksps Channel-to-Channel Isolation −80 dB (typ) fIN = 25 kHz Full-Power Bandwidth 10 MHz (typ) Measured at 3 dB down DC ACCURACY(Any channel) Resolution 12 Bits Integral Nonlinearity ±1 LSB (max) VDD = 3V Differential Nonlinearity ±1 LSB (max) VDD = 3V; Guaranteed no missing codes to 11 bits Offset Error ±4 LSB (max) VDD = 3V, dual-channel mode ±6 LSB (typ) Single-channel mode Offset Error Match 0.5 LSB (max) Gain Error ±2 LSB (typ) Dual-channel mode ±1 LSB (max) Single-channel mode, external reference ±6 LSB (typ) Single-channel mode, internal reference Gain Error Match 2 LSB (max) ANALOG INPUT Input Voltage Range 0 to VREF V Single-channel operation 0 to VDD V Dual-channel operation Leakage Current ±5 μA (max) Input Capacitance 10 pF (typ) REFERENCE INPUT/OUTPUT REFIN Input Voltage Range 2.5/VDD V (min/max) Single-channel/Dual-channel; Functional from 1.2V Input Impedance 10 kΩ (typ) Very high impedance if internal reference is disabled REFOUT Output Voltage 2.488/2.513 V (min/max) Initial accuracy = 0.5% REFOUT Temperature Coefficient 30 ppm/°C (typ) LOGIC INPUTS Input High Voltage, VINH 2.1 V (min) VDD = 2.7V to 3.6V Input Low Voltage, VINL 0.8 V (max) VDD = 2.7V to 3.6V Input Current, IIN ±1 μA (max) Typically 10nA, VIN = 0V or VDD Input Capacitance, CIN 3 10 pF (max) LOGIC OUTPUTS Output High Voltage, VOH VDD − 0.5 V (min) VDD = 2.7V to 3.6V, ISOURCE = 200 μA Output Low Voltage, VOL 0.4 V (max) ISINK = 200 μA Floating-State Leakage Current ±1 μA (max) Floating-State Output Capacitance4 10 pF (max) Output Coding Straight (Natural) Binary CONVERSION RATE Throughput Time 16 SCLK cycles Conversion time plus acquisition time is 187.5ksps, with 3 MHz Clock Track-and-Hold Acquisition Time 1.5 SCLK cycles Conversion Time 14.5 SCLK cycles 4.833 μs (3 MHz Clock)
ELECTRICAL SPECIFICATIONS (continued) VDD = +2.7V to +3.6V; VREF = 2.5V External/internal reference unless otherwise noted; fSCLK = 3 MHz; TA = TMIN to TMAX, unless otherwise noted. Parameter Limit1 Unit Test Conditions/Comments POWER REQUIREMENTS VDD +2.7/+3.6 V (min/max) IDD Normal Mode4 (PM Mode 2) Static 0.6 mA (max) Operational (fSAMPLE = 187.5 ksps) 0.85 mA (typ) Internal reference enabled 0.7 mA (typ) Internal reference disabled Using Standby Mode (PM Mode 4) 0.45 mA (typ) fSAMPLE = 50 ksps Using Shutdown Mode (PM Modes 1 and 3) 0.12 mA (typ) fSAMPLE = 10 ksps 0.012 mA (typ) fSAMPLE = 1 ksps Standby Mode5 0.21 mA (max) VDD = 2.7V to 3.6V Shutdown Mode5 1 μA (max) VDD = 2.7V to 3.6V Normal Mode Power Dissipation 2.1 mW (max) VDD = 3 V Shutdown Power Dissipation 3 μW (max) VDD = 3 V Standby Power Dissipation 0.63 mW (max) VDD = 3 V Note 1: The TS7001’s temperature range is –40°C to +85°C. Note 2: SNR calculation includes distortion and noise components. Note 3: Sample tested at TA = 25°C to ensure compliance. Note 4: All digital inputs at GND except for CS at VDD. All digital outputs are unloaded. Analog inputs are connected to GND. Note 5: SCLK is at GND when SCLK is off. All digital inputs are at GND except for CS at VDD. All digital outputs are unloaded. Analog inputs are connected to GND.
VDD = +2.7V to +3.6V; TA = TMIN to TMAX, unless otherwise noted. Parameter Limit Unit Description fSCLK 2 3 MHz (max) External serial clock tCONVERT 14.5 × tSCLK Conversion Time tACQ 1.5 × tSCLK Throughput Time = tCONVERT + tACQ = 16 tSCLK t1 10 ns (min) CS to SCLK Setup Time 3 60 ns (max) Delay from CS until DOUT three-state disabled 3 100 ns (max) Data Access Time after SCLK High-to-Low Edge t4 20 ns (min) Data Setup Time prior to SCLK Low-to-High Edge t5 20 ns (min) Data Valid to SCLK Hold Time t6 0.4 × tSCLK ns (min) SCLK high Pulse Width t7 0.4 × tSCLK ns (min) SCLK low Pulse Width 4 80 ns (max) CS rising edge to DOUT High-Z t9 5 μs (typ) Power-up Time from Shutdown Note 1: Timing specifications are sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed relative to a voltage level of 1.6V. Note 2: The mark/space ratio for the SCLK input is 40/60 to 60/40. See Serial Interface section for additional details. Note 3: Measured with the load circuit as shown below and defined as the time required for the output to cross 0.8V or 2.0V. Note 4: Timing specification t8 is derived from the measured time taken by the data outputs to change 0.5V when loaded with the circuit shown below. The measured result is then extrapolated back to remove the effects of charging or discharging the 50pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the TS7001 and is independent of bus loading. Load Circuit Used for TS7001’s Digital Output Timing Specifications.
Power Supply Rejection vs Frequency POWER SUPPLY REJECTION - dB -97 -93 -89 -85 -77 FREQUENCY - kHz -81 2.7 30 45 60 15 75 90 VDD = 2.7V/3.6V REFIN (External) = 2.488V 100mVPP Sine Wave on VDD VDD = 3V REFIN (External) = 3V Signal-to-Noise Ratio vs Frequency SIGNAL-TO-NOISE RATIO - dB 70.5 71.5 0.7 45 60.2 90 15.5 FREQUENCY - kHz Dynamic Performance vs Frequency FFT RESULTS - dB -140 -100 -80 -60 -40 FREQUENCY - kHz -20 0 20 40 60 -120 4096-point FFT 187.5ksps Sampling Rate 10kHz Fundamental 75 30.5 Integral Nonlinearity INL - LSB DIGITAL OUTPUT CODE -0.6 -0.2 0.2 1k 2k 0 3k 4k 0.6 Differential Nonlinearity DNL - LSB DIGITAL OUTPUT CODE 1k 2k 0 3k 4k -0.6 -0.2 0.2 0.6 TEMPERATURE - ºC -15 35 60 85 10 0.8 0.4 OFFSET ERROR - LSB Offset Error vs Temperature -40 1.6 1.2 TYPICAL PERFORMANCE CHARACTERISTICS VDD = +3V; fSCLK = 3MHz; TA = 25ºC, unless otherwise noted.
1.2 0.8 Gain Error vs Temperature TEMPERATURE - ºC -15 35 60 85 10 GAIN ERROR - LSB -40 0.4 -0.4 Internal Reference Output vs Supply Voltage REFERENCE OUTPUT - V 2.494 2.496 2.498 2.500 2.502 POWER SUPPLY VOLTAGE - Volt TEMPERATURE - ºC -15 35 60 85 10 -40 Internal Reference Output vs Temperature REFERENCE OUTPUT - V 2.495 2.497 2.499 2.501 2.505 2.503 Power Supply Current vs Power Supply Voltage SUPPLY CURENT - mA 0.6 0.5 0.4 0.1 POWER SUPPLY VOLTAGE - Volt 0.3 CODE = 1111 1111 1111 CONVERTING SCLK = 3MHz STATIC 0.2 Power Supply Current vs Temperature TEMPERATURE - ºC -15 35 60 85 10 -40 0.55 0.50 0.40 0.10 0.35 0.15 SUPPLY CURENT - mA STATIC, VDD = 3V CONVERTING, VDD = 3V 0.45 0.30 0.20 0.25 TYPICAL PERFORMANCE CHARACTERISTICS VDD = +3V; fSCLK = 3MHz; TA = 25ºC, unless otherwise noted.
Chip Select: As an active low logic input signal , the CS input provides the dual function of initiating TS7001 conversions as well as framing the serial data transfer. When the TS7001 is operated in Mode 1(its default power management mode), the CS pin also acts as the shutdown pin in that the TS7001 is powered-down when the CS pin is logic high.
2 VDD
Power Supply Voltage: The TS7001’s VDD range +2.7V to +3.6V. In two-channel operation, the VDD pin also serves as the TS7001’s voltage reference source during conversions. For optimal performance, the VDD pin should be bypassed to GND with a 10-µF tantalum capacitor in parallel with a 0.1µF ceramic capacitor.
3 GND
Analog Ground Pin : The GND pin is the ground reference point for all TS7001 internal circuitry. In systems with separate AGND and DGND planes , the TS7001’s GND pin should be connected to the AGND plane.
4 AIN1/VREF
Analog Input Channel 1/External VREF Input: In single-channel mode, the AIN1/VREF pin is configured as VREFIN/OUT. In this mode, the TS7001’s internal 2.5V reference can be accessed or an external reference can be applied to this pin thereby overriding the internal reference. The reference voltage range for an externally-applied reference is 1.2V to VDD. In two -channel mode, the AIN1/VREF pin operates as a second analog input channel, AIN1. The input voltage range on AIN1 is 0 to VDD.
5 AIN0
Analog Input Channel 0: In single -channel operation, AIN0 is the TS7001’s analog input with an input voltage range of 0V to VREF. In two-channel operation, the AIN0 pin exhibits an analog input range of 0V to VDD.
6 DIN
Serial Data Input: Serial data to be loaded into the TS7001’s control register is applied at the DIN pin. Serial data is loaded into the ADC from the host processor on low-to-high SCLK transitions (see the Control Register section for additional information ). Configuring the TS7001 as a single -channel, read-only ADC can be achieved by hard -wiring the DIN pin to GND or by applying a logic LOW at all times at the DIN pin.
7 DOUT
Serial Data Output: The TS7001’s conversion result is available on this pin . Serial data is transferred out of the TS7887 on high -to low transitions of SCLK. The 12-bit conversion result is comprised of four leading zeros followed by the 12 bits of conversion data formatted MSB first. Thus, a total of 16 SCLK high -to-low transitions transfers the conversion result to the host processo r as shown in the corresponding timing diagram of Figure 14.
8 SCLK
Serial-Clock Input: SCLK is used for (3) purpose s: a) to load serial data from the host processor into the TS7001’s control register on low-to-high SCLK transitions; b) to transfer the 12-bit conversion result to the host processor on high -to-low SCLK transitions; and c) to control the TS7001’s conversion process.
conversion result is transferred out of the TS7001. functions of the Control Register’s 8 bits. Table 1. TS7001’s 8-Bit Control Register Content Description 7 DONTC Control Register DB7: Bit status of DB7 is “Don’t Care.” In other words, the DB7 bit can be a “0” or a “1”.
5 REF
4 SIN/DUAL
TS7001 for two-channel operation with the AIN1/VREF pin configured to its AIN1 function as the second analog input. reference should be disabled; that is, a “1” should be loaded into DB5’s register location. the AIN1 input is selected. DB3 should be a “zero” (“0”) when the TS7001 is configured for single-channel operation. Table 2. TS7001’s Power Management Operating Modes CS transition and is powered up on a high-to-low CS transition. Control Register’s REF bit (DB5) should be a “zero” (“0”) to ensure the internal reference is enabled/remains enabled.
example, P1.0) to generate a serial clock and using two other I/O ports (for example, P1.1 for DOUT and P1.2 for DIN) to transfer data from/to the TS7001. A TS7001 to PIC16C6x/PIC16C7x Microcontroller Interface As shown in Figure 20, the connection between the TS7001 and the PIC16C6x/PIC16C7x is simple and does not require any glue logic circuits. The PIC16C6x synchronous serial port (SSP) is configured as an SPI master with its clock polarity bit set to 1 by writing to the synchronous serial port control register (SS PCON). In this example, I/O port RA1 is being used to generate the TS7001’s CS signal. Since this microcontroller family only transfers eight bits of data during each serial transfer operation, two consecutive read/write operations are required. For additional information, please consult the PIC16/PIC17 Microcontroller User Manual. APPLICATIONS INFORMATION Ground Plane Management and Layout For best performance, printed circuit boards should always be used and wire -wrap boards are not recommended. Good PC board layout techniques ensure that digital and analog signal lines are kept separate from each other, analog and digital (especially clock) lines are not routed parallel to one another, and high -speed digital lines are not routed underneath the ADC package. A contiguous analog ground plane should be routed under the TS7001 to avoid digital noise coupling. A single-point analog ground (star ground point) should be created at the ADC’s GND and separate from any digital logic ground. All analog grounds as well as the ADC’s GND pin should be connected to the star ground. No other digital system ground should be made to this ground connection. For lowest-noise operation, the ground return to the star ground’s power supply should be low impedance and as short as possible. Even though the TS7001’s exhibits excellent supply rejection as shown in th Typical Operating Characteristics, it is always considered good engineering practice to prevent h igh-frequency noise on the TS7001’s VDD power supply from affecting the ADC’s high -speed comparator. Therefore, the VDD supply pin should be bypassed to the star ground with 0.1μF and 1 0μF capacitors in parallel and placed close to the ADC’s Pin 2 as was shown in Figure 4. Component lead lengths should be very short for o ptimal supply-noise rejection. If the power supply is very noisy, an optional 10 -Ω resistor inserted in series with the TS7001’s VDD pin can be used in conjunction with the bypass capacitors to form a low-pass filter. Evaluating the TS7001’s Dynamic Performance The recommended layout for the TS7001 is outlined in the demo board manual for the TS7001. The demo board kit includes a fully assembled/ tested demo board and documentation describing how to evaluate the TS7001’s dynamic performance using Touchstone Semiconductor’s proprietary TSDA -VB data acquisition/capture kit. Figure 20: Interfacing the TS7001 to PIC16C6x/PIC16C7x-type Microcontrollers.
Page 20 Touchstone Semiconductor, Inc. TS7001DS r1p0
630 Alder Drive, Milpitas, CA 95035 RTFDS
+1 (408) 215 - 1220 ▪ www.touchstonesemi.com PACKAGE OUTLINE DRAWING 8-Pin MSOP Package Outline Drawing (N.B., Drawings are not to scale)
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NOTE: 1. PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 2. PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTUSIONS. 3. CONTROLLING DIMENSION IN MILIMETERS. 4. THIS PART IS COMPLIANT WITH JEDEC MO-187 VARIATIONS AA 5. LEAD SPAN/STAND OFF HEIGHT/COPLANARITY ARE CONSIDERED AS SPECIAL CHARACTERISTIC. 1 2
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