TS612

TS612 STMICROELECTRONICS | Alldatasheet

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Technical content

■ LOW NOISE : 3nV/√Hz, 1.2pA/√Hz ■ HIGH OUTPUT CURRENT : 200mA ■ VERY LOW HARMONIC AND INTERMODU- LATION DISTORTION ■ HIGH SLEW RATE : 40V/µs ■ SPECIFIED FOR 25Ω LOAD

DESCRIPTION

The TS612 is a dual operational amplifier featur- ing a high output current (200mA min.), large gain-bandwidth product (130MHz) and capable of driving a 25Ω load with a 160mA output current at ±6V power supply. This device is particularly intended for applications where multiple carriers must be amplified simulta- neously with very low intermodulation products. The TS612 is housed in SO20 batwing plastic package for a very low thermal resistance. The TS612 is fitted out with Power Down function in order to decrease the consumption. APPLICATION ■ UPSTREAM line driver for Assymetric Digital Subscriber Line (ADSL) (NT). ORDER CODE D = Small Outline Package (SO) - also available in Tape & Reel (DT) PIN CONNECTIONS (top view) Part Number Temperature Range Package D TS612ID -40, +85°C • D SO-20 Batwing (Plastic Micropackage) Top view Vcc+ 1 Inverting input 1 Non-inverting input 1 Vcc+ 2 Vcc - Vcc - Power Down 2 Non-Inverting input 2 Inverting input 2 GND Vcc - Vcc - Vcc - Vcc - Vcc - Vcc - Power Down 1 Vcc- Output 1 Output 2 TS612 DUAL WIDE BAND OPERATIONAL AMPLIFIER WITH HIGH OUTPUT CURRENT May 2000

Symbol Parameter Value Unit VCC Supply voltage 1) ±7 V Vid Differential Input Voltage 2) ±2 V Vin Input Voltage Range 3) ±6 V Toper Operating Free Air Temperature Range TS612ID -40 to + 85 °C Tstd Storage Temperature -65 to +150 °C Tj Maximum Junction Temperature 150 °C R thjc Thermal Resistance Junction to Case 25 °C/W R thja Thermal Resistance Junction to Ambient Area 45 °C/W Pmax. Maximum Power Dissipation (@25°C) 2.6 W Output Short Circuit Duration 4) 1. All voltages values, except differential voltage are with respect to network terminal. 2. Differential voltages are non-inverting input terminal with respect to the inverting input terminal. 3. The magnitude of input and output voltages must never exceed V CC +0.3V. 4. An output current limitation protects the circuit from transient currents. Short-circuits can cause excessive heating. Destructive dissipation can result from short circuit on amplifiers. Symbol Parameter Value Unit VCC Supply Voltage ±2.5 to ±6 V Vicm Common Mode Input Voltage (VCC ) +2 to (VCC +) -1 V

ELECTRICAL CHARACTERISTICS VCC = ±6Volts, Tamb = 25°C (unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max Unit DC PERFORMANCE Vio Input Offset Voltage Tamb -6 -1 6 mV Tmin. < Tamb < Tmax. 10 ΔVio Differential Input Offset Voltage Tamb = 25°C 6m V Iio Input Offset Current Tamb 0.2 3 µA Tmin. < Tamb < Tmax. 5 Iib Input Bias Current Tamb 51 5 µA Tmin. < Tamb < Tmax. 30 CMR Common Mode Rejection Ratio Vic = 2V to 2V, Tamb 90 108 dB Tmin. < Tamb < Tmax. 70 SVR Supply Voltage Rejection Ratio Vic = ±6V to ±4V, Tamb 70 88 dB Tmin. < Tamb < Tmax. 50 ICC Total Supply Current per Operator No load, Vout = 0 14 mA DYNAMIC PERFORMANCE VOH High Level Output Voltage Iout = 160mA R L connected to GND 4 4.5 V VOL Low Level Output Voltage Iout = 160mA R L connected to GND -4.5 -4 V AVD Large Signal Voltage Gain Vout = 7V peak R L = 25Ω , Tamb 6500 11000 V/V Tmin. < Tamb < Tmax. 5000 GBP Gain Bandwidth Product AVCL = +11, f = 20MHz R L = 100Ω 80 130 MHz SR Slew Rate AVCL = +7, RL = 50Ω 23 40 V/ µs Iout Output Short Circuit Current ±320 mA Isink Output Sink Current Vic = ±6V, Tamb +200 mA Tmin. < Tamb < Tmax. +180 Isource Output Source Current Vic = ±6V, Tamb -200 mA Tmin. < Tamb < Tmax. -180 Φ M14 Phase Margin at AVCL = 14dB R L = 25Ω //15pF 60 ° Φ M6 Phase Margin at AVCL = 6dB R L = 25Ω //15pF 40 °

ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Condition Min. Typ. Max Unit NOISE AND DISTORTION en Equivalent Input Noise Voltage f = 100kHz 3 nV/ √Hz in Equivalent Input Noise Current f = 100kHz 1.2 pA/ √Hz THD Total Harmonic Distortion Vout = 4Vpp, f = 100kHz AVCL = -10 R L = 25Ω //15pF -69 dB HD2 -10 2nd Harmonic Distortion Vout = 4Vpp, f = 100kHz AVCL = -10 Load =25Ω //15pF -70 dBc HD2 +2 2nd Harmonic Distortion Vout = 4Vpp, f = 100kHz AVCL = +2 Load =25Ω //15pF -74 dBc HD3 +2 3rd Harmonic Distortion Vout = 4Vpp, f = 1MHz AVCL = +2 Load =25Ω //15pF -79 dBc HD3 -10 3rd Harmonic Distortion Vout = 4Vpp, f = 100kHz AVCL = -10 Load =25Ω //15pF -80 dBc IM2-10 2nd Order Intermodulation Product F1 = 80kHz, F2 = 70kHz Vout = 8Vpp, AVCL = -10 Load = 25Ω //15pF -77 dBc IM3-10 3rd Order Intermodulation Product F1 = 80kHz, F2 = 70kHz Vout = 8Vpp, AVCL = -10 Load = 25Ω //15pF -77 dBc

VCC = ±6Volts, Tamb = 25°C POWER DOWN EQUIVALENT SHEMATIC OUPUT IMPEDANCE IN POWER DOWN MODE In Power Down Mode the output of the driver is in "high impedance" state. It is really the case for the static mode. Regarding the dynamic mode, the im- pedance decreases due to a capacitive effect of the collector-substrat and base collector junction. The impedance behaviour comes capacitive, typi- cally: 1.4MΩ // 33pF. Symbol Parameter Min. Typ. Max Unit Vpdw Pin (1)(7) Thershold Voltage for Power Down Mode V Low Level 0 0.8 High Level 2 3.3 Iccpdw Power Down Mode Current Consumption 75 µA R pdw Power Down Mode Ouput Impedance 3 Ω C pdw Power Down Mode Output Capacitance TBD µA STANDBY CONTROL OPERATOR STATUS pin (1) operator 1 pin (7) operator 2 operator 1 operator 2 Vhigh level Vlow level Standby Active Vhigh level Vhigh level Standby Standby Vlow level Vlow level Active Active Vlow level Vhigh level Active Standby Vcc - Vcc + /c51 /c50/c58/c40/c53 /c39/c50/c58/c49 Oupu t.

INTERMODULATION DISTORTION The curves shown below are the measurements results of a single operator wired as an adder with a gain of 15dB. The operational amplifier is supplied by a symmetric ±6V and is loaded with 25Ω . Two synthesizers (Rhode & Schwartz SME) generate two frequencies (tones) (70 & 80kHz or 180 & 280kHz). An HP3585 spectrum analyzer measures the spurious level at different frequencies. The curves are traced for different output levels (the value in the X ax is the value of each tone). The output levels of the two tones are the same. The generators and spectrum analyzer are phase locked to enhance measurement precision. 3rd ORDER INTERMODULATION (2 tones : 70kHz and 80kHz) 2nd ORDER INTERMODULATION Spurious measurement @ 100kHz (2 tones : 180kHz and 280kHz) 3rd ORDER INTERMODULATION (2 tones : 180kHz and 280kHz) 11 , 522 , 533 , 544 , 5 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 IM3 (dBc) Vout peak (V) 230kHz 220kHz 90kHz 60kHz Vout peak (V) 1 , 522 , 533 , 544 , 5 -70 -65 -60 -55IM2 (dBc) 11 , 522 , 533 , 544 , 5 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 IM3 (dBc) Vout peak (V) 80kHz 640kHz 380kHz 740kHz

Closed Loop Gain and Phase vs. Frequency Gain=+2, Vcc=±6V, RL=25Ω Closed Loop Gain and Phase vs. Frequency Gain=+11, Vcc=±6V, RL=25Ω Maximum Output Swing Vcc=±6V, RL=25Ω Closed Loop Gain and Phase vs. Frequency Gain=+6, Vcc=±6V, RL=25Ω Equivalent Input Voltage Noise Gain=+100, Vcc=±6V, no load Channel Separation (Xtalk) vs. Frequency XTalk=20Log(V2/V1), Vcc=±6V, RL=25Ω -30 -20 -10 Gain (dB) -200 -100 100 200 Phase (degrees) 10kHz 100kHz 1MHz 10MHz 100MHz Frequency Gain Phase -30 -20 -10 30Gain (dB) -200 -100 100 200 Phase (degrees) 10kHz 100kHz 1MHz 10MHz 100MHz Frequency Gain Phase 02468 1 0 Time (µs) 5swing (V) output input -20 -15 -10 20Gain (dB) -200 -100 100 200 Phase (degrees) 10kHz 100kHz 1MHz 10MHz 100MHz Frequency Gain Phase 100Hz 1kHz 10kHz 100kHz 1MHz 20en (nV/VHz) 100 10k Frequency -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 Xtalk (dB) 10kHz 100kHz 1MHz 10MHz Frequency 100Ω 1kΩ 49.9Ω VIN 100Ω 1kΩ 49.9Ω 25Ω 25Ω

1µF capacitance provides a path for low frequen- cies, the 10nF capacitance provides a path for high end of the spectrum. In differential mode the TS612 is able to deliver a typical amplitude signal of 18V peak to peak. The dynamic line impedance is 100Ω . The typical value of the amplitude signal required on the line is up to 12.4V peak to peak. By using a 1:2 trans- former ratio the reflected impedance back to the primary will be a quarter (25Ω ) and therefore the amplitude of the signal required with this imped- ance will be the half (6.2 V peak to peak). Assum- ing the 25Ω series resistance (12.5Ω for both out- puts) necessary for impedance matching, the out- put signal amplitude required is 12.4 V peak to peak. This value is acceptable for the TS612. In this case the load impedance is 25Ω for each driv- er. For the ADSL upstream path, a lowpass filter is absolutely necessary to cutoff the higher frequen- cies from the DAC analog output. In this simple non-inverting amplification configuration, it will be easy to implement a Sallen-Key lowpass filter by using the TS612. For ADSL over POTS, a maxi- mum frequency of 135kHz is reached. For ADSL over ISDN, the maximum frequency will be 276kHz. INCREASING THE LINE LEVEL BY USING AN ACTIVE IMPEDANCE MATCHING With passive matching, the output signal ampli- tude of the driver must be twice the amplitude on the load. To go beyond this limitation an active maching impedance can be used. With this tech- nique it is possible to keep good impedance matching with an amplitude on the load higher than the half of the ouput driver amplitude. This concept is shown in figure3 for a differential line. Component calculation: Let us consider the equivalent circuit for a single ended configuration, figure4. Let us consider the unloaded system. Assuming the currents through R1, R2 and R3 as respectively: As Vo° equals Vo without load, the gain in this case becomes : The gain, for the loaded system will be (1): As shown in figure5, this system is an ideal gener- ator with a synthesized impedance as the internal impedance of the system. From this, the output voltage becomes: with Ro the synthesized impedance and Iout the output current. On the other hand Vo can be ex- pressed as: Figure 3 : TS612 as a differential line driver with an active impedance matching R2Vi Vi Vo Vo 25Ω 100Ω 1:2 Hybrid Transformer GND +12V 47k 47k10µ 100n 100n 100n 12.5 12.5 10n Vo° Vo° GND 20 +12V 11 +12V Figure 4 : Single ended equivalent circuit 1/2R1 _Vi Vo Rs1 Vo° 1/2RL 2Vi G Vo noload() 1 2R 2

1 R 2

GL Vo withload() 2--- 1 2R 2 Vo ViG() RoIout()–= 2(), Vo Vi 1 2R 2

By identification of both equations (2) and (3), the synthesized impedance is, with Rs1=Rs2=Rs: Unlike the level Vo° required for a passive imped- ance, Vo° will be smaller than 2Vo in our case. Let us write Vo°=kVo with k the matching factor vary- ing between 1 and 2. Assuming that the current through R3 is negligeable, it comes the following resistance divider: After choosing the k factor, Rs will equal to 1/2RL(k-1). A good impedance matching assumes: From (4) and (5) it becomes: By fixing an arbitrary value for R2, (6) gives: Finally, the values of R2 and R3 allow us to extract R1 from (1), and it comes: with GL the required gain. CAPABILITIES The table below shows the calculated compo- nents for different values of k. In this case R2=1000 Ω and the gain=16dB. The last column displays the maximum amplitude level on the line regarding the TS612 maximum output capabilities (18Vpp diff.) and a 1:2 line transformer ratio. MEASUREMENT OF THE POWER CONSUMPTION IN THE ADSL APPLICATION Conditions: Passive impedance matching Transformer turns ratio: 2 Maximun level required on the line: 12.4Vpp Maximum output level of the driver: 12.4Vpp Crest factor: 5.3 (Vp/Vrms) The TS612 power consumption during emission on 900 and 4550 meter twisted pair telephone lines: 450mW Figure 5 : Equivalent schematic. Ro is the syn- thesized impedance Ro Rs Vi.Gi Iout 1/2RL Ro kVoRL Ro 1 2---RL 5(),= R 2 R 3 R 2 1 2Rs R 1 2R 2

21 R 2

 GL 1– R 2 GL (gain for the loaded system) GL is fixed for the application requirements GL=Vo/Vi=0.5(1+2R2/R1+R2/R3)/(1-R2/R3) R1 2R2/[2(1-R2/R3)GL-1-R2/R3] R2 (=R4) Abritrary fixed R3 (=R5) R2/(1-Rs/0.5RL) Rs 0.5RL(k-1) Active matching k R1 (Ω ) (Ω ) Rs (Ω ) TS612 Output Level to get 12.4Vpp on the line (Vpp diff) Maximum Line level (Vpp diff) 1.3 820 1500 3.9 8 27.5 1.4 490 1600 5.1 8.7 25.7 1.5 360 2200 6.2 9.3 25.3 1.6 270 2400 7.5 9.9 23.7 1.7 240 3300 9.1 10.5 22.3 Passive matching 12.4 18

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2000 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom © http://www.st.com PACKAGE MECHANICAL DATA

8 PINS - PLASTIC MICROPACKAGE (SO)

Dim. Millimeters Inches A 2.65 0.104 a1 0.1 0.3 0.004 0.012 a2 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 C 0.5 0.020 c1 45° (typ.) D 12.6 13.0 0.496 0.512 E 10 10.65 0.394 0.419 e 1.27 0.050 e3 11.43 0.450 F 7.4 7.6 0.291 0.299 L 0.5 1.27 0.020 0.050 M 0.75 0.030 S 8° (max.)