TS5V330D

TS5V330_10 TI | Alldatasheet

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D D, DBQ, OR PW PACKAGE (TOP VIEW) RGY P ACKAGE (TOP VIEW) 1 16 8 9 EN S1D S2D D D S1C S2C S1A S2A D A S1B S2B D B IN V GND CC IN S1A S2A D A S1B S2B D B GND VCC EN S1D S2D D D S1C S2C D C C DESCRIPTION/ORDERING INFORMATION TS5V330 www.ti.com SCDS164D MAY 2004 REVISED JUNE 2009 QUAD SPDT WIDE-BANDWIDTH VIDEO SWITCH WITH LOW ON-STATE RESISTANCE Low Differential Gain and Phase G 0.64%, D P 0.1 Degrees Typ) Wide Bandwidth (BW 300 MHz Min) Low Crosstalk TALK dB Typ) Low Power Consumption CC µ A Max) Bidirectional Data Flow With Near-Zero Propagation Delay Low ON-State Resistance on Ω Typ) V CC Operating Range From 4.5 V to 5.5 V I off Supports Partial-Power-Down Mode Operation Data and Control Inputs Provide Undershoot Clamp Diode Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS Outputs Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 1000-V Charged-Device Model (C101) Suitable for Both RGB and Composite-Video Switching The TS5V330 video switch is a 4-bit 1-of-2 multiplexer/demultiplexer with a single switch-enable EN input. When EN is low, the switch is enabled and the D port is connected to the S port. When EN is high, the switch is disabled and the high-impedance state exists between the D and S ports. The select (IN) input controls the data path of the multiplexer/demultiplexer. Low differential gain and phase make this switch ideal for composite and RGB video applications. This device has wide bandwidth and low crosstalk, making it suitable for high-frequency

applications

well. This device is fully specified for partial-power-down I off The I off feature ensures that damaging current will not backflow through the device when it is powered down. This switch maintains isolation during power off. Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. PRODUCTION DATA information is current as of publication date. Copyright 2004 2009, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

(CONTINUED) TS5V330 SCDS164D MAY 2004 REVISED JUNE 2009 www.ti.com ORDERING INFORMATION T A PACKAGE (1) ORDERABLE PART NUMBER TOP-SIDE MARKING QFN RGY Tape and reel TS5V330RGYR TE330 Tube TS5V330D SOIC D TS5V330 Tape and reel TS5V330DR C to C SSOP (QSOP) DBQ Tape and reel TS5V330DBQR TE330 Tube TS5V330PW TSSOP PW TE330 Tape and reel TS5V330PWR (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. To ensure the high-impedance state during power up or power down, EN should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTION TABLE INPUTS INPUT/OUTPUT FUNCTION D EN IN L L D port port L H D port port H X Z Disconnect xxxx PIN

DESCRIPTION

S1, Analog video I/Os D Analog video I/Os IN Select input EN Switch-enable input Submit Documentation Feedback Copyright 2004 2009, Texas Instruments Incorporated Product Folder Link(s): TS5V330

www.ti.com SCDS164D MAY 2004 REVISED JUNE 2009 PARAMETER DEFINITIONS PARAMETER r on Resistance between the D and S ports, with the switch in the ON state I OZ Output leakage current measured at the D and S ports, with the switch in the OFF state I OS Short-circuit current measured at the I/O pins V IN Voltage at IN V EN Voltage at EN C IN Capacitance at the control EN IN) inputs C OFF Capacitance at the analog I/O port when the switch is OFF C ON Capacitance at the analog I/O port when the switch is ON V IH Minimum input voltage for logic high for the control EN IN) inputs V IL Minimum input voltage for logic low for the control EN IN) inputs V hys Hysteresis voltage at the control EN IN) inputs V IK I/O and control EN IN) inputs diode clamp voltage V I Voltage applied to the D or S pins when D or S is the switch input V O Voltage applied to the D or S pins when D or S is the switch output I IH Input high leakage current of the control EN IN) inputs I IL Input low leakage current of the control EN IN) inputs I I Current into the D or S pins when D or S is the switch input I O Current into the D or S pins when D or S is the switch output I off Output leakage current measured at the D or S ports, with V CC t ON Propagation delay measured between 50% of the digital input to 90% of the analog output when switch is turned ON t OFF Propagation delay measured between 50% of the digital input to 90% of the analog output when switch is turned OFF BW Frequency response of the switch in the ON state measured at dB Unwanted signal coupled from channel to channel. Measured in dB. X TALK log V O I This is a nonadjacent X TALK crosstalk. O IRR Off isolation is the resistance (measured in dB) between the input and output with the switch OFF. Magnitude variation between analog input and output pins when the switch is ON and the dc offset of composite-video D G signal varies at the analog input pin. In the NTSC standard, the frequency of the video signal is 3.58 MHz, and dc offset is from to 0.714 Phase variation between analog input and output pins when the switch is ON and the dc offset of composite-video signal D P varies at the analog input pin. In the NTSC standard, the frequency of the video signal is 3.58 MHz, and dc offset is from to 0.714 I CC Static power-supply current I CCD Variation of I CC for a change in frequency in the control EN IN) inputs Δ I CC This is the increase in supply current for each control input that is at the specified voltage level, rather than V CC or GND. Copyright 2004 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TS5V330

(1) TS5V330 SCDS164D MAY 2004 REVISED JUNE 2009 www.ti.com FUNCTIONAL DIAGRAM (POSITIVE LOGIC) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT V CC Supply voltage range 0.5 V V IN Control input voltage range (2) (3) 0.5 V V I/O Switch I/O voltage range (2) (3) (4) 0.5 V I IK Control input clamp current V IN mA I I/OK I/O port clamp current V I/O mA I I/O ON-state switch current (5) 128 mA Continuous current through V CC or GND 100 mA D package (6) DBQ package (6) θ JA Package thermal impedance C/W PW package (6) 108 RGY package (7) T stg Storage temperature range 150 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are with respect to ground, unless otherwise specified. (3) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. (4) V I and V O are used to denote specific conditions for V I/O (5) I I and I O are used to denote specific conditions for I I/O (6) The package thermal impedance is calculated in accordance with JESD 51-7. (7) The package thermal impedance is calculated in accordance with JESD 51-5. Submit Documentation Feedback Copyright 2004 2009, Texas Instruments Incorporated Product Folder Link(s): TS5V330

(1) Electrical Characteristics TS5V330 www.ti.com SCDS164D MAY 2004 REVISED JUNE 2009 MIN MAX UNIT V CC Supply voltage range 5.5 V V IH High-level control input voltage range EN IN) 5.5 V V IL Low-level control input voltage range EN IN) 0.8 V V ANALOG Analog I/O voltage range Vcc V T A Operating free-air temperature range C (1) All unused control inputs of the device must be held at V CC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs literature number SCBA004. over recommended operating free-air temperature range, V CC V 10% (unless otherwise noted) PARAMETER TEST CONDITIONS (1) MIN TYP (2) MAX UNIT V IK EN IN V CC 4.5 I IN mA 1.8 V V hys EN IN 150 mV I IH EN IN V CC 5.5 V IN and V EN V CC µ A I IL EN IN V CC 5.5 V IN and V EN GND µ A I OZ (3) V CC 5.5 V O to 5.5 V I Switch OFF µ A I OS (4) V CC 5.5 V O 0.5 V CC, V I Switch ON mA I off V CC V O to 5.5 V I µ A I CC V CC 5.5 I I/O Switch ON or OFF µ A Δ I CC EN IN V CC 5.5 One input at 3.4 Other inputs at V CC or GND 2.5 mA I CCD V EN GND, V CC 5.5 D and S ports open, V IN input switching 50% duty cycle 0.25 mA/MHz V IN of V EN C IN EN IN 3.5 pF f MHz D port C OFF V I f MHz, Outputs open, Switch OFF pF S port C ON V I f MHz, Outputs open, Switch ON pF V I I O mA, R L Ω r on (5) V CC 4.5 V Ω V I I O mA, R L Ω (1) V I V O I I and I O refer to I/O pins. (2) All typical values are at V CC V (unless otherwise noted), T A (3) For I/O ports, I OZ includes the input leakage current. (4) The I OS test is applicable to only one ON channel at a time. The duration of this test is less than (5) Measured by the voltage drop between the D and S terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two or terminals. Copyright 2004 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TS5V330

www.ti.com over recommended operating free-air temperature range, V CC V 10%, R L Ω C L pF (unless otherwise noted) (see Figure FROM TO PARAMETER MIN TYP MAX UNIT (INPUT) (OUTPUT) t ON S D 2.5 ns t OFF S D 1.1 ns over recommended operating free-air temperature range, V CC V 10% (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT D G (2) R L 150 Ω f 3.58 MHz, See Figure 0.64 D P (2) R L 150 Ω f 3.58 MHz, See Figure 0.1 Deg BW R L 150 Ω See Figure 300 MHz X TALK R L 150 Ω f MHz, RIN Ω See Figure dB O IRR R L 150 Ω f MHz, See Figure dB (1) All typical values are at V CC V (unless otherwise noted), T A (2) D G and D P are expressed in absolute magnitude. Submit Documentation Feedback Copyright 2004 2009, Texas Instruments Incorporated Product Folder Link(s): TS5V330

−60 −50 −40 −30 −20 −10 1 10 100 1000 Phase − Deg −1Gain − dB Phase Gain Frequency − MHz Phase at −3-dB Frequency, 35 Degrees Gain −3 dB at 460 MHz −0.01 0.00 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 Differential Phase − Deg −1.0 −0.9 −0.8 −0.7 −0.6 −0.5 −0.4 −0.3 −0.2 −0.1 0.0 Differential Gain − % VBIAS − V Differential Phase Differential Gain Differential Phase at 0.714, 0.056 Degrees Differential Gain at 0.714, −0.63% TS5V330 www.ti.com SCDS164D MAY 2004 REVISED JUNE 2009 Figure Gain/Phase vs Frequency Figure Differential Gain/Phase vs V BIAS Copyright 2004 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TS5V330

−90 −80 −70 −60 −50 −40 −30 −20 −10 1 10 100 1000 Frequency − MHz Phase − Deg 100 120 140 160 Off Isolation − dB Off Isolation Phase Phase at 10 MHz, 88.5 Degrees Off Isolation at 10 MHz, −60 dB 100 150 200 250 1 10 100 1000 Frequency − Mhz Phase − Deg −90 −80 −70 −60 −50 −40 −30 −20 −10 Crosstalk Phase Phase at 10 MHz, −90.4 Degrees Crosstalk at 10 MHz, −63.9 dB Crosstalk − dB TS5V330 SCDS164D MAY 2004 REVISED JUNE 2009 www.ti.com Figure Off Isolation vs Frequency Figure Crosstalk vs Frequency Submit Documentation Feedback Copyright 2004 2009, Texas Instruments Incorporated Product Folder Link(s): TS5V330

(see Note A) TEST CIRCUIT R L Analog Output Waveform (VO ) tON 0 V 3 V VOLT AGE W AVEFORMS tON AND tOFF TIMES NOTES: A. C L includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr10 MHz, ZO = 50 W , tr ≤/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr2.5 ns, tf ≤/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr2.5 ns. C. The outputs are measured one at a time, with one transition per measurement. 50% 50% 50 Ω VG1 VCC DUT 50 Ω VIN VS2 TEST C LR L VS2 5 V ±/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr0.5 V 5 V ±/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr0.5 V VCC VS1 tOFF tON 5 V ±/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr0.5 V 5 V ±/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr0.5 V GND 3 V GND 3 V 3 V GND 3 V GND Output Control (VIN) Input Generator VOVS1 IN S2 EN D 0 V VOH tOFF 90%90% TS5V330 www.ti.com SCDS164D MAY 2004 REVISED JUNE 2009 Figure Test Circuit and Voltage Waveforms Copyright 2004 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TS5V330

(HP8753ES) EXT TRIGGER BIAS P1 P2 VBIAS Sawtooth W aveform Generator DUT IN EN S1A VEN VIN VCC NOTE A: For additional information on measurement method, refer to the TI application report, Measuring Differential Gain and Phase, literature number SLOA040. R L = 150 Ω D A HP8753ES Setup Sawtooth Waveform Generator Setup TS5V330 SCDS164D MAY 2004 REVISED JUNE 2009 www.ti.com Figure Test Circuit for Differential Gain/Phase Measurement Differential gain and phase are measured at the output of the ON channel. For example, when V IN V EN and DA is the input, the output is measured at A Average RBW 300 Hz ST 1.381 s dBM CW frequency 3.58 MHz V BIAS to V Frequency 0.905 Hz Submit Documentation Feedback Copyright 2004 2009, Texas Instruments Incorporated Product Folder Link(s): TS5V330

(HP8753ES) R L = 150 Ω EXT TRIGGER BIAS P1 P2 DUT D A IN EN S1A VEN VIN VCC VBIAS HP8753ES Setup TS5V330 www.ti.com SCDS164D MAY 2004 REVISED JUNE 2009 Figure Test Circuit for Frequency Response (BW) Frequency response is measured at the output of the ON channel. For example, when V IN V EN and D A is the input, the output is measured at A All unused analog I/O ports are left open. Average RBW Hz V BIAS 0.35 V ST s dBM Copyright 2004 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TS5V330

(HP8753ES) R L = 150 Ω EXT TRIGGER BIAS P1 P2 DUT D A IN EN S1A VEN VIN VCC VBIAS D B R IN = 10 Ω R L = 150 Ω S1B 50 Ω (1) (1) A 50-Ω termination resistor is needed for the network analyzer. HP8753ES Setup TS5V330 SCDS164D MAY 2004 REVISED JUNE 2009 www.ti.com Figure Test Circuit for Crosstalk TALK Crosstalk is measured at the output of the nonadjacent ON channel. For example, when V IN V EN and D A is the input, the output is measured at B All unused analog input (D) ports and output (S) ports are connected to GND through 10- Ω and 50- Ω pulldown resistors, respectively. Average RBW kHz V BIAS 0.35 V ST s dBM Submit Documentation Feedback Copyright 2004 2009, Texas Instruments Incorporated Product Folder Link(s): TS5V330

(HP8753ES) R L = 150 Ω EXT TRIGGER BIAS P1 P2 DUT D A IN EN S1A VEN VIN VCC VBIAS R L = 150 Ω S2A 50 Ω (1) (1) A 50-Ω termination resistor is needed for the network analyzer. HP8753ES Setup TS5V330 www.ti.com SCDS164D MAY 2004 REVISED JUNE 2009 Figure Test Circuit for Off Isolation IRR Off isolation is measured at the output of the OFF channel. For example, when V IN V CC V EN and D A is the input, the output is measured at A All unused analog input (D) ports are left open, and output (S) ports are connected to GND through 50- Ω pulldown resistors. Average RBW kHz V BIAS 0.35 V ST s dBM Copyright 2004 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TS5V330

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TS5V330D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS5V330DBQR ACTIVE SSOP/ QSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TS5V330DBQRE4 ACTIVE SSOP/ QSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TS5V330DBQRG4 ACTIVE SSOP/ QSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TS5V330DE4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS5V330DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS5V330DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS5V330DRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS5V330DRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS5V330PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS5V330PWE4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS5V330PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS5V330PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS5V330PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS5V330PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS5V330RGYR ACTIVE VQFN RGY 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TS5V330RGYRG4 ACTIVE VQFN RGY 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame PACKAGE OPTION ADDENDUM www.ti.com 21-Dec-2009 Addendum-Page 1

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 21-Dec-2009 Addendum-Page 2

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 30-Jul-2010 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TS5V330DR SOIC D 16 2500 333.2 345.9 28.6 TS5V330PWR TSSOP PW 16 2000 346.0 346.0 29.0 TS5V330RGYR VQFN RGY 16 3000 346.0 346.0 29.0 PACKAGE MATERIALS INFORMATION www.ti.com 30-Jul-2010 Pack Materials-Page 2

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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