TS5USBC41_V01 TI | Alldatasheet
Document overview
- Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
- PDF pages: 30
Technical content
VBUSDP_TDP_BDM_TDM_BGND USB Connector UART USB D2- SEL1 SEL2 OE FLT Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TS5USBC41 SCDS377B –MARCH 2018–REVISED JUNE 2018 TS5USBC41Dual2:1USB2.0Mux/DeMuxorSingleEndedCrossSwitchwith20-V/24-V OvervoltageProtection
1 Features
1• Supply Range 2.3 V to 5.5 V
- Differential 2:1 or 1:2 Switch/Multiplexer or Flexible Dual Single Ended Cross Switch
- 0-V to 20-V (TS5USBC410) and 24-V (TS5USBC412) Overvoltage Protection (OVP) on Common Pins
- Powered Off Protection When VCC = 0 V
- Low RON of 9 Ω Maximum
- BW of 1.1-GHz (TS5USBC410) and 1.2-GHz (TS5USBC412) Typical
- CON typical of 2.7 pF (TS5USBC410) and 2.5 pF (TS5USBC412)
- Low Power Disable Mode
- 1.8-V Compatible Logic Inputs
- ESD Protection Exceeds JESD 22 – 2000-V Human Body Model (HBM)
- TS5USBC410 and TS5USBC412: Standard Temperature Range of 0°C to 70°C
- TS5USBC410I and TS5USBC412I: Industrial Temperature Range of -40°C to 85°C
- Small DSBGA Package
2 Applications
- Mobile
- PC/Notebook
- Tablet
- Anywhere a USB Type-C™ or Micro-B Connector is Used
3 Description
The TS5USBC41 is a bidirectional low-power dual port, high-speed, USB 2.0 analog switch with integrated protection for USB Type-C™ systems. The device is configured as a dual 2:1 or 1:2 switch. It is optimized for use with the USB 2.0 D+/- lines in a USB Type-C™ systems. The TS5USBC41 protection on the I/O pins can tolerate up to 20 V (TS5USBC410) or 24 V (TS5USBC412) with automatic shutoff circuitry to protect system components behind the switch. The TS5USBC41 comes in a small 12 pin DSBGA package making it a perfect candidate for mobile and space constrained applications. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TS5USBC410 TS5USBC410I TS5USBC412 TS5USBC412I DSBGA (12) 1.638 mm × 1.238 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic
SCDS377B –MARCH 2018–REVISED JUNE 2018 www.ti.com Product Folder Links: TS5USBC41 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Table of Contents
12.2 Receiving Notification of Documentation Updates 22
13 Mechanical, Packaging, and Orderable
4 Revision History
Changes from Revision A (May 2018) to Revision B Page
A B C Not to scale SEL1 D+ D ± FLT VCC SEL2 GND OE D2+ D2 ± D1+ D1 ± TS5USBC41 www.ti.com SCDS377B –MARCH 2018–REVISED JUNE 2018 Product Folder Links: TS5USBC41 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated
5 Pin Configuration and Functions
NO. NAME A1 SEL1 I Switch select1. Refer to Table 1. A2 D+ I/O Data switch input (Differential +). A3 D– I/O Data switch input (Differential –) A4 FLT O Fault indicator output pin (Active low) - open drain B1 VCC PWR Supply Voltage B2 SEL2 I Switch select2. Refer to Table 1. B3 GND GND Ground B4 OE I Output enable (Active low). Refer to Table 1. C1 D2+ I/O Data switch output 2 (Differential +) C2 D2– I/O Data switch output 2 (Differential -) C3 D1+ I/O Data switch output 1 (Differential +) C4 D1– I/O Data switch output 1 (Differential -)
SCDS377B –MARCH 2018–REVISED JUNE 2018 www.ti.com Product Folder Links: TS5USBC41 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum. (3) All voltages are with respect to ground, unless otherwisespecified.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2) MIN MAX UNIT VCC Supply voltage(3) -0.5 6 V VI/O Input/Output DC voltage (D+, D-) (TS5USBC412, TS5USBC412I)(3) -0.5 28 V VI/O Input/Output DC voltage (D+, D-) (TS5USBC410, TS5USBC410I)(3) -0.5 24 V VI/O Input/Output DC voltage (D1+/D1-, D2+/D2-)(3) -0.5 6 V VI Digital input voltage (SEL1, SEL2, OE) -0.5 6 V VO Digital output voltage (FLT) -0.5 6 V IK Input-output port diode current (D+, D-, D1+, D1-, D2+, D2-) when VIN < 0 -50 mA IIK Digital logic input clamp current (SEL1, SEL2, OE) when VI < 0 (3) -50 mA ICC Continuous current through VCC 100 mA IGND Continuous current through GND -100 mA Tstg Storage temperature -65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process.
6.2 ESD Ratings
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
6.3 Recommended Operating Conditions
VCC Supply voltage 2.3 5.5 V VI/O (D+, D-) Analog input/output voltage (TS5USBC412, TS5USBC412I) 0 24 V VI/O (D+, D-) Analog input/output voltage (TS5USBC410, TS5USBC410I) 0 20 V VI/O (D1, D1-, D2+, D2-) Analog input/output voltage 0 3.6 V VI Digital input voltage (SEL1, SEL2, OE) 0 5.5 V VO Digital output voltage (FLT) 0 5.5 V II/O (D+, D-, D1+, D1-, D2+, D2-) Analog input/output port continuous current -50 50 mA IOL Digital output current 3 mA TA Operating free-air temperature (Standard) (TS5USBC410, TS5USBC412) 0 70 ºC TA Operating free-air temperature (Industrial) (TS5USBC410I, TS5USBC412I) –40 85 ºC TJ Junction temperature –40 125 ºC
www.ti.com SCDS377B –MARCH 2018–REVISED JUNE 2018 Product Folder Links: TS5USBC41 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated (1) For more information about traditional and new thermalmetrics, see the Semiconductor and ICPackage Thermal Metrics application report.
6.4 Thermal Information
THERMAL METRIC (1) Device UNITYFF
12 PINS
RθJA Junction-to-ambient thermal resistance 91.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 0.8 °C/W RθJB Junction-to-board thermal resistance 22.8 °C/W ψJT Junction-to-top characterization parameter 0.5 °C/W ψJB Junction-to-board characterization parameter 23.0 °C/W
6.5 Electrical Characteristics
TA = –40°C to +85°C (Industrial), TA = 0℃ to 70℃ (Standard),VCC = 2.3 V to 5.5 V, GND = 0 V, Typical values are at VCC =
3.3 V, TA = 25°C, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER ICC-ACTIVE Active supply current. OE = 0 V SEL1, SEL2 = 0 V, 1.8 V or VCC 0 V < VI/O < 3.6 V 9 22 µA ICC-OVP Supply current during OVP condition. OE = 0 V SEL1, SEL2 = 0 V, 1.8 V or VCC VI/O > VPOS_THLD 10 35 μA ICC_PD Standby powered down supply current OE = 1.8 V or VCC SEL1 = 0 V, 1.8 V, or VCC SEL2 = 0 V, 1.8 V, or VCC 2 6 µA DC Characteristics RON ON-state resistance VI/O = 0.4 V ISINK = 8 mA Refer to ON-State Resistance Figure 5.6 9 Ω ΔRON ON-state resistance match between channels VI/O = 0.4 V ISINK = 8 mA Refer to ON-State Resistance Figure 0.075 0.48 Ω RON (FLAT) ON-state resistance flatness VI/O = 0 V to 0.4 V ISINK = 8 mA Refer to ON-State Resistance Figure 0.1 0.4 Ω IOFF I/O pin OFF leakage current OE = H VD± = 0 V or 3.6 V VCC = 2.3 V to 5.5 V VD1±or VD2± = 3.6 V or 0 V Refer to Off Leakage Figure -4 0.1 4 µA IOFF-20V D1/D2+/- pin OFF leakage current during OVP scenario on D+/- OE = H VD± = 20-V VCC = 2.3 V to 5.5 V VD1± or VD2± = 0 V Refer to Off Leakage Figure -0.5 0.5 µA IOFF-20V-DP/N D+/- pin OFF leakage current during OVP scenario OE = H VD± = 20-V VCC = 2.3 V to 5.5 V VD1± or VD2± = 0 V Refer to Off Leakage Figure 140 150 180 µA
SCDS377B –MARCH 2018–REVISED JUNE 2018 www.ti.com Product Folder Links: TS5USBC41 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Electrical Characteristics (continued) TA = –40°C to +85°C (Industrial), TA = 0℃ to 70℃ (Standard),VCC = 2.3 V to 5.5 V, GND = 0 V, Typical values are at VCC = PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IOFF-24V D1/D2 +/- pin OFF leakage current during OVP scenario on D+/-. OE = H VD± = 24-V VCC = 2.3 V to 5.5 V VD1± or VD2± = 0 V Refer to Off Leakage Figure -0.5 0.5 µA IOFF-24V-DPN D+/- pin OFF leakage current during OVP scenario. OE = H VD± = 0 V or 24-V VCC = 2.3 V to 5.5 V VD1± or VD2± = 0 V Refer to Off Leakage Figure 220 250 270 µA ION ON leakage current. VD± = 0 V or 3.6 V VD1± and VD2+/- = high-Z Refer to On Leakage Figure -5.5 0.25 7.5 µA Digital Characteristics VIH Input logic high SEL1, SEL2, OE 1.4 V VIL Input logic low SEL1, SEL2, OE 0.5 V VOL Output logic low FLT IOL = 3 mA 0.4 V IIH Input high leakage current SEL1, SEL2, OE = 1.8 V, VCC -1 1 5 μA IIL Input low leakage current SEL1, SEL2, OE = 0 V -1 ±0.2 5 μA RPD Internal pull-down resistor on digital input pins 6 MΩ CI Digital input capacitance SEL1, SEL2 = 0 V, 1.8 V or VCC f = 1 MHz 4 pF Protection VOVP_TH OVP positive threshold 4.4 4.8 5.2 V VOVP_HYST OVP threshold hysteresis 125 250 440 mV VCLAMP_V Maximum voltage to appear on D1± and D2± pins during OVP scenario (TS5USBC412, TS5USBC412I) VD± = 0 to 24 V tRISE and tFALL(10% to 90 %) = 100 ns RL = Open Switch on or off OE = 0 V 11.2 V VCLAMP_V Maximum voltage to appear on D1± and D2± pins during OVP scenario (TS5USBC412, TS5USBC412I) VD± = 0 to 24 V tRISE and tFALL(10% to 90 %) = 100 ns RL = 50Ω Switch on or off OE = 0 V 10.8 V VCLAMP_V Maximum voltage to appear on D1± and D2± pins during OVP scenario (TS5USBC410, TS5USBC410I) VD± = 0 to 20 V tRISE and tFALL(10% to 90 %) = 100 ns RL = Open Switch on or off OE = 0 V 10.8 V VCLAMP_V Maximum voltage to appear on D1± and D2± pins during OVP scenario (TS5USBC410, TS5USBC410I) VD± = 0 to 20 V tRISE and tFALL(10% to 90 %) = 100 ns RL = 50Ω Switch on or off OE = 0 V 9.8 V
www.ti.com SCDS377B –MARCH 2018–REVISED JUNE 2018 Product Folder Links: TS5USBC41 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated Electrical Characteristics (continued) TA = –40°C to +85°C (Industrial), TA = 0℃ to 70℃ (Standard),VCC = 2.3 V to 5.5 V, GND = 0 V, Typical values are at VCC = PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCLAMP_T Maximum OVP transient duration above 5 V (TS5USBC412, TS5USBC412I). VD± = 0 to 24 V tRISE and tFALL(10% to 90 %) = 100 ns RL = Open CL = 10pF Switch on or off OE = 0 V 75 100 ns VCLAMP_T Maximum OVP transient duration above 5 V (TS5USBC412, TS5USBC412I) VD± = 0 to 24 V tRISE and tFALL(10% to 90 %) = 100 ns RL = 50Ω CL = 10pF Switch on or off OE = 0 V 68 95 ns VCLAMP_T Maximum OVP transient duration above 5 V (TS5USBC410, TS5USBC410I) VD± = 0 to 20 V tRISE and tFALL(10% to 90 %) = 100 ns RL = Open CL = 10pF Switch on or off OE = 0 V 64 100 ns VCLAMP_T Maximum OVP transient duration above 5 V (TS5USBC410, TS5USBC410I) VD± = 0 to 20 V tRISE and tFALL(10% to 90 %) = 100 ns RL = 50Ω CL = 10pF Switch on or off OE = 0 V 55 95 ns tEN_OVP OVP enable time RPU = 10 kΩ to VCC (FLT) CL = 35 pF Refer to OVP Timing Diagram Figure 3 μs tREC_OVP OVP recovery time RPU = 10 kΩ to VCC (FLT) CL = 35 pF Refer to OVP Timing Diagram Figure 5 μs
SCDS377B –MARCH 2018–REVISED JUNE 2018 www.ti.com Product Folder Links: TS5USBC41 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated
6.6 Dynamic Characteristics
TA = –40°C to +85°C (Industrial), TA = 0℃ to 70℃ (Standard),VCC = 2.3 V to 5.5V, GND = 0V, Typical values are at VCC = 3.3 V, TA = 25°C, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT COFF D+, D- off capacitance VD+/- = 0 or 3.3 V, OE = VCC f = 240 MHz Switch OFF 1.2 1.6 3.2 pF D1+, D1-, D2+, D2- off capacitance VD+/- = 0 or 3.3 V, OE = VCC or OE = 0V with SEL1, SEL2 (switch not selected) f = 240 MHz Switch OFF or not selected 1.2 1.5 3.0 pF CON IO pins ON capacitance (TS5USBC412, TS5USBC412I) VD+/- = 0 or 3.3 V, f = 240 MHz Switch ON 2.0 2.5 3.9 pF CON IO pins ON capacitance (TS5USBC410, TS5USBC410I) VD+/- = 0 or 3.3 V, f = 240 MHz Switch ON 2.0 2.7 4 pF OISO Differential off isolation RL = 50 Ω CL = 5 pF f = 100 kHz Refer to Off Isolation Figure Switch OFF -95 dB RL = 50 Ω CL = 5 pF f = 240 MHz Refer to Off Isolation Figure Switch OFF -25 dB XTALK Channel to Channel crosstalk RL = 50 Ω CL = 5 pF f = 100 kHz Refer to Crosstalk Figure Switch ON -90 dB BW Bandwidth (TS5USBC412, TS5USBC412I) RL = 50 Ω; Refer to BW and Insertion Loss Figure Switch ON 1.2 GHz BW Bandwidth (TS5USBC410, TS5USBC410I) RL = 50 Ω; Refer to BW and Insertion Loss Figure Switch ON 1.1 GHz ILOSS Insertion loss RL = 50 Ω f = 240 MHz; Refer to BW and Insertion Loss Figure Switch ON -0.8 dB
6.7 Timing Requirements
TA = –40°C to +85°C (Industrial), TA = 0℃ to 70℃ (Standard),VCC = 2.3 V to 5.5V, GND = 0V, Typical values are atVCC = 3.3 V, TA = 25°C, (unless otherwisenoted) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT tSWITC H Switching time between channels (SEL1, SEL2 to output) VD+/- = 0.8 V Refer to Tswitch Timing Figure RL = 50 Ω, CL = 5 pF, VCC = 2.3 V to 5.5 V 0.8 2.5 µs tON Device turn on time (OE to output). VD+/- = 0.8 V Refer to Ton and Toff Figure 84 250 µs tOFF Device turn off time (OE to output) VD+/- = 0.8 V Refer to Ton and Toff Figure 0.75 1 µs tSK(P) Skew of opposite transitions of same output (between D+ and D- VD+/- = 0.4 V Refer to Tsk Figure RL = 50 Ω, CL = 1 pF, VCC = 2.3 V to 5.5 V 11 50 ps tPD Propagation delay. f - 240 MHz VD+/- = 0.4 V Refer to Tpd Figure RL = 50 Ω, CL = 5 pF, VCC = 2.3 V to 5.5 V 150 230 ps
6.8 Typical Characteristics
Figure 1. ON-Resistance vs Input Voltage Figure 2. IOFF Leakage Current vs Voltage on D± Figure 3. IOFF Leakage Current vs Voltage on D1± or D2± Figure 4. ION Leakage Current vs Voltage on D± or D1± or
7 Parameter Measurement Information
Figure 5. ON-State Resistance (RON) Figure 6. Off Leakage Figure 7. On Leakage (2) CL includes probe and jig capacitance. Figure 8. tSWITCH Timing
50 O D+
(2) CL includes probe and jig capacitance. Figure 9. tON, tOFF for OE Figure 10. Off Isolation Figure 11. Cross Talk
(2) CL includes probe and jig capacitance. Figure 15. tSK
8 Detailed Description
8.1 Overview
handling the USB 2.0 D+/- lines in a USB Type-C system as shown in Figure 16. Figure 16. USB Type-C Connector Pinout
8.2 Functional Block Diagram
20 V / 24 V
8.3 Feature Description
8.3.1 Powered-off Protection
and leakage remain within the Electrical Specifications.
8.3.2 Overvoltage Protection
20 V for TS5USBC412) to appear on an existing USB solution that could pass through the device and damage
components behind the device. Figure 17. Existing Solution Being Damaged by a Short
20 V / 24 9GRHVQ¶W
Figure 18. Protecting During a 20-V / 24-V Short Figure 19 is a waveform showing the voltage on the pins during an over-voltage scenario. Figure 19. Overvoltage Protection Waveform
8.4 Device Functional Modes
8.4.1 Pin Functions
Table 1. Function Table
9 Application and Implementation
validate and test their design implementation to confirm system functionality.
9.1 Application Information
and SEL2, TS5USBC41 can be used to cross switch single ended signals.
9.2 Typical Application
D1+/D1- channel is selected by default. The pull-down on OE enables the switch when power is applied. Figure 20. Typical Application
9.2.1 Design Requirements
internal pull-down resistor on OE enables the switch when power is applied to VCC.
9.2.2 Detailed Design Procedure
device. TI does recommend a 100-nF bypass capacitor placed close to TS5USBC41 VCC pin.
9.2.3 Application Curves
Figure 21. High Speed Eye Diagram With TS5USBC41 Figure 22. High Speed Eye Diagram Without TS5USBC41
10 Power Supply Recommendations
lower frequency noise to provide better load regulation across the frequency spectrum.
11 Layout
11.1 Layout Guidelines
- Place supply bypass capacitors as close to VCC pin as possible and avoid placing the bypass caps near the
- The high-speed D± must match and be no more than 4 inches long; otherwise, the eye diagram performance
characteristic differential impedance for optimal performance.
- Route the high-speed USB signals using a minimum of vias and corners which reduces signal reflections and
pair lines; through-hole pins are not recommended.
- When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This
reduces reflections on the signal traces by minimizing impedance discontinuities.
- Do not route USB traces under or near crystals, oscillators, clock signal generators, switching regulators,
mounting holes, magnetic devices or ICs that use or duplicate clock signals.
- Avoid stubs on the high-speed USB signals due to signal reflections. If a stub is unavoidable, then the stub
- Route all high-speed USB signal traces over continuous GND planes, with no interruptions.
- Avoid crossing over anti-etch, commonly found with plane splits.
- Due to high frequencies associated with the USB, a printed circuit board with at least four layers is
recommended; two signal layers separated by a ground and power layer as shown in Figure 23. Figure 23. Four-Layer Board Stack-Up number of signal vias reduces EMI by reducing inductance at high frequencies.
11.2 Layout Example
Figure 24. Layout Example
SCDS377B –MARCH 2018–REVISED JUNE 2018 www.ti.com Product Folder Links: TS5USBC41 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
- USB 2.0 Board Design and Layout Guidelines
- High-Speed Layout Guidelines Application Report
- High-Speed Interface Layout Guidelines
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments. USB Type-C is a trademark of USB Implementers Forum. All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com PACKAGE OUTLINE C0.625 MAX 0.23 0.17 0.8 TYP
1.2 TYP
0.4 TYP
0.4 TYP 12X 0.27 0.23 B 1.628 1.568 A 1.228 1.168 4224132/A 01/2018 DSBGA - 0.625 mm max height DIE SIZE BALL GRID ARRAY TS5USBC41YFF YFF0012-C01 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. NanoFree TM package configuration. NanoFree Is a trademark of Texas Instruments. BALL A1 CORNER SEATING PLANE BALL TYP 0.05 C A B C 1 2 3
0.015 C A B
SCALE 8.000
www.ti.com EXAMPLE BOARD LAYOUT 12X ( 0.23) (0.4) TYP (0.4) TYP ( 0.23) METAL
0.05 MAX
( 0.23) SOLDER MASK OPENING
0.05 MIN
DSBGA - 0.625 mm max height DIE SIZE BALL GRID ARRAY NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009). TS5USBC41YFF YFF0012-C01 SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:50X A B C 1 2 3 4 NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE EXPOSED METAL SOLDER MASK DEFINED EXPOSED METAL
www.ti.com EXAMPLE STENCIL DESIGN (0.4) TYP (0.4) TYP METAL TYP 4224132/A 01/2018 DSBGA - 0.625 mm max height DIE SIZE BALL GRID ARRAY NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. TS5USBC41YFF YFF0012-C01 SYMM SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:50X A B C 1 2 3 4
www.ti.com 10-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TS5USBC410IYFFR Active Production DSBGA (YFF) | 12 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 85 TU41 TS5USBC410IYFFR.A Active Production DSBGA (YFF) | 12 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 85 TU41 TS5USBC410IYFFT Active Production DSBGA (YFF) | 12 250 | SMALL T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 85 TU41 TS5USBC410IYFFT.A Active Production DSBGA (YFF) | 12 250 | SMALL T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 85 TU41 TS5USBC410YFFR Active Production DSBGA (YFF) | 12 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM 0 to 70 TU41 TS5USBC410YFFR.A Active Production DSBGA (YFF) | 12 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM 0 to 70 TU41 TS5USBC410YFFT Active Production DSBGA (YFF) | 12 250 | SMALL T&R Yes SNAGCU Level-1-260C-UNLIM 0 to 70 TU41 TS5USBC410YFFT.A Active Production DSBGA (YFF) | 12 250 | SMALL T&R Yes SNAGCU Level-1-260C-UNLIM 0 to 70 TU41 TS5USBC412IYFFR Active Production DSBGA (YFF) | 12 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 85 TU41 TS5USBC412IYFFR.A Active Production DSBGA (YFF) | 12 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 85 TU41 TS5USBC412IYFFT Active Production DSBGA (YFF) | 12 250 | SMALL T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 85 TU41 TS5USBC412IYFFT.A Active Production DSBGA (YFF) | 12 250 | SMALL T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 85 TU41 TS5USBC412YFFR Active Production DSBGA (YFF) | 12 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM 0 to 70 TU41 TS5USBC412YFFR.A Active Production DSBGA (YFF) | 12 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM 0 to 70 TU41 TS5USBC412YFFT Active Production DSBGA (YFF) | 12 250 | SMALL T&R Yes SNAGCU Level-1-260C-UNLIM 0 to 70 TU41 TS5USBC412YFFT.A Active Production DSBGA (YFF) | 12 250 | SMALL T&R Yes SNAGCU Level-1-260C-UNLIM 0 to 70 TU41 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. Addendum-Page 1
www.ti.com 10-Nov-2025 (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 31-Mar-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 31-Mar-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TS5USBC410IYFFR DSBGA YFF 12 3000 182.0 182.0 20.0 TS5USBC410IYFFR DSBGA YFF 12 3000 182.0 182.0 20.0 TS5USBC410IYFFT DSBGA YFF 12 250 182.0 182.0 20.0 TS5USBC410IYFFT DSBGA YFF 12 250 182.0 182.0 20.0 TS5USBC410YFFR DSBGA YFF 12 3000 182.0 182.0 20.0 TS5USBC410YFFT DSBGA YFF 12 250 182.0 182.0 20.0 TS5USBC412IYFFR DSBGA YFF 12 3000 182.0 182.0 20.0 TS5USBC412IYFFT DSBGA YFF 12 250 182.0 182.0 20.0 TS5USBC412YFFR DSBGA YFF 12 3000 182.0 182.0 20.0 TS5USBC412YFFT DSBGA YFF 12 250 182.0 182.0 20.0 Pack Materials-Page 2
IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you fully indemnify TI and its representatives against any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale, TI’s General Quality Guidelines, or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Unless TI explicitly designates a product as custom or customer-specified, TI products are standard, catalog, general purpose devices. TI objects to and rejects any additional or different terms you may propose. IMPORTANT NOTICE Copyright © 2025, Texas Instruments Incorporated Last updated 10/2025