TS5USBC400 TI | Alldatasheet
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VBUSDP_TDP_BDM_TDM_BGND USB Connector TS5USBC400 Copyright © 2017, Texas Instruments Incorporated UART USB D2- SEL1 SEL2 OE FLT Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TS5USBC400 SCDS374A –SEPTEMBER 2017–REVISED SEPTEMBER 2017 TS5USBC400Dual2:1USB2.0Mux/DeMuxwith16-VOvervoltageProtection
1 Features
1• Supply Range 2.3 V to 5.5 V
- Differential 2:1 or 1:2 Switch/Multiplexer
- 0-V to 16-V Overvoltage Protection (OVP) on Common Pins
- Powered Off Protection When VCC = 0 V
- Low RON of 9 Ω Maximum
- BW of 1.1 GHz Typical
- CON of 4.5 pF Typical
- Low Power Disable Mode
- 1.8-V Compatible Logic Inputs
- ESD Protection Exceeds JESD 22 – 2000-V Human Body Model (HBM)
- TS5USBC400: Standard Temperature Range of 0°C to 70°C
- TS5USBC400I: Industrial Temperature Range of -40°C to 85°C
- Small DSBGA Package
2 Applications
- Mobile
- PC/Notebook
- Tablet
- Anywhere a USB Type-C™ or Micro-B Connector is Used
3 Description
The TS5USBC400 is a bidirectional low-power dual port, high-speed, USB 2.0 analog switch with integrated protection for USB Type-C™ systems. The device is configured as a dual 2:1 or 1:2 switch and is optimized for handling the USB 2.0 D+/- lines in a USB Type-C™ systems. The TS5USBC400 protection on the I/O pins can tolerate up to 16V with automatic shutoff circuitry to protect system components behind the switch. The TS5USBC400 comes in a small 12 pin DSBGA package making it a perfect candidate for mobile and space constrained applications. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TS5USBC400 TS5USBC400I DSBGA (12) 1.582 mm × 1.182 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic
SCDS374A –SEPTEMBER 2017–REVISED SEPTEMBER 2017 www.ti.com Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Table of Contents
13 Mechanical, Packaging, and Orderable
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (September 2017) to Revision A Page
A B C 1 2 3 4 TS5USBC400 www.ti.com SCDS374A –SEPTEMBER 2017–REVISED SEPTEMBER 2017 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated
5 Pin Configuration and Functions
NAME NO. SEL1 A1 I Switch select1 (Active high) D+ A2 I/O Data switch input (Differential +) D– A3 I/O Data switch input (Differential –) FLT A4 O Fault indicator output pin (Active low) - open drain VCC B1 PWR Supply Voltage SEL2 B2 I Switch select2 (Active high) GND B3 GND Ground OE B4 I Output enable (Active low) D2+ C1 I/O Data switch output 2 (Differential +) D2– C2 I/O Data switch output 2 (Differential -) D1+ C3 I/O Data switch output 1 (Differential +) D1– C4 I/O Data switch output 1 (Differential -)
SCDS374A –SEPTEMBER 2017–REVISED SEPTEMBER 2017 www.ti.com Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum. (3) All voltages are with respect to ground, unless otherwise specified.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2) MIN MAX UNIT VCC Supply voltage(3) –0.5 6 V VI/O Input/Output DC voltage (D+, D-)(3) –0.5 18 V VI/O Input/Output DC voltage (D1+/D1-, D2+/D2-) (3) –0.5 6 V VI Digital input voltage (SEL1, SEL2, OE) –0.5 6 V VO Digital output voltage (FLT) –0.5 6 V IK Input-output port diode current (D+, D-, D1+, D1-, D2+, D2-) VIN < 0 –50 mA IIK Digital logic input clamp current (SEL1, SEL2, OE) (3) VI < 0 –50 mA ICC Continuous current through VCC 100 mA IGND Continuous current through GND –100 mA Tstg Storage temperature –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
6.3 Recommended Operating Conditions
VCC Supply voltage 2.3 5.5 V VI/O (D+, D-) Analog input/output voltage 0 18 V VI/O (D1, D1-, D2+, D2-) 0 3.6 V VI Digital input voltage (SEL1, SEL2, OE) 0 5.5 V VO Digital output voltage (FLT) 0 5.5 V II/O (D+, D-, D1+, D1-, D2+, D2-) Analog input/output port continuous current -50 50 mA IOL Digital output current 3 mA TA Operating free-air temperature (TS5USBC400) Standard 0 70 ºC TA Operating free-air temperature (TS5USBC400I) Industrial –40 85 ºC TJ Junction temperature –40 125 ºC
www.ti.com SCDS374A –SEPTEMBER 2017–REVISED SEPTEMBER 2017 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
6.4 Thermal Information
THERMAL METRIC (1) TS5USBC400 UNITYFP
12 PINS
RθJA Junction-to-ambient thermal resistance 91.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 0.8 °C/W RθJB Junction-to-board thermal resistance 22.8 °C/W ψJT Junction-to-top characterization parameter 0.5 °C/W ψJB Junction-to-board characterization parameter 23.0 °C/W
6.5 Electrical Characteristics
TA = –40°C to +85°C (Industrial), TA = 0℃ to 70℃ (Standard), VCC = 2.3 V to 5.5 V, GND = 0V, Typical values are at VCC =
3.3 V, TA = 25°C, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VCC Power supply voltage 2.3 5.5 V ICC Active supply current OE = 0 V SEL1, SEL2 = 0 V, 1.8 V or VCC 0 V < VI/O < 3.6 V 72 100 µA Supply current during OVP condition OE = 0 V SEL1, SEL2 = 0 V, 1.8 V or VCC VI/O > VPOS_THLD 80 120 µA ICC_PD Standby powered down supply current OE = 1.8 V or VCC SEL1 = 0 V, 1.8 V, or VCC SEL2 = 0 V, 1.8 V, or VCC 2.2 10 µA DC Characteristics RON ON-state resistance VI/O = 0.4 V ISINK = 8 mA Refer to ON-State Resistance Figure 5.6 9 Ω ΔRON ON-state resistance match between channels VI/O = 0.4 V ISINK = 8 mA Refer to ON-State Resistance Figure 0.07 0.3 Ω RON (FLAT) ON-state resistance flatness VI/O = 0 V to 0.4 V ISINK = 8 mA Refer to ON-State Resistance Figure 0.07 0.4 Ω IOFF I/O pin OFF leakage current VD± = 0 V or 3.6 V VCC = 2.3 V to 5.5 V VD1±or VD2+/- = 3.6 V or 0 V Refer to Off Leakage Figure -1 1.2 6 µA VD± = 0 V or 16 V VCC = 2.3 V to 5.5 V VD1± or VD2+/- = 0 V Refer to Off Leakage Figure -1 165 200 µA ION ON leakage current VD± = 0 V or 3.6 V VD1± and VD2+/- = high-Z Refer to On Leakage Figure -1 1.2 6 µA Digital Characteristics VIH Input logic high SEL1, SEL2, OE 1.4 V VIL Input logic low SEL1, SEL2, OE 0.5 V VOL Output logic low FLT IOL = 3 mA 0.4 V IIH Input high leakage current SEL1, SEL2, OE = 1.8 V, VCC -1 1 5 μA IIL Input low leakage current SEL1, SEL2, OE = 0 V -1 ±0.2 5 μA
SCDS374A –SEPTEMBER 2017–REVISED SEPTEMBER 2017 www.ti.com Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Electrical Characteristics (continued) TA = –40°C to +85°C (Industrial), TA = 0℃ to 70℃ (Standard), VCC = 2.3 V to 5.5 V, GND = 0V, Typical values are at VCC = PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RPD Internal pull-down resistor on digital input pins 6 MΩ CI Digital input capacitance SEL1, SEL2 = 0 V, 1.8 V or VCC f = 1 MHz 3.4 pF Protection VOVP_TH OVP positive threshold 4.5 4.8 5.2 V VOVP_HYST OVP threshold hysteresis 75 230 425 mV VCLAMP_V Maximum voltage to appear on D1± and D2± pins during OVP scenario VD± = 0 to 18 V tRISE and tFALL(10% to 90 %) = 100 ns RL = Open Switch on or off OE = 0 V 0 9.6 V VD± = 0 to 18 V tRISE and tFALL(10% to 90 %) = 100 ns RL = 50Ω Switch on or off OE = 0 V 0 9.0 V tEN_OVP OVP enable time RPU = 10 kΩ to VCC (FLT) CL = 35 pF Refer to OVP Timing Diagram Figure 0.6 3 μs tREC_OVP OVP recovery time RPU = 10 kΩ to VCC (FLT) CL = 35 pF Refer to OVP Timing Diagram Figure 1.5 5 μs
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6.6 Dynamic Characteristics
TA = –40°C to +85°C (Industrial), TA = 0℃ to 70℃ (Standard), VCC = 2.3 V to 5.5V, GND = 0V, Typical values are at VCC = PARAMETER TEST CONDITIONS MIN TYP MAX UNIT COFF D+, D- off capacitance VD+/- = 0 or 3.3 V, OE = VCC f = 240 MHz Switch OFF 1.2 3.5 6.2 pF D1+, D1-, D2+, D2- off capacitance VD+/- = 0 or 3.3 V, OE = VCC or OE = 0V with SEL1, SEL2 (switch not selected) f = 240 MHz Switch OFF or not selected 1.2 3.5 6.2 pF CON IO pins ON capacitance VD+/- = 0 or 3.3 V, f = 240 MHz Switch ON 1.4 4.5 6.2 pF OISO Differential off isolation RL = 50 Ω CL = 5 pF f = 100 kHz Refer to Off Isolation Figure Switch OFF -90 dB RL = 50 Ω CL = 5 pF f = 240 MHz Refer to Off Isolation Figure Switch OFF -22 dB XTALK Channel to Channel crosstalk RL = 50 Ω CL = 5 pF f = 100 kHz Refer to Crosstalk Figure Switch ON -90 dB BW Bandwidth RL = 50 Ω; Refer to BW and Insertion Loss Figure Switch ON 1.1 GHz ILOSS Insertion loss RL = 50 Ω f = 240 MHz; Refer to BW and Insertion Loss Figure Switch ON -0.7 dB
6.7 Timing Requirements
TA = –40°C to +85°C (Industrial), TA = 0℃ to 70℃ (Standard), VCC = 2.3 V to 5.5V, GND = 0V, Typical values are at VCC = PARAMETER TEST CONDITIONS MIN NOM MAX UNIT tswitch Switching time between channels (SEL1, SEL2 to output) VD+/- = 0.8 V Refer to Tswitch Timing Figure RL = 50 Ω, CL = 5 pF, VCC = 2.3 V to 5.5 V 0.45 1.2 µs ton Device turn on time (OE to output) VD+/- = 0.8 V Refer to Ton and Toff Figure 100 250 µs toff Device turn off time (OE to output) VD+/- = 0.8 V Refer to Ton and Toff Figure 0.35 1 µs tSK(P) Skew of opposite transitions of same output (between D+ and D-) VD+/- = 0.4 V Refer to Tsk Figure RL = 50 Ω, CL = 1 pF, VCC = 2.3 V to 5.5 V 9 50 ps tpd Propagation delay VD+/- = 0.4 V Refer to Tpd Figure RL = 50 Ω, CL = 5 pF, VCC = 2.3 V to 5.5 V 130 180 ps
6.8 Typical Characteristics
Figure 1. ON-Resistance vs Input Voltage
7 Parameter Measurement Information
Figure 2. ON-State Resistance (RON) Figure 3. Off Leakage Figure 4. On Leakage (2) CL includes probe and jig capacitance. Figure 5. tSWITCH Timing
50 O D+
(2) CL includes probe and jig capacitance. Figure 6. tON, tOFF for OE Figure 7. Off Isolation Figure 8. Cross Talk
(2) CL includes probe and jig capacitance. Figure 12. tSK
8 Detailed Description
8.1 Overview
handling the USB 2.0 D+/- lines in a USB Type-C system as shown in Figure 13. Figure 13. USB Type-C Connector Pinout fault condition where VBUS is shorted the D+ and D- pins on the connector.
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 Powered-off Protection
isolation, and leakage remain within the Electrical Specifications.
8.3.2 Overvoltage Protection
solution that could pass through the device and damage components behind the device. Figure 14. Existing Solution Being Damaged by a Short, 16 V The TS5USBC400 will open the switches and protect the rest of the system by blocking the 16 V as depicted in .
8.4 Device Functional Modes
8.4.1 Pin Functions
Table 1. Function Table
9 Application and Implementation
validate and test their design implementation to confirm system functionality.
9.1 Application Information
and SEL2, TS5USBC400 can be used to cross switch single ended signals.
9.2 Typical Application
the D1+/D1- channel is selected by default. The pull-down on OE enables the switch when power is applied. Figure 17. Typical TS5USBC400 Application
9.2.1 Design Requirements
internal pull-down resistor on OE enables the switch when power is applied to VCC.
9.2.2 Detailed Design Procedure
device. TI does recommend a 100nF bypass capacitor placed close to TS5USBC400 VCC pin.
9.2.3 Application Curves
Figure 18. High Speed Eye Diagram With TS5USBC400 Figure 19. High Speed Eye Diagram Without TS5USBC400
10 Power Supply Recommendations
lower frequency noise to provide better load regulation across the frequency spectrum.
11 Layout
11.1 Layout Guidelines
- Place supply bypass capacitors as close to VCC pin as possible and avoid placing the bypass caps near the
- The high-speed D± must match and be no more than 4 inches long; otherwise, the eye diagram performance
characteristic differential impedance for optimal performance.
- Route the high-speed USB signals using a minimum of vias and corners which reduces signal reflections and
pair lines; through-hole pins are not recommended.
- When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This
reduces reflections on the signal traces by minimizing impedance discontinuities.
- Do not route USB traces under or near crystals, oscillators, clock signal generators, switching regulators,
mounting holes, magnetic devices or ICs that use or duplicate clock signals.
- Avoid stubs on the high-speed USB signals because they cause signal reflections. If a stub is unavoidable,
then the stub must be less than 200 mm.
- Route all high-speed USB signal traces over continuous GND planes, with no interruptions.
- Avoid crossing over anti-etch, commonly found with plane splits.
- Due to high frequencies associated with the USB, a printed circuit board with at least four layers is
recommended; two signal layers separated by a ground and power layer as shown in Figure 20. Figure 20. Four-Layer Board Stack-Up number of signal vias reduces EMI by reducing inductance at high frequencies.
11.2 Layout Example
Figure 21. Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
- USB 2.0 Board Design and Layout Guidelines
- High-Speed Layout Guidelines Application Report
- High-Speed Interface Layout Guidelines
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments. USB Type-C is a trademark of USB Implementers Forum. All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com PACKAGE OUTLINE C0.5 MAX 0.19 0.13 0.8 TYP
1.2 TYP
0.4 TYP
0.4 TYP 12X 0.25 0.21 B 1.612 1.552 A 1.212 1.152 4223498/B 04/2017 DSBGA - 0.5 mm max heightYFP0012-C01 DIE SIZE BALL GRID ARRAY NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. BALL A1 CORNER SEATING PLANE BALL TYP 0.05 C A B C 1 2 3
0.015 C A B
SCALE 8.000 TS5USBC400 SCDS374A –SEPTEMBER 2017–REVISED SEPTEMBER 2017 www.ti.com Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
www.ti.com EXAMPLE BOARD LAYOUT 12X ( 0.23) (0.4) TYP (0.4) TYP ( 0.23) METAL
0.05 MAX
( 0.23) SOLDER MASK OPENING
0.05 MIN
DSBGA - 0.5 mm max heightYFP0012-C01 DIE SIZE BALL GRID ARRAY NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009). SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:50X A B C 1 2 3 4 NON-SOLDER MASK DEFINED (PREFERRED) NOT TO SCALE SOLDER MASK DETAILS EXPOSED METAL SOLDER MASK DEFINED EXPOSED METAL TS5USBC400 www.ti.com SCDS374A –SEPTEMBER 2017–REVISED SEPTEMBER 2017 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated
www.ti.com EXAMPLE STENCIL DESIGN (0.4) TYP (0.4) TYP METAL TYP 4223498/B 04/2017 DSBGA - 0.5 mm max heightYFP0012-C01 DIE SIZE BALL GRID ARRAY NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. SYMM SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:50X A B C 1 2 3 4 TS5USBC400 SCDS374A –SEPTEMBER 2017–REVISED SEPTEMBER 2017 www.ti.com Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TS5USBC400IYFPR Active Production DSBGA (YFP) | 12 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 85 USB4 TS5USBC400IYFPR.A Active Production DSBGA (YFP) | 12 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 85 USB4 TS5USBC400IYFPT Active Production DSBGA (YFP) | 12 250 | SMALL T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 85 USB4 TS5USBC400IYFPT.A Active Production DSBGA (YFP) | 12 250 | SMALL T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 85 USB4 TS5USBC400YFPR Active Production DSBGA (YFP) | 12 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM 0 to 70 USB4 TS5USBC400YFPR.A Active Production DSBGA (YFP) | 12 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 85 USB4 TS5USBC400YFPT Active Production DSBGA (YFP) | 12 250 | SMALL T&R Yes SNAGCU Level-1-260C-UNLIM 0 to 70 USB4 TS5USBC400YFPT.A Active Production DSBGA (YFP) | 12 250 | SMALL T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 85 USB4 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1
www.ti.com 23-May-2025 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 2-Apr-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 2-Apr-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TS5USBC400IYFPR DSBGA YFP 12 3000 182.0 182.0 20.0 TS5USBC400IYFPT DSBGA YFP 12 250 182.0 182.0 20.0 TS5USBC400YFPR DSBGA YFP 12 3000 182.0 182.0 20.0 TS5USBC400YFPT DSBGA YFP 12 250 182.0 182.0 20.0 Pack Materials-Page 2
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