TS5L100DR.A

TS5L100 TI | Alldatasheet

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Technical content

/C0084/C0083/C0053/C0076/C0049/C0048/C0048 /C0081/C0085/C0065/C0068 /C0083/C0080/C0068/C0084 /C0087/C0073/C0068/C0069/C0262/C0066/C0065/C0078/C0068/C0087/C0073/C0068/C0084/C0072 /C0076/C0065/C0078 /C0083/C0087/C0073/C0084/C0067/C0072 /C0087/C0073/C0084/C0072 /C0076/C0079/C0087 /C0079/C0078/C0262/C0083/C0084/C0065/C0084/C0069 /C0082/C0069/C0083/C0073/C0083/C0084/C0065/C0078/C0067/C0069 SCDS163A − MAY 2004 − REVISED MAY 2004 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Wide Bandwidth (BW = 300 MHz Min) /C0068Low Differential Crosstalk (XTALK = −60 dB Typ) /C0068Low Power Consumption (ICC = 3 /C0109A Max) /C0068Bidirectional Data Flow, With Near-Zero Propagation Delay /C0068Low ON-State Resistance (ron = 3 /C0087 Typ) /C0068VCC Operating Range From 6 V to 6.5 V /C0068Ioff Supports Partial-Power-Down Mode Operation /C0068Data and Control Inputs Provide Undershoot Clamp Diode /C0068Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II /C0068ESD Performance Tested Per JESD 22 − 2000-V Human-Body Model (A114-B, Class II) − 1000-V Charged-Device Model (C101) /C0068Suitable for Both 10 Base-T/100 Base-T Signaling D OR DBQ PACKAGE (TOP VIEW) S IA0 IA1 YA IB0 IB1 YB GND VCC E ID0 ID1 YD IC0 IC1 YC NC S IA0 IA1 YA IB0 IB1 YB GND NC NC VCC E ID0 ID1 YD IC IC1 YC NC PW PACKAGE (TOP VIEW) RGY PACKAGE (TOP VIEW) 11 6 E ID0 ID1 YD IC0 IC1 IA0 IA1 YA IB0 IB1 YB S YC V GND CC NC − No internal connection description/ordering information The TI TS5L100 LAN switch is a 4-bit 1-of-2 multiplexer/demultiplexer with a single switch-enable (E) input. When E is low, the switch is enabled and the I port is connected to the Y port. When E is high, the switch is disabled and the high-impedance state exists between the I and Y ports. The select (S) input controls the data path of the multiplexer/demultiplexer.

ORDERING INFORMATION

TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING QFN − RGY Tape and reel TS5L100RGYR TG100 SOIC − D Tube TS5L100D TS5L100 0°C to 70°C SOIC − D Tape and reel TS5L100DR TS5L100 0°C to 70°C SSOP (QSOP) − DBQ Tape and reel TS5L100DBQR TG100 TSSOP − PW Tube TS5L100PW TG100TSSOP − PW Tape and reel TS5L100PWR TG100 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright  2004, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046

/C0084/C0083/C0053/C0076/C0049/C0048/C0048 /C0081/C0085/C0065/C0068 /C0083/C0080/C0068/C0084 /C0087/C0073/C0068/C0069/C0262/C0066/C0065/C0078/C0068/C0087/C0073/C0068/C0084/C0072 /C0076/C0065/C0078 /C0083/C0087/C0073/C0084/C0067/C0072 /C0087/C0073/C0084/C0072 /C0076/C0079/C0087 /C0079/C0078/C0262/C0083/C0084/C0065/C0084/C0069 /C0082/C0069/C0083/C0073/C0083/C0084/C0065/C0078/C0067/C0069 SCDS163A − MAY 2004 − REVISED MAY 2004

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description/ordering information (continued) This device can be used to replace mechanical relays in LAN applications. This device has low ron, wide bandwidth, and low differential crosstalk, making it suitable for 10 Base-T, 100 Base-T, and various other LAN applications. This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, E should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTION TABLE INPUTS INPUT/OUTPUT FUNCTIONE S INPUT/OUTPUT YX FUNCTION L L IX0 YX = IX0 L HI X 1 YX = IX1 H X Z Disconnect PIN DESCRIPTIONS PIN NAME DESCRIPTION IAn−IDn Data I/Os S Select input E Enable input YA−YD Data I/Os

/C0084/C0083/C0053/C0076/C0049/C0048/C0048 /C0081/C0085/C0065/C0068 /C0083/C0080/C0068/C0084 /C0087/C0073/C0068/C0069/C0262/C0066/C0065/C0078/C0068/C0087/C0073/C0068/C0084/C0072 /C0076/C0065/C0078 /C0083/C0087/C0073/C0084/C0067/C0072 /C0087/C0073/C0084/C0072 /C0076/C0079/C0087 /C0079/C0078/C0262/C0083/C0084/C0065/C0084/C0069 /C0082/C0069/C0083/C0073/C0083/C0084/C0065/C0078/C0067/C0069 SCDS163A − MAY 2004 − REVISED MAY 2004 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 logic diagram (positive logic) YA IA0 IA1 IB0 IB1 IC0 IC1 ID0 ID1 E S YC YB YD Control Logic

/C0084/C0083/C0053/C0076/C0049/C0048/C0048 /C0081/C0085/C0065/C0068 /C0083/C0080/C0068/C0084 /C0087/C0073/C0068/C0069/C0262/C0066/C0065/C0078/C0068/C0087/C0073/C0068/C0084/C0072 /C0076/C0065/C0078 /C0083/C0087/C0073/C0084/C0067/C0072 /C0087/C0073/C0084/C0072 /C0076/C0079/C0087 /C0079/C0078/C0262/C0083/C0084/C0065/C0084/C0069 /C0082/C0069/C0083/C0073/C0083/C0084/C0065/C0078/C0067/C0069 SCDS163A − MAY 2004 − REVISED MAY 2004

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to ground, unless otherwise specified. 2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. VI and VO are used to denote specific conditions for VI/O. 4. II and IO are used to denote specific conditions for II/O. 5. The package thermal impedance is calculated in accordance with JESD 51-7. 6. The package thermal impedance is calculated in accordance with JESD 51-5. recommended operating conditions (see Note 7) MIN MAX UNIT VCC Supply voltage 6 6.5 V VIH High-level control input voltage (E, S) 2.5 6.5 V VIL Low-level control input voltage (E, S) 0 0.8 V TA Operating free-air temperature 0 70 °C NOTE 7: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

/C0084/C0083/C0053/C0076/C0049/C0048/C0048 /C0081/C0085/C0065/C0068 /C0083/C0080/C0068/C0084 /C0087/C0073/C0068/C0069/C0262/C0066/C0065/C0078/C0068/C0087/C0073/C0068/C0084/C0072 /C0076/C0065/C0078 /C0083/C0087/C0073/C0084/C0067/C0072 /C0087/C0073/C0084/C0072 /C0076/C0079/C0087 /C0079/C0078/C0262/C0083/C0084/C0065/C0084/C0069 /C0082/C0069/C0083/C0073/C0083/C0084/C0065/C0078/C0067/C0069 SCDS163A − MAY 2004 − REVISED MAY 2004 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range, VCC = 6 V to 6.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VIK E, S VCC = 6 V, IIN = −18 mA −1.8 V Vhys E, S 150 mV VO VI = 4.5 V, E = low, R L = 100 Ω, see Figure 11 3.7 4.06 V IIH E, S VCC = 6.5 V, VIN = VCC ±1 µA IIL E, S VCC = 6.5 V, VIN = GND ±1 µA IOZ ‡ VCC = 6.5 V, VO = 0 to 6.5 V, VI = 0, Switch OFF ±1 µA IOS § VCC = 6.5 V, VO = 0 to 0.5 VCC , VI = 0, Switch ON 50 mA Ioff VCC = 0, VO = 0 to 6.5 V, VI = 0 1 µA ICC VCC = 6.5 V, II/O = 0, Switch ON or OFF 3 µA ∆ICC E, S VCC = 6.5 V, One input at 3.4 V, Other inputs at VCC or GND 6 mA ICCD VCC = 6.5 V, I and Y ports open, VIN input switching 50% duty cycle 0.35 mA/ MHz C IN E, S f = 1 MHz 3.5 pF C OFF I port VI = 0, f = 1 MHz, Switch OFF 4.5 pFC OFF Y port VI = 0, f = 1 MHz, Outputs open, Switch OFF 6.5 pF C ON VI = 0, f = 1 MHz, Outputs open, Switch ON 14 pF ron VI = 4.5 V, Switch ON, R L = 100 Ω, see Figure 11 7.5 11.2 19 Ωron M2 VI = 4.5 V, Switch ON, R L = 100 Ω, see Figure 11 2 3 6 Ω ∆ron VI = 4.5 V, Switch ON 1 2 Ω VI, VO , II, and IO refer to I/O pins. VIN refers to the control inputs. † All typical values are at VCC = 6.2 V (unless otherwise noted), TA = 25°C. ‡ For I/O ports, IOZ includes the input leakage current. § The IOS test is applicable to only one ON channel at a time. The duration of this test is less than one second. switching characteristics over recommended operating free-air temperature range, VCC = 6 V to 6.5 V, RL = 100 Ω, CL = 35 pF (unless otherwise noted) (see Figure 7) PARAMETER FROM (INPUT) TO (OUTPUT) MIN MAX UNIT tON S Y 7 ns tOFF S Y 4 ns † All typical values are at VCC = 6.2 V (unless otherwise noted), TA = 25°C. dynamic characteristics over recommended operating free-air temperature range, VCC = 6 V to 6.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT XTALK (Diff) R L = 100 Ω, f = 10 MHz, see Figure 12, tr = tf = 2 ns −40 −60 dB XTALK R L = 100 Ω, f = 30 MHz, see Figure 9 −50 dB O IRR R L = 100 Ω, f = 30 MHz, see Figure 10 −40 dB BW R L = 100 Ω, see Figure 8 350 MHz † All typical values are at VCC = 6.2 V (unless otherwise noted), TA = 25°C.

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Figure 1. ron and VO vs VI Over Temperature (VCC = 6 V)

Figure 2. ron and VO vs VI (VCC = 6.2 V and TA = 25/C0053C)

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Figure 3. Gain/Phase vs Frequency

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Figure 6. Differential Crosstalk

NOTES: A. C L includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. C. The outputs are measured one at a time, with one transition per measurement. Figure 7. Test Circuit and Voltage Waveforms

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Figure 8. Test Circuit for Frequency Response (BW) input, the output is measured at IA0. All unused analog I/O ports are left open.

† A 50-Ω termination resistor is needed for the network analyzer. Figure 9. Test Circuit for Crosstalk (XTALK ) are connected to GND through 50-Ω pulldown resistors.

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† A 50-Ω termination resistor is needed for the network analyzer. Figure 10. Test Circuit for Off Isolation (OIRR) GND through 50-Ω pulldown resistors.

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TS5L100D Active Production SOIC (D) | 16 40 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TS5L100 TS5L100D.A Active Production SOIC (D) | 16 40 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TS5L100 TS5L100DBQR Active Production SSOP (DBQ) | 16 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR 0 to 70 TG100 TS5L100DBQR.A Active Production SSOP (DBQ) | 16 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR 0 to 70 TG100 TS5L100DR Active Production SOIC (D) | 16 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TS5L100 TS5L100DR.A Active Production SOIC (D) | 16 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TS5L100 TS5L100PWR Active Production TSSOP (PW) | 20 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TG100 TS5L100PWR.A Active Production TSSOP (PW) | 20 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TG100 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

www.ti.com 23-May-2025 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TS5L100DBQR SSOP DBQ 16 2500 353.0 353.0 32.0 TS5L100DR SOIC D 16 2500 340.5 336.1 32.0 TS5L100PWR TSSOP PW 20 2000 356.0 356.0 35.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) TS5L100D D SOIC 16 40 507 8 3940 4.32 TS5L100D.A D SOIC 16 40 507 8 3940 4.32 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C TYP-.244.228 -6.195.80[ ] .069 MAX [1.75] 14X .0250 [0.635] 16X -.012.008 -0.300.21[ ] .175 [4.45] TYP-.010.005 -0.250.13[ ] - 8 -.010.004 -0.250.11[ ] (.041 ) [1.04] .010 [0.25] GAGE PLANE -.035.016 -0.880.41[ ] A NOTE 3 -.197.189 -5.004.81[ ] B NOTE 4 -.157.150 -3.983.81[ ] SSOP - 1.75 mm max heightDBQ0016A SHRINK SMALL-OUTLINE PACKAGE 4214846/A 03/2014 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 inch, per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MO-137, variation AB. 1 16 .007 [0.17] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .002 MAX [0.05] ALL AROUND .002 MIN [0.05] ALL AROUND (.213) [5.4] 14X (.0250 ) [0.635] 16X (.063) [1.6] 16X (.016 ) [0.41] SSOP - 1.75 mm max heightDBQ0016A SHRINK SMALL-OUTLINE PACKAGE 4214846/A 03/2014 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS OPENING SOLDER MASK METAL SOLDER MASK DEFINED LAND PATTERN EXAMPLE SCALE:8X SYMM 8 9 SEE DETAILS

www.ti.com EXAMPLE STENCIL DESIGN 16X (.063) [1.6] 16X (.016 ) [0.41] 14X (.0250 ) [0.635] (.213) [5.4] SSOP - 1.75 mm max heightDBQ0016A SHRINK SMALL-OUTLINE PACKAGE 4214846/A 03/2014 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.127 MM] THICK STENCIL SCALE:8X SYMM SYMM 8 9

www.ti.com PACKAGE OUTLINE C 18X 0.65 5.85 20X 0.30 0.19 TYP6.6 6.2

1.2 MAX

0.15 0.05 0.25 GAGE PLANE -80 B NOTE 4 4.5 4.3 A NOTE 3 6.6 6.4 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0020A SMALL OUTLINE PACKAGE 4220206/A 02/2017

0.1 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

20X (1.5) 20X (0.45) 18X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0020A SMALL OUTLINE PACKAGE 4220206/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 10 11 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 20X (1.5) 20X (0.45) 18X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0020A SMALL OUTLINE PACKAGE 4220206/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 10 11

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