TS5A22364YZPR.B

TS5A22364 TI | Alldatasheet

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OUT– OUT– NO1 TS5A22364 Audio Source 1 Audio Source 2 8- SpeakerΩ Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TS5A22364 SCDS261H –MARCH 2008–REVISED JUNE 2017 TS5A223640.65-ΩDualSPDTAnalogSwitchesWithNegativeSignalingCapability

1 Features

1• Specified Break-Before-Make Switching

• Negative Signaling Capability: Maximum Swing from –2.75 V to 2.75 V (VCC = 2.75 V)
• Internal Shunt Switch Prevents Audible Click-and- Pop When Switching Between Two Sources
• Low ON-State Resistance (0.65 Ω Typical)
• Low Charge Injection
• Excellent ON-State Resistance Matching
• 2.3-V to 5.5-V Power Supply (VCC)
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Performance Tested Per JESD 22 – 2500-V Human-Body Model (A114-B, Class II) – 1500-V Charged-Device Model (C101) – 200-V Machine Model (A115-A)

2 Applications

• Cell Phones
• PDAs
• Portable Instrumentation
• Audio Routing
• Medical Imaging

3 Description

The TS5A22364 is a bidirectional, 2-channel, single- pole double-throw (SPDT) analog switch designed to operate from 2.3 V to 5.5 V. The device features negative signal capability that allows signals below ground to pass through the switch without distortion. Additionally, the TS5A22364 includes an internal shunt switch, which automatically discharges any capacitance at the NC or NO terminals when they are unconnected to COM. This reduces the audible click/pop noise when switching between two sources. The break-before-make feature prevents signal distortion during the transferring of a signal from one path to another. Low ON-state resistance, excellent channel-to-channel ON-state resistance matching, and minimal total harmonic distortion (THD) performance are ideal for audio applications. The 3.00-mm x 3.00-mm DRC package is also available as a nonmagnetic package for medical imaging applications. Device Information (1) PART NUMBER PACKAGE BODY SIZE (NOM) TS5A22364 VSON (10) 3.00 mm × 3.00 mm DSBGA (10) 1.90 mm × 1.40 mm VSSOP (10) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Schematic

SCDS261H –MARCH 2008–REVISED JUNE 2017 www.ti.com Product Folder Links: TS5A22364 Submit Documentation Feedback Copyright © 2008–2017, Texas Instruments Incorporated Table of Contents

12.1 Receiving Notification of Documentation Updates 20

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision G (September 2015) to Revision H Page Changes from Revision F (June 2015) to Revision G Page Changes from Revision E (May 2013) to Revision F Page

• Added Pin Configuration and Functions section, ESD Ratings table, Recommended Operating Conditions table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
• Split the TS5A22364 and TS5A22362 into separate datasheets and added verbiage to clarify the operation of the Changes from Revision D (November 2011) to Revision E Page Changes from Revision C (April 2010) to Revision D Page

Laser Marking View Bump View B C D 3 2 1 A B C D 1 2 3 A NO2 COM2 NC2 IN2 VCC NO1 COM1 NC1 IN1 GND Exposed Center Pad VCC NO1 COM1 NC1 IN1 NO2 COM2 NC2 IN2 GND TS5A22364 www.ti.com SCDS261H –MARCH 2008–REVISED JUNE 2017 Product Folder Links: TS5A22364 Submit Documentation FeedbackCopyright © 2008–2017, Texas Instruments Incorporated

5 Pin Configuration and Functions

*The exposed center pad, if used, must be connected as a secondary GND or left electrically open. 10-Pin VSSOP Top View 10-Pin DSBGA Top View Pin Functions PIN TYPE DESCRIPTION NAME DRC / DGS YZP VCC 1 A2 — Power Supply NO1 2 A3 I/O Normally Open (NO) signal path, Switch 1 COM1 3 B3 I/O Common signal path, Switch 1 NC1 4 C3 I/O Normally Closed (NC) signal path, Switch 1 IN1 5 D3 I Digital control pin to connect COM1 to NO1, Switch 1 GND 6 D2 — Ground IN2 7 D1 I Digital control pin to connect COM2 to NO2, Switch 2 NC2 8 C1 I/O Normally Closed (NC) signal path, Switch 2 COM2 9 B1 I/O Common signal path, Switch 2 NO2 10 A1 I/O Normally Open (NO) signal Path, Switch 2

SCDS261H –MARCH 2008–REVISED JUNE 2017 www.ti.com Product Folder Links: TS5A22364 Submit Documentation Feedback Copyright © 2008–2017, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions . Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability (2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum (3) All voltages are with respect to ground, unless otherwise specified. (4) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. (5) This value is limited to 5.5 V maximum. (6) Pulse at 1-ms duration < 10% duty cycle. (7) VCC = 3.0 V to 5.0 V, TA = –40°C to 85°C. (8) For YZP package only.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1) (2) MIN MAX UNIT VCC Supply voltage (3) –0.5 6 V VNC VNO VCOM Analog voltage (3) (4) (5) VCC – 6 VCC + 0.5 V II/OK Analog port diode current VNC, VNO, VCOM < 0 or VNC, VNO, VCOM > VCC –50 50 mA INC INO ICOM ON-state switch current VNC, VNO, VCOM = 0 to VCC –150 150 mAON-state peak switch current (6) –300 300 IRSH OFF-state switch Shunt Resistor current –20 20 INC (3) (7) (8) INO (3) (7) (8) ICOM (3) (7) (8) ON-state switch current VNC, VNO, VCOM = 0 to VCC –350 350 mA ON-state peak switch current (6) –500 500 VIN Digital input voltage range –0.5 6.5 V IIK Digital input clamp current (3) (4) VI < 0 –50 50 mA ICC IGND Continuous current through VCCor GND –100 100 mA Tstg Storage temperature –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2500 VCharged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1500

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage 2.3 5.5 V VNC VNO VCOM Signal path voltage VCC – 5.5 VCC V VIN Digital control GND 5.5 V

www.ti.com SCDS261H –MARCH 2008–REVISED JUNE 2017 Product Folder Links: TS5A22364 Submit Documentation FeedbackCopyright © 2008–2017, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC (1) TS5A22364 UNITDGS (VSSOP) DRC (VSON) YZP (DSBGA)

10 PINS 10 PINS 10 PINS

RθJA Junction-to-ambient thermal resistance 163.3 44.3 90.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 56.4 70.1 0.3 °C/W RθJB Junction-to-board thermal resistance 83.1 19.3 8.3 °C/W ψJT Junction-to-top characterization parameter 6.8 2.0 3.2 °C/W ψJB Junction-to-board characterization parameter 81.8 19.4 8.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 6.2 N/A °C/W (1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum (2) All unused digital inputs of the device must be held at VCC or GND to ensure proper device operation. Floating digital inputs will cause excessive current consumption. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, SCBA004. 6.5 Electrical Characteristics for 2.5-V Supply VCC = 2.3 V to 2.7 V, TA = –40°C to 85°C (unless otherwise noted) (1) PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX UNIT ANALOG SWITCH VCOM, VNO, VNC Analog signal range VCC – 5.5 VCC V Ron ON-state resistance VNC or VNO = VCC, 1.5 V, VCC – 5.5 V ICOM = –100 mA, COM to NO or NC, see Figure 13 25°C 2.3 V 0.65 0.94 Ω Full 1.3 25°C 2.7 V 0.65 0.94 Ω Full 1.3 ΔRon ON-state resistance match between channels VNC or VNO = 1.5 V, ICOM = –100 mA, COM to NO or NC, see Figure 13 25°C 2.7 V 0.023 0.11 Ω Full 0.15 Ron(flat) ON-state resistance flatness VNC or VNO = VCC, 1.5 V, VCC – 5.5 V ICOM = –100 mA, COM to NO or NC, see Figure 13 25°C 2.7 V 0.18 0.46 Ω Full 0.5 RSH Shunt switch resistance INO or INC = 10 mA Full 2.7 V 25 50 Ω ICOM(ON) COM ON leakage current VNC and VNO = Floating, VCOM = VCC,VCC – 5.5 V, See Figure 15 25°C 2.7 V –50 50 nA Full –375 375 DIGITAL CONTROL INPUTS (IN) (2) VIH Input logic high Full 1.4 5.5 V VIL Input logic low 0.4 IIH, IIL Input leakage current VIN = VCC or 0 25°C 2.7 V –250 250 nA Full –250 250

SCDS261H –MARCH 2008–REVISED JUNE 2017 www.ti.com Product Folder Links: TS5A22364 Submit Documentation Feedback Copyright © 2008–2017, Texas Instruments Incorporated Electrical Characteristics for 2.5-V Supply (continued) VCC = 2.3 V to 2.7 V, TA = –40°C to 85°C (unless otherwise noted) (1) PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX UNIT DYNAMIC tON Turnon time VCOM = VCC, RL = 300 Ω, CL = 35 pF, see Figure 17 25°C 2.5 V 44 80 ns Full 2.3 V to

2.7 V 120

tOFF Turnoff time VCOM = VCC, RL = 300 Ω, CL = 35 pF, see Figure 17 25°C 2.5 V 22 70 ns Full 2.3 V to

2.7 V 70

time See Figure 18 25°C 2.5 V 1 7 ns QC Charge injection VGEN = 0, RGEN = 0 CL = 1 nF, see Figure 22 25°C 2.5 V 215 pC CCOM(ON) NC, NO, COM ON capacitance VCOM = VCC or GND, Switch ON, f = 10 MHz See Figure 16 25°C 2.5 V 370 pF CI Digital input capacitance VIN = VCC or GND See Figure 16 25°C 2.5 V 2.6 pF BW Bandwidth RL = 50 Ω, –3 dB 25°C 2.5 V 17 MHz OISO OFF isolation RL = 50 Ω f = 100 kHz, see Figure 20 25°C 2.5 V –66 dB XTALK Crosstalk RL = 50 Ω f = 100 kHz, see Figure 21 25°C 2.5 V –75 dB THD Total harmonic distortion RL = 600 Ω, CL = 35 pF, f = 20 Hz to 20 kHz, see Figure 23 25°C 2.5 V 0.01% SUPPLY ICC Positive supply current VCOM and VIN = VCC or GND, VNC and VNO = Floating 25°C 2.7 V 0.2 1.1 μA Full 1.3 VCOM = VCC – 5.5, VIN = VCC or GND, VNC and VNO = Floating Full 2.7 V 3.3 μA (1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum (2) All digital inputs of the device must be held at VCC or GND to ensure proper device operation. Floating digital inputs will cause excessive current consumption. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, SCBA004. 6.6 Electrical Characteristics for 3.3-V Supply VCC = 3 V to 3.6 V, TA = –40°C to 85°C (unless otherwise noted) (1) PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX UNIT ANALOG SWITCH VCOM, VNO, VNC Analog signal range VCC – 5.5 VCC V Ron ON-state resistance VNC or VNO ≤ VCC, 1.5 V, VCC – 5.5 V, ICOM = –100 mA, COM to NO or NC, see Figure 13 25°C 3 V 0.61 0.87 Ω Full 0.97 ΔRon ON-state resistance match between channels VNC or VNO = 1.5 V, ICOM = –100 mA, COM to NO or NC, see Figure 13 25°C 3 V 0.024 0.13 Ω Full 0.13 Ron(flat) ON-state resistance flatness VNC or VNO ≤ VCC, 1.5 V, VCC – 5.5 V, ICOM = –100 mA, COM to NO or NC, see Figure 13 25°C 3 V 0.12 0.46 Ω Full 0.5 RSH Shunt switch resistance INO or INC = 10 mA Full 3 V 25 37 Ω ICOM(ON) COM ON leakage current VNC and VNO = Open, VCOM = VCC,VCC – 5.5 V, COM to NO or NC, see Figure 15 25°C 3.6 V –50 50 nA Full –375 375 DIGITAL CONTROL INPUTS (IN) (2) VIH Input logic high Full 1.4 5.5 V VIL Input logic low 0.6 IIH, IIL Input leakage current VIN = VCC or 0 25°C 3.6 V –250 250 nA Full –250 250

www.ti.com SCDS261H –MARCH 2008–REVISED JUNE 2017 Product Folder Links: TS5A22364 Submit Documentation FeedbackCopyright © 2008–2017, Texas Instruments Incorporated Electrical Characteristics for 3.3-V Supply (continued) VCC = 3 V to 3.6 V, TA = –40°C to 85°C (unless otherwise noted) (1) PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX UNIT DYNAMIC tON Turnon time VCOM = VCC, RL = 300 Ω, CL = 35 pF, see Figure 17 25°C 3.3 V 34 80 ns Full 3 V to

3.6 V 120

tOFF Turnoff time VCOM = VCC, RL = 300 Ω, CL = 35 pF, see Figure 17 25°C 3.3 V 19 70 ns Full 3 V to

3.6 V 70

time See Figure 18 25°C 3.3 V 1 7 ns QC Charge injection VGEN = 0, RGEN = 0, CL = 1 nF, see Figure 22 25°C 3.3 V 300 pC CCOM(ON) NC, NO, COM ON capacitance VCOM = VCC or GND, f = 10 MHz See Figure 16 25°C 3.3 V 370 pF CI Digital input capacitance VIN = VCC or GND See Figure 16 25°C 3.3 V 2.6 pF BW Bandwidth RL = 50 Ω, –3 dB Switch ON, 25°C 3.3 V 17.5 MHz OISO OFF isolation RL = 50 Ω, f = 100 kHz, see Figure 20 25°C 3.3 V –68 dB XTALK Crosstalk RL = 50 Ω, f = 100 kHz, see Figure 21 25°C 3.3 V –76 dB THD Total harmonic distortion RL = 600 Ω, CL = 35 pF, f = 20 Hz to 20 kHz, see Figure 23 25°C 3.3 V 0.008% SUPPLY ICC Positive supply current VCOM and VIN = VCC or GND, VNC and VNO = Floating 25°C 3.6 V 0.1 1.2 μA Full 1.3 VCOM = VCC – 5.5 V, VIN = VCC or GND, VNC and VNO = Floating Full 3.6 V 3.4 μA

SCDS261H –MARCH 2008–REVISED JUNE 2017 www.ti.com Product Folder Links: TS5A22364 Submit Documentation Feedback Copyright © 2008–2017, Texas Instruments Incorporated (1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum (2) All unused digital inputs of the device must be held at VCC or GND to ensure proper device operation. Floating digital inputs will cause excessive current consumption. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, SCBA004.

6.7 Electrical Characteristics for 5-V Supply

VCC = 4.5 V to 5.5 V, TA = –40°C to 85°C (unless otherwise noted) (1) PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX UNIT ANALOG SWITCH VCOM, VNO, VNC Analog signal range VCC – 5.5 VCC V Ron ON-state resistance VNC or VNO = VCC, 1.6 V, VCC = –5.5 V, ICOM = –100 mA, COM to NO or NC, see Figure 13 25°C 4.5 V 0.52 0.74 Ω Full 0.83 ΔRon ON-state resistance match between channels VNC or VNO = 1.6 V, ICOM = –100 mA, COM to NO or NC, see Figure 13 25°C 4.5 V 0.04 0.23 Ω Full 0.30 Ron(flat) ON-state resistance flatness VNC or VNO = VCC, 1.6 V, VCC = –5.5 V, ICOM = –100 mA, COM to NO or NC, see Figure 13 25°C 4.5 V 0.076 0.46 Ω Full 0.5 RSH Shunt switch resistance INO or INC = 10 mA Full 4.5 V 16 36 Ω ICOM(ON) COM ON leakage current VNC and VNO = Open, VCOM = VCC, VCC – 5.5 V, See Figure 15 25°C 5.5 V –50 50 nA Full –375 375 DIGITAL CONTROL INPUTS (IN) (2) VIH Input logic high Full 2.4 5.5 V VIL Input logic low 0.8 IIH, IIL Input leakage current VIN = VCC or 0 25°C 5.5 V –250 250 nA Full –250 250 DYNAMIC tON Turnon time VCOM = VCC, RL = 300 Ω, CL = 35 pF, see Figure 17 25°C 5 V 27 80 ns Full 4.5 V to

5.5 V 80

tOFF Turnoff time VCOM = VCC, RL = 300 Ω, CL = 35 pF, see Figure 17 25°C 5 V 13 70 ns Full 4.5 V to

5.5 V 70

VNC = VNO = VCC/2 RL = 300 Ω, CL = 35 pF, 25°C 5 V 1 3.5 ns QC Charge injection VGEN = 0, RGEN = 0, CL = 1 nF, see Figure 22 25°C 5 V 500 pC CCOM(ON) NC, NO, COM ON capacitance VCOM = VCC or GND, See Figure 16 25°C 5 V 370 pF CI Digital input capacitance VIN = VCC or GND See Figure 16 25°C 5 V 2.6 pF BW Bandwidth RL = 50 Ω, 25°C 5 V 18.3 MHz OISO OFF isolation RL = 50 Ω, f = 100 kHz, see Figure 20 25°C 5 V –70 dB XTALK Crosstalk RL = 50 Ω, f = 100 kHz, see Figure 21 25°C 5 V –78 dB THD Total harmonic distortion RL = 600 Ω, CL = 35 pF, f = 20 Hz to 20 kHz, see Figure 23 25°C 5 V 0.009% SUPPLY ICC Positive supply current VCOM and VIN = VCC or GND, VNC and VNO = Floating 25°C 5.5 V 0.2 1.3 μA Full 3.5 VCOM = VCC – 5.5, VIN = VCC or GND, VNC and VNO = Floating Full 5

6.8 Typical Characteristics

Figure 1. Ron vs VCOM Figure 2. Ron vs VCOM (VCC = 2.7 V) Figure 3. Ron vs VCOM (VCC = 3.3 V) Figure 4. Ron vs VCOM (VCC = 5 V) Figure 5. Insertion Loss Figure 6. Off Isolation vs Frequency

7 Parameter Measurement Information

Figure 13. ON-State Resistance (Ron) Figure 14. OFF-State Leakage Current (ICOM(OFF), INO(OFF)) Figure 15. ON-State Leakage Current

OUT– OUT– NO1 TS5A22364 Audio Source 1 Audio Source 2 8- SpeakerΩ TS5A22364 www.ti.com SCDS261H –MARCH 2008–REVISED JUNE 2017 Product Folder Links: TS5A22364 Submit Documentation FeedbackCopyright © 2008–2017, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The TS5A22364 is a bidirectional 2-channel, single-pole, double-throw (SPDT) analog switch designed to operate from 2.3-V to 5.5-V power supply. The device features negative signal swing capability that allows signals below ground to pass through the switch without distortion. Additionally, the TS5A22364 includes an internal shunt switch, which automatically discharges any capacitance at the NC or NO terminals when they are not connected to COM. Discharging the capacitance reduces the audible click and pop noise when switching between two sources. The break-before-make feature prevents signal distortion during the transferring of a signal from one path to another. Low ON-state resistance, excellent channel-to-channel ON-state resistance matching, and minimal total harmonic distortion (THD) performance are ideal for audio applications.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Click and Pop Reduction

thereby reducing the clicks and pops.

8.3.2 Negative Signal Swing Capability

Table 1 shows the input/output signal swing the user can get with different supply voltages. Table 1. Input/Output Signal Swing

8.4 Device Functional Modes

The function table for TS5A22364 is shown in Table 2. Table 2. Function Table

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.2 Typical Application

recommends that during operation, the current through the shunt path should be limited to ±10 mA. Figure 24. Shunt Switch (TS5A22364)

9.2.1 Design Requirements

high current consumption that could result if the logic control pins are left floating.

9.2.2 Detailed Design Procedure

9.2.3 Application Curve

Figure 25. Ron vs VCOM

10 Power Supply Recommendations

frequency noise to provide better load regulation across the frequency spectrum.

11 Layout

11.1 Layout Guidelines

frequency noise to provide better load regulation across the frequency spectrum. Minimize trace lengths and vias on the signal paths in order to preserve signal integrity.

11.2 Layout Example

Figure 26. Layout Example of TS5A22364

SCDS261H –MARCH 2008–REVISED JUNE 2017 www.ti.com Product Folder Links: TS5A22364 Submit Documentation Feedback Copyright © 2008–2017, Texas Instruments Incorporated

12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.3 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.5 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 10-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TS5A22364DGSR Active Production VSSOP (DGS) | 10 2500 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 85 (38Q, 38R) TS5A22364DGSR.B Active Production VSSOP (DGS) | 10 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 (38Q, 38R) TS5A22364DGSRG4 Active Production VSSOP (DGS) | 10 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 38R TS5A22364DGSRG4.B Active Production VSSOP (DGS) | 10 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 38R TS5A22364DRCR Active Production VSON (DRC) | 10 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ZVF TS5A22364DRCR.B Active Production VSON (DRC) | 10 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ZVF TS5A22364DRCRG4 Active Production VSON (DRC) | 10 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ZVF TS5A22364DRCRG4.B Active Production VSON (DRC) | 10 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ZVF TS5A22364YZPR Active Production DSBGA (YZP) | 10 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 85 (38, 382) TS5A22364YZPR.B Active Production DSBGA (YZP) | 10 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 85 (38, 382) (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative Addendum-Page 1

www.ti.com 10-Nov-2025 and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TS5A22364 :

• Automotive : TS5A22364-Q1 NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 11-Sep-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 11-Sep-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TS5A22364DGSR VSSOP DGS 10 2500 366.0 364.0 50.0 TS5A22364DGSRG4 VSSOP DGS 10 2500 358.0 335.0 35.0 TS5A22364DRCR VSON DRC 10 3000 353.0 353.0 32.0 TS5A22364DRCRG4 VSON DRC 10 3000 353.0 353.0 32.0 TS5A22364YZPR DSBGA YZP 10 3000 220.0 220.0 35.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C0.5 MAX 0.19 0.15 1.5 TYP

1 TYP

0.5 TYP 0.5 TYP10X 0.25 0.21 B E A D DSBGA - 0.5 mm max heightYZP0010 DIE SIZE BALL GRID ARRAY 4219350/B 11/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. BALL A3 CORNER SEATING PLANE BALL TYP 0.015 C D C B A 1 2 3

0.015 C A B

SCALE 8.000 D: Max = E: Max = 1.89 mm, Min = 1.39 mm, Min = 1.83 mm 1.33 mm

www.ti.com EXAMPLE BOARD LAYOUT 10X ( 0.225) (0.5) TYP (0.5) TYP ( 0.225) METAL

0.05 MAX

( 0.225) SOLDER MASK OPENING

0.05 MIN

DSBGA - 0.5 mm max heightYZP0010 DIE SIZE BALL GRID ARRAY 4219350/B 11/2017 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SBVA017 (www.ti.com/lit/sbva017). SYMM SYMM LAND PATTERN EXAMPLE SCALE:30X D C 2 3 A B NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (0.5) TYP (0.5) TYP METAL TYP DSBGA - 0.5 mm max heightYZP0010 DIE SIZE BALL GRID ARRAY 4219350/B 11/2017 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. D C 1 2 3 A B SYMM SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:30X

www.ti.com PACKAGE OUTLINE C TYP5.05 4.75

1.1 MAX

8X 0.5 10X 0.27 0.17 0.15 0.05 TYP0.23 0.13 0 - 8 0.25 GAGE PLANE 0.7 0.4 A NOTE 3 3.1 2.9 B NOTE 4 3.1 2.9 4221984/A 05/2015 VSSOP - 1.1 mm max heightDGS0010A SMALL OUTLINE PACKAGE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187, variation BA.

0.1 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 3.200

www.ti.com EXAMPLE BOARD LAYOUT (4.4) 10X (1.45) 10X (0.3) 8X (0.5) (R ) TYP 0.05 4221984/A 05/2015 VSSOP - 1.1 mm max heightDGS0010A SMALL OUTLINE PACKAGE SYMM SYMM LAND PATTERN EXAMPLE SCALE:10X 5 6 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (4.4) 8X (0.5) 10X (0.3) 10X (1.45) (R ) TYP0.05 4221984/A 05/2015 VSSOP - 1.1 mm max heightDGS0010A SMALL OUTLINE PACKAGE NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 5 6 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. VSON - 1 mm max heightDRC 10 PLASTIC SMALL OUTLINE - NO LEAD3 x 3, 0.5 mm pitch 4226193/A

www.ti.com PACKAGE OUTLINE C 10X 0.30 0.18 2.4 0.1 1.65 0.1 8X 0.5 1.0 0.8 10X 0.5 0.3 0.05 0.00 A 3.1 2.9 B 3.1 2.9 (0.2) TYP 4X (0.25) 2X (0.5) VSON - 1 mm max heightDRC0010J PLASTIC SMALL OUTLINE - NO LEAD 4218878/B 07/2018 PIN 1 INDEX AREA SEATING PLANE 0.08 C 5 6 (OPTIONAL) PIN 1 ID 0.1 C A B 0.05 C THERMAL PAD EXPOSED SYMM SYMM11 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

ALL AROUND0.07 MAX ALL AROUND 10X (0.24) (2.4) (2.8) 8X (0.5) (1.65) ( 0.2) VIA TYP (0.575) (0.95) 10X (0.6) (R0.05) TYP (3.4) (0.25) (0.5) VSON - 1 mm max heightDRC0010J PLASTIC SMALL OUTLINE - NO LEAD 4218878/B 07/2018 SYMM 5 6 LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X SYMM NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (R0.05) TYP 10X (0.24) 10X (0.6) 2X (1.5) (1.06) (2.8) (0.63) 8X (0.5) (0.5) 4X (0.34) 4X (0.25) (1.53) VSON - 1 mm max heightDRC0010J PLASTIC SMALL OUTLINE - NO LEAD 4218878/B 07/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 11: 80% PRINTED SOLDER COVERAGE BY AREA SCALE:25X SYMM 5 6 EXPOSED METAL TYP11 SYMM

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