TS555CDT STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Features
■ Very low power consumption: 110 µA typ at VCC = 5 V 90 µa typ at VCC = 3 V ■ High maximum astable frequency of 2.7 MHz ■ Pin-to-pin functionally-compatible with bipolar NE555 ■ Wide voltage range: +2 V to +16 V ■ Supply current spikes reduced during output transitions ■ High input impedance: 1012 Ω ■ Output compatible with TTL, CMOS and logic MOS
Description
The TS555 is a single CMOS timer with a very low consumption: cc(TYP) TS555 = 110 µA at VCC = +5 V versus Icc(TYP) NE555 = 3 mA), and high frequency: f(max.) TS555 = 2.7 MHz versus f(max) NE555 = 0.1 MHz). Timing remains accurate in both monostable and astable mode. The TS555 provides reduced supply current spikes during output transitions, which enable the use of lower decoupling capacitors compared to those required by bipolar NE555. With the high input impedance (10 12Ω), timing capacitors can also be minimized. N DIP8 (Plastic package) D SO8 (Plastic micropackage) P TSSOP8 (Thin shrink small outline package) GND Trigger Output Reset CC ControlVoltage V Discharge Threshold Pin connections (top view)
1 Absolute maximum ratings and operating conditions
Table 1. Absolute maximum ratings
- Short-circuits can cause excessive heating. These values are typical and specified for a single layer PCB.
- Short-circuits can cause excessive heating. These values are typical and specified for a four layers PCB.
- Human body model: a 100 pF capacit or is charged to the specified voltage, then discharged through a
while the other pins are floating.
- Machine model: a 200 pF capacitor is charged to the specified voltage, then discharged directly between
connected pin combinations while the other pins remain floating.
- Charged device model: all pins plus package ar e charged together to the specified voltage and then
discharged directly to the ground. Table 2. Operating conditions
2 Schematic diagrams
Figure 1. Schematic diagram
Figure 2. Block diagram Note: LOW: level voltage ≤ minimum voltage specified. HIGH: level voltage ≥ maximum voltage specified. Table 3. Functions table
3 Electrical characteristics
Table 4. Static electrical characteristics
Table 5. Static electrical characteristics
Table 6. Dynamic electrical characteristics
2 MHz
Table 7. Static electrical characteristics
Table 8. Dynamic electrical characteristics
2.7 MHz
Table 9. Static electrical characteristics Table 10. Dynamic electrical characteristics
Figure 3. Supply current (per timer) versus supply voltage
4 Application information
4.1 Monostable operation
initially held discharged by a transistor inside the timer, as shown in Figure 4. Figure 4. Application schematic again during this interval. The duration of the output HIGH state is given by t = 1.1 R x C. output is driven to the LOW state. capacitor increases exponentially with the time constant τ = R x C. shows the actual waveforms generated in this mode of operation. When Reset is not used, it should be tied high to avoid any false triggering. Figure 5. Timing diagram
4.2 Astable operation
In the astable mode of operation, C charges and discharges between 1/3 VCC and 2/3 VCC. independent of the supply voltage. Figure 6. Application schematic Figure 7 shows actual waveforms generated in this mode of operation. Figure 7. Timing diagram
5 Package information
In order to meet environmental requirements, STMicroelectronics offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an STMicroelectronics trademark. ECOPACK specifications are available at: www.st.com.
5.1 DIP8 package information
Figure 8. DIP8 package mechanical drawing Table 11. DIP8 package mechanical data
5.2 SO-8 package information
Figure 9. SO-8 package mechanical drawing Table 12. SO-8 package mechanical data
5.3 TSSOP8 package information
Figure 10. TSSOP8 package mechanical drawing Table 13. TSSOP8 package mechanical data
6 Ordering information
Table 14. Order codes
7 Revision history
Table 15. Document revision history 01-Feb-2003 1 Initial release. Table 1: Absolute maximum ratings. Added output current values in Table 2: Operating conditions.