TS52002 ETC2 | Alldatasheet

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  • 1 - TS52002 Version 1.2 Specifications subject to change WWW.TRIUNESYSTEMS.COM Copyright © 2011, Triune Systems, LLC DESCRIPTION FEATURES  Utilizes a temperature-independent PV MPPT-Lite™ regulation scheme  VBAT reverse current blocking  Up to 1.5A continuous output current  High efficiency – up to 92% at typical load  Current mode PWM control in constant voltage  Input supply under-voltage lockout  Full protection for VBAT over-voltage  Device over-current and over-temperature protection  I2C status interface  VBAT status indication SUMMARY SPECIFICATION  Wide Input Voltage Range: 3.2V to 7.2V  Packaged in a 16pin QFN (4x4) TYPICAL APPLICATION GND EN SW nFLT VBAT SCL PGND COUT LOUT RSENSE VIN SDA Photovoltaic Cells VSENSE RPULLUP (optional) VDD RPULLUP (optional) VDD CIN VDD CVdd TS52002 µC NiMH – 1 or 2 cells Series or Parallel The TS52002 is a DC/DC synchronous switching MPPT Regulator with fully integrat ed power switches, internal compensation, and fu ll fault protection. The TS52002 utilizes a temperature - independent photovoltaic Maximum Power Point Tracking ( MPPT-Lite™) calculator to optimize power output from the source. The switching frequency of 1MHz enables the use of small filter components, resulting in smaller board space and reduced BOM costs.

APPLICATIONS

 1-cell and 2-cell NiMH chargers  Portable solar chargers  Off-grid systems  Wireless sensor networks  Smoke detectors  HVAC controls High Efficiency NiMH Battery Charger for Photovoltaic Sources

  • 2 - TS52002 Version 1.2 Specifications subject to change WWW.TRIUNESYSTEMS.COM Copyright © 2011, Triune Systems, LLC PINOUT TS52002 QFN16 4x4 Top/Symbolization View VIN VSENSE VBAT SW VIN NC NC SCL SW PGND PGND SDA nFLT EN GND VDD Figure 1b: Package Pinout Diagram PIN DESCRIPTION Pin Symbol Pin # Function Description SW 1 Switching Voltage Node Connected to 4.7uH (typical) inductor VIN 2 Photovoltaic Input Voltage Input voltage VSENSE 3 Current Sense Positive Input Positive input for the MPP current loop. VBAT 4 Output Voltage Regulator Feedback Input GND 5 GND Primary ground for the majority of the device except the low-side power FET. EN 6 Enable Input Above 2.2V the device is enabled. GND the pin to disable the device. Includes internal pull-up. nFLT 7 Inverted Fault Open-drain output. VDD 8 Internal 3.3V Supply Output Connected to 100nF capacitor to GND

9 Unused GND in application

10 Unused GND in application

VIN 11 Photovoltaic Input Voltage Input voltage SCL 12 Clock Input I²C clock input. SDA 13 Data Input/Output I²C data open-drain output. SW 14 Switching Voltage Node Connected to 4.7uH (typical) inductor PGND 15 Power GND GND supply for internal low-side FET/integrated diode PGND 16 Power GND GND supply for internal low-side FET/integrated diode

  • 3 - TS52002 Version 1.2 Specifications subject to change WWW.TRIUNESYSTEMS.COM Copyright © 2011, Triune Systems, LLC FUNCTIONAL BLOCK DIAGRAM VIN Gate Drive Gate Drive Gate Drive Control VBAT SW Oscillator Ramp Generator Comparator Error Amp GND MONITOR CONTROL Over Voltage Protection VBAT VIN VIN EN PGND nFLT COUT LOUT Compensation Network Backgate Blocking Photovoltaic Cells ~5V @ 450mA Vref Load RSENSE VSENSE MPP & Current Control I²C Interface SCL SDA VIN CIN VDD CVDD VDD Regulator VIN Figure 2: TS52002 Block Diagram
  • 4 - TS52002 Version 1.2 Specifications subject to change WWW.TRIUNESYSTEMS.COM Copyright © 2011, Triune Systems, LLC ABSOLUTE MAXIMUM RATINGS Over operating free–air temperature range unless otherwise noted(1,2,3) Parameter Range Unit VIN, EN, nFLT, SCL, SDA, VBAT, VSENSE -0.3 to 8 V SW -1 to 8.8 V VDD -0.3 to 3.6 V Operating Junction Temperature Range, TJ -40 to 125 C Storage Temperature Range, TSTG -65 to 150 C Electrostatic Discharge – Human Body Model ±2k V Electrostatic Discharge – Machine Model +/-200 V Lead Temperature (soldering, 10 seconds) 260 C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is n ot implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to network ground terminal. (3) ESD testing is performed according to the respective JESD22 JEDEC standard. THERMAL CHARACTERISTICS Symbol Parameter Value Unit JA Thermal Resistance Junction to Air (Note 1) 50 °C/W Note 1: Assumes 4x4 QFN-16 in 1 in2 area of 2 oz copper and 25C ambient temperature. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Typ Max Unit VIN Photovoltaic Input Operating Voltage 3.2 5.3 7.2 V RSENSE Sense Resistor 50 m LOUT Output Filter Inductor Typical Value (Note 1) 4.7 uH COUT Output Filter Capacitor Typical Value (Note 2) 4.7 uF COUT-ESR Output Filter Capacitor ESR 100 m CIN Input Supply Bypass Capacitor Typical Value (Note 3) 3.3 10 uF CVDD VDD Supply Bypass Capacitor Value (Note 2) 70 100 130 nF TA Operating Free Air Temperature -40 85 C TJ Operating Junction Temperature -40 125 C Note 1: For best performance, an inductor with a saturation current rating higher than the maximum VBAT load requirement plus the inductor current ripple. Note 2: For best performance, a low ESR ceramic capacitor should be used. Note 3: For best performance, a low ESR ceramic capacitor should be used. If CIN is not a low ESR ceramic capacitor, a 0.1uF ceramic capacitor should be added in parallel to CIN.
  • 5 - TS52002 Version 1.2 Specifications subject to change WWW.TRIUNESYSTEMS.COM Copyright © 2011, Triune Systems, LLC CHARACTERISTICS Electrical Characteristics, TJ = -40C to 125C, VIN = 5.3V (unless otherwise noted) Symbol Parameter Condition Min Typ Max Unit VIN Supply Voltage V IN Photovoltaic Voltage Input 3.2 5.3 7.2 V ICC-NORM Quiescent current Normal Mode ILOAD = 0A 3 mA ICC-STBY Quiescent current Disable Mode EN = 0V 15 50 uA VBAT Leakage IBAT-LEAK Leakage Current From Output EN = 0V 10 uA IBAT-BACK Reverse Current VBAT > VIN 10 uA VIN Under-Voltage Lockout VIN-UV Input Supply Under-Voltage Threshold VIN Increasing 3.15 V VIN-UV_HYST Input Supply Under-Voltage Threshold Hysteresis 100 200 mV OSC FOSC Oscillator Frequency 0.9 1 1.1 MHz nFLT Open Drain Output IOH-nFLT High-Level Output Leakage VnFLT = 5.3V 0.1 uA VOL-nFLT Low-Level Output Voltage InFLT = -1mA 0.4 V EN/SCL/SDA Input Voltage Thresholds VIH High Level Input Voltage 2.2 V VIL Low Level Input Voltage 0.8 V VHYST Input Hysteresis 200 mV IIN-EN Input Leakage VEN=VIN 0.1 uA VEN=0V -2.0 uA IIN-SCL Input Leakage VSCL=VIN 55 uA VSCL=0V -0.1 uA IIN-SDA Input Leakage VSDA=VIN 0.1 uA VSDA=0V -0.1 uA VOL-SDA Low-Level Output Voltage ISDA = -1mA 0.4 V Thermal Shutdown TSD Thermal Shutdown Junction Temperature 150 170 C TSDHYST TSD Hysteresis 10 C
  • 6 - TS52002 Version 1.2 Specifications subject to change WWW.TRIUNESYSTEMS.COM Copyright © 2011, Triune Systems, LLC CHARGER CHARACTERISTICS Electrical Characteristics, TJ = -40C to 125C, VIN = 5.3V (unless otherwise noted) Symbol Parameter Condition Min Typ Max Unit Charging Regulator: L=4.7uH and C=4.7uF IBAT-FC Output Current Limit IBAT =1.5A IBAT - 10% IBAT IBAT + 10% A VBAT-TO Termination Voltage 4.16 4.2 4.24 V RDSON High Side Switch On Resistance ISW = -1A, TJ=25C 250 mΩ Low Side Switch On Resistance ISW = 1A, TJ=25C 150 mΩ IBAT Max Output Current 1.5 A IOCD Over-Current Detect HS switch current 2.5 A VBAT-OV VBAT Over-Voltage Threshold 101% VBAT 102% VBAT 103% VBAT VBAT-OV_HYST VBAT Over-Voltage Hysteresis 0.2% VBAT 0.4% VBAT 0.6% VBAT DUTYMAX Max Duty Cycle 99 % I2C INTERFACE TIMING REQUIREMENTS Electrical Characteristics, TJ = -40C to 125C, VIN = 5.3V (unless otherwise noted) Symbol Parameter Standard Mode Fast Mode Unit Min Max Min Max fscl I2C clock frequency 0 100 0 400 kHz tsch I2C clock high time 4 0.6 µs tscl I2C clock low time 4.7 1.3 µs tsp I2C tolerable spike time 0 50 0 50 ns tsds I2C serial data setup time 250 100 ns tsdh I2C serial data hold time 0 0 µs ticr I2C input rise time 1000 300 ns ticf I2C input fall time 300 300 ns tocf I2C output fall time; 10 pF to 400 pF bus 300 300 ns tbuf I2C bus free time between Stop and Start 4.7 1.3 µs tsts I2C Start or repeated Start condition setup time 4.7 0.6 µs tsth I2C Start or repeated Start condition hold time 4 0.6 µs tsps I2C Stop condition setup time 4 0.6 µs
  • 7 - TS52002 Version 1.2 Specifications subject to change WWW.TRIUNESYSTEMS.COM Copyright © 2011, Triune Systems, LLC FUNCTIONAL DESCRIPTION The TS 52002 is a fully -integrated MPP regulator IC based on a highly -efficient switching topology. It includes a Maximum Power Point Tracking (MPPT) function to optimize its input voltage to extract the maximum possible power from a photovoltaic cell. A 1 MHz internal switching frequency facilitates low-cost LC filter combinations. When the output voltage is below the termination voltage, the device will regulate to the maximum power point. This will continue as long as the output current is below the current limit and no fault has occurred. In order for the Maximum Power Point (MPP) regulation to be most effective, the output load needs to not allow high frequency transients in output voltage. This will cause the device to operate at a non optimal MPP point until the output voltage has remained stat ic for several milliseconds. As detailed in the Ap plication Diagram, the external µC pulses the charging current based on a NiMH charging profile . The battery voltage and/or temperature is monitored to safely charge and ensure the battery is fully charged. One or two NiMH cells can be configured in series or parallel with a p arallel configuration requiring two switches to allow the µC to manage the charging profile. INTERNAL PROTECTION DETAILS Internal Current Limit The current through the inductor is sensed on a cycle by cycle basis and if current l imit is reached, it will abbreviate the cycle. Current limit is always active when the regulator is enabled. Thermal Shutdown If the temperature of the die exceeds 170C (typical), the SW outputs will tri -state to protect the device from damage. The nF LT and all other protection circuitry will stay active to inform the system of the failure mode. Once the device cools to 160C (typical), the device will attempt to start up again. If the device reaches 170C, the shutdown/restart sequence will repeat. VIN Under-Voltage Lockout The device is held in the off state until VIN reaches 3. 15V. There is a 200mV hysteresis on this input, which requ ires the input to fall below 2.95V before the device will disable. VBAT Over-Voltage Protection The TS52002 has an output protection circuit designed to shutdown the charging profile if the output voltage is greater than the termination voltage. Shutting down the charging profile puts the TS52002 in a fault condition.
  • 8 - TS52002 Version 1.2 Specifications subject to change WWW.TRIUNESYSTEMS.COM Copyright © 2011, Triune Systems, LLC SERIAL INTERFACE The TS52002 features an I2C slave interface which offers advanced control and diagnostic features. I 2C operation offers fault and warning indicators. Whenever a fault is detected, the associated status bit in the STATUS register is set and the nFLT p in is pulled low. Wheneve r a warning is detected, the associated status bit in the STATUS register is set, but the nFLT pin is not pulled low. Reading of the STATUS register resets the fault and warning status bits, and the nFLT pin is released after all fault status bits have been reset. I2C SUBADDRESS DEFINITION Figure 3: Sub-address in I2C Transmission I2C BUS OPERATION The TS52002 has a slave I2C interface that supports standard and fast mode data rates, auto-sequencing, and is compliant to I2C standard version 3.0. I2C is a two -wire serial interface where the two lines are serial clock (SCL) and serial data (SDA). SDA must be connected to a positive supply through an external pull -up resistor. The devices communicating on this bus can drive the SDA line low or release it to high impedance. The device that initiates the I 2C transaction becomes the master of the bus. Communication is initiated by the master sending a Start condition, a high -to-low transition on SDA, while the SCL line is high. After the Start condition, the device address byte is sent, most significant bit (MSB) first, including the data direction bit (R/nW). After receiving the valid address byte, the device responds with an acknowledge (ACK). An ACK is a low on SDA during the high of the ACK related clock pulse. On the I2C bus, during each clock pulse only one data bit is transferred. The data on the SDA line must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as Sta rt or Stop control commands. A low-to-high transition on SDA while the SCL input is high, indicates a Stop condition and is sent by the master (see Figure 4). Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Sto p conditions. Each byte of eight bits is followed by one ACK bit. The SDA line must be released by the transmitter before the receiver can send an ACK bit. The receiver that acknowledges must pull down the SDA line during the ACK clock pulse, so that the SDA line is stable low during the high pulse of the ACK -related clock period. When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must generate an ACK after each byte that it receives from the sl ave transmitter. To ensure proper operation, setup and hold times must be met. An end of data is signaled by the master receiver to the slave transmitter by not generating an acknowledge after the last byte has been clocked out of the slave. This is don e by the master receiver by holding the SDA line high. The transmitter must then release the data line to enable the master to generate a St op condition.
  • 10 - TS52002 Version 1.2 Specifications subject to change WWW.TRIUNESYSTEMS.COM Copyright © 2011, Triune Systems, LLC REGISTER DESCRIPTION (Device Address = 0x48) REGISTER ADDRESS (HEX) NAME DESCRIPTION 0 00 STATUS Status bit register 1-31 N/A N/A Registers not implemented STATUS REGISTER (STATUS) Address – 0x00h DATA BIT D7 D6 D5 D4 D3 D2 D1 D0 FIELD NAME VBAT_OV Not Used Not Used Not Used TSD Not Used VIN_UV Not Used READ/WRITE R R R R R R R R FIELD NAME BIT DEFINITION(1) VBAT_OV VBAT over-voltage TSD Thermal shutdown VIN_UV VIN under-voltage (1) Faults are defined as VBAT_OV. Warnings are defined as TSD, and VIN_UV. Faults cause the nFLT pin to be pulled low, Warnings do not cause the nFLT pin to be pulled low. All status bits are cleared after register read access. nFLT pin will go high impedance (open drain output) after the status register has been read and all status bits have been reset. CONFIGURATION REGISTER Address – 0x04h DATA BIT D7 D6 D5 D4 D3 D2 D1 D0 FIELD NAME MAX_CHRG_CURR [3:0] Not Used READ/WRITE R/W R/W R/W R/W R/W R/W R/W R/W FIELD NAME BIT DEFINITION MAX_CHRG_CURR[3:0] Maximum charge current configuration 0000 – 50 mA 0001 – 100 mA 0010 – 200 mA 0011 – 300 mA 0100 – 400 mA 0101 – 500 mA 0110 – 600 mA 0111 – 700 mA 1000 – 800 mA 1001 – 900 mA 1010 – 1000 mA 1011 – 1100 mA 1100 – 1200 mA 1101 – 1300 mA 1110 – 1400 mA 1111 – 1500 mA EXTERNAL COMPONENT SELECTION The internal compensation is optimized for a 4.7uF output capacitor and a 4.7uH inductor. To keep the output ripple low, a low ESR (less than 35mOhm) ceramic is recommended.
  • 11 - TS52002 Version 1.2 Specifications subject to change WWW.TRIUNESYSTEMS.COM Copyright © 2011, Triune Systems, LLC PACKAGE MECHANICAL DRAWINGS
  • 12 - TS52002 Version 1.2 Specifications subject to change WWW.TRIUNESYSTEMS.COM Copyright © 2011, Triune Systems, LLC APPLICATION USING A MULTI-LAYER PCB To maximize the efficiency of this package for application on a single layer or multi -layer PCB, certain guidelines must be followed when laying out this part on the PCB. The following are guidelines for mounting the exposed pad IC on a Multi-Layer PCB with ground a plane. JEDEC standard FR4 PCB Cross-section: Multi-Layer Board (Cross-sectional View) In a multi -layer board application, the thermal vias are the primary method of heat transfer from the package thermal pad to the internal ground plane. The efficiency of this method depends on several factors, including die area, number of thermal v ias, thickness of copper, etc. Package Thermal Pad Solder Pad (Land Pattern) Thermal Via's Package Outline Package and PCB Land Configuration For a Multi-Layer PCB (square) Package Solder Pad Package Solder Pad (bottom trace) Thermal Via Component Traces Thermal Isolation Power plane only 1.5748mm 0.0 - 0.071 mm Board Base & Bottom Pad 0.5246 - 0.5606 mm Power Plane (1oz Cu) 1.0142 - 1.0502 mm Ground Plane (1oz Cu) 1.5038 - 1.5748 mm Component Trace (2oz Cu) 2 Plane

4 Plane

  • 13 - TS52002 Version 1.2 Specifications subject to change WWW.TRIUNESYSTEMS.COM Copyright © 2011, Triune Systems, LLC The above drawing is a representation of how the heat can be conducted away from the die using an exposed pad package. Each application will have different requirements and limitations and therefore the user should use sufficient copper to dissipate the power in the system. The output current rating for the linear regulators m ay have to be de -rated for ambient temperatures above 85C. The de -rate value will depend on calculated worst case power dissipation and the thermal management implementation in the application. APPLICATION USING A SINGLE LAYER PCB Layout recommendations for a Single Layer PCB: utilize as much Copper Area for Power Management. In a single layer board application the thermal pad is attached to a heat spreader (copper areas) by using low thermal impedance attachment method (solder paste or thermal conductive epoxy). In both of the methods mentioned above it is advisable to use as much copper traces as possible to dissipate the heat. IMPORTANT: If the attachment method is NOT implemented correctly, the functionality of the product is not guaranteed. Pow er dissipation capability will be adversely affected if the device is incorrectly mounted onto the circuit board. Mold compound Die Epoxy Die attach Exposed pad Solder Thermal Vias with Cu plating Single Layer, 2oz Cu Ground Layer, 1oz Cu Signal Layer, 1oz Cu Bottom Layer, 2oz Cu 20% Cu coverage 90% Cu coverage 5% - 10% Cu coverage Note: NOT to Scale Use as much Copper Area as possible for heat spread Package Thermal Pad Package Outline
  • 14 - TS52002 Version 1.2 Specifications subject to change WWW.TRIUNESYSTEMS.COM Copyright © 2011, Triune Systems, LLC Legal Notices Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. “Typical” parameters whic h may be provided in Triune Systems data sheets and/or specifications can and do vary in different applica tions and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for your application by your technical experts. TRIUNE SYSTEMS MAKES NO R EPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED , WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Triune Systems disclaims all liability arising from this information and its us e. Triune System products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to su pport or sustain life, or for any other application in which the failure o f the Triune Systems product could create a situation where personal injury or death may occur. Should the Buyer purchase or use Triune Systems products for any such unintended or unauthorized application, the Buyer shall indemnify and hold Triune Systems, and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expe nses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with s uch unintended or unauthorized use, even if such claim alleges that Triune Systems was negligent regarding the design or manufacture of the part. No licenses are conveyed, implici tly or otherwise, under any Triune Systems intellectual property rights. Trademarks All other trademarks mentioned herein are property of their respective companies. © 2012 Triune Systems, LLC. All Rights Reserved.