TS512_08 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 16
Technical content
Features
■ Low input offset voltage: 500 µV max. ■ Low power consumption ■ Short-circuit protection ■ Low distortion, low noise ■ High gain-bandwidth product: 3 MHz ■ High channel separation ■ ESD protection 2 kV ■ Macromodel included in this specification
Description
The TS512 is a high performance dual operational amplifier with frequency and phase compensation built into the chip. The internal phase compensation allows stable operation in voltage follower in spite of its high gain-bandwidth product. The circuit presents very stable electrical characteristics over the entire supply voltage range, and is particularly intended for professional and telecom applications (such as active filtering). N DIP8 (Plastic package) D SO-8 (Plastic micropackage) /C73/C110/C118/C101/C114/C116/C105/C110/C103/C32/C73/C110/C112/C117/C116/C32/C50 /C78/C111/C110/C45/C105/C110/C118/C101/C114/C116/C105/C110/C103/C32/C73/C110/C112/C117/C116/C32/C50 /C78/C111/C110/C45/C105/C110/C118/C101/C114/C116/C105/C110/C103/C32/C73/C110/C112/C117/C116/C32/C49 /C45/C67/C67/C86 /C49 /C50 /C51 /C52 /C56 /C53 /C54 /C55 /C67/C67/C86/C32/C32/C32/C32/C32/C43 /C45 /C43 /C45 /C43 /C79/C117/C116/C112/C117/C116/C32/C49 /C73/C110/C118/C101/C114/C116/C105/C110/C103/C32/C73/C110/C112/C117/C116/C32/C49/C79/C117/C116/C112/C117/C116 Pin connections (Top view)
1 Absolute maximum ratings and operating conditions
Table 1. Absolute maximum ratings
- Short-circuits can caus e excessive heating and destructive dissipation.Rth are typical values.
- Human body model: A 100 pF capacitor is charged to the specified voltage, then discharged through a
while the other pins are floating.
- Machine model: A 200 pF capacitor is charged to t he specified voltage, then discharged directly between
connected pin combinations while the other pins are floating.
- Charged device model: all pins and the package are charged together to the specified voltage and then
discharged directly to the ground through only one pin. This is done for all pins. Table 2. Operating conditions
- Value with respect to V DD pin.
2 Schematic diagram
Figure 1. Schematic diagram (1/2 TS512)
3 Electrical characteristics
Table 3. V CC
4 Macromodels
4.1 Important note concerning this macromodel
Please consider the following remarks before using this macromodel.
- All models are a trade-off between accuracy and complexity (i.e. simulation time).
- Macromodels are not a substitute to breadboarding; rather, they confirm the validity of a design approach and help to select surrounding component values.
- A macromodel emulates the nominal performance of a typical device within specified operating conditions (temperature, supply voltage, for example). Thus the macromodel is often not as exhaustive as the datasheet, its purpose is to illustrate the main parameters of the product. Data derived from macromodels used outside of the specified conditions (VCC, temperature, for example) or even worse, outside of the device operating conditions (VCC, Vicm, for example), is not reliable in any way.
4.2 Macromodel code
Standard Linear Ics Macromodels, 1993. CONNECTIONS : * 1 INVERTING INPUT * 2 NON-INVERTING INPUT * 3 OUTPUT * 4 POSITIVE POWER SUPPLY * 5 NEGATIVE POWER SUPPLY .SUBCKT TS512 1 3 2 4 5 .MODEL MDTH D IS=1E-8 KF=6.565195E-17 CJO=10F * INPUT STAGE CIP 2 5 1.000000E-12 CIN 1 5 1.000000E-12 EIP 10 5 2 5 1 EIN 16 5 1 5 1 RIP 10 11 2.600000E+01 RIN 15 16 2.600000E+01 RIS 11 15 1.061852E+02 DIP 11 12 MDTH 400E-12 DIN 15 14 MDTH 400E-12 VOFP 12 13 DC 0 VOFN 13 14 DC 0 IPOL 13 5 1.000000E-05 CPS 11 15 12.47E-10 DINN 17 13 MDTH 400E-12 VIN 17 5 1.500000e+00 DINR 15 18 MDTH 400E-12 VIP 4 18 1.500000E+00 FCP 4 5 VOFP 3.400000E+01 FCN 5 4 VOFN 3.400000E+01
Table 4. V CC = ±15V, Tamb = 25°C (unless otherwise specified)
5 Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
Figure 23. DIP8 package mechanical drawing Table 5. DIP8 package mechanical data
Figure 24. SO-8 package mechanical drawing Table 6. SO-8 package mechanical data
6 Ordering information
7 Revision history
Table 7. Order codes
- Qualification and characterizati on according to AEC Q100 and Q003 or equivalent, advanced screening
according to AEC Q001 & Q 002 or equivalent are on-going. Table 8. Document revision history 21-Nov-2001 1 Initial release. electrical characteristics table. Corrected macromodel information.