TS507_08 STMICROELECTRONICS | Alldatasheet

Document overview

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  • PDF pages: 20

Technical content

Datasheet sections

  • 1 Absolute maximum ratings and operating conditions
  • 2 Electrical characteristics
  • 3 Application note
  • 3.1 Out-of-the-loop compensation technique
  • 3.2 In-the-loop-compensation technique
  • 4 Package information
  • 4.1 SOT23-5 package information
  • 4.2 SO-8 package
  • 5 Ordering information
  • 6 Revision history

Features

■ Ultra low offset voltage: 25 µV typ, 100 µV max ■ Rail-to-rail input/output voltage swing ■ Operating from 2.7 V to 5.5 V ■ High speed: 1.9 MHz ■ 45° phase margin with 100 pF ■ Low consumption: 0.8 mA at 2.7 V ■ Very large signal voltage gain: 131 dB ■ High power supply rejection ratio: 105 dB ■ Very high ESD protection 5kV (HBM) ■ Latch-up immunity ■ Available in SOT23-5 micropackage

Applications

■ Battery-powered applications ■ Portable devices ■ Signal conditioning ■ Medical instrumentation

Description

The TS507 is a high performance rail-to-rail input and output amplifier with very low offset voltage. This amplifier uses a new trimming technique that yields ultra low offset voltages without any need for external zeroing. The circuit offers very stable electrical characteristics over the entire supply voltage range, and is particularly intended for automotive and industrial applications. The TS507 is housed in the space-saving 5-pin SOT23 package, making it well suited for battery- powered systems. This micropackage simplifies the PC board design because of its ability to be placed in tight spaces (external dimensions are 2.8 mm x 2.9 mm). VDD VCC N.C. N.C. Non Inverting Input Inverting Input Output+ N.C. VDD VCC N.C. N.C. Non Inverting Input Inverting Input Output+ N.C. VDD VCC Non Inverting Input Inverting Input Output 1 VDD VCC Non Inverting Input Inverting Input Output Pin connections (top view) SOT23-5 SO-8

1 Absolute maximum ratings and operating conditions

Table 1. Absolute maximum ratings (AMR)

  1. Value with respect to V DD pin.
  2. Differential voltages are the non-inverting input termi nal with respect to the inverting input terminal.
  3. V CC-Vin must not exceed 6V and Vin must not exceed 6V.
  4. Short-circuits can c ause excessive heating and destructive dissipation.
  5. R thja/c are typical values.
  6. Human body model: A 100 pF capacitor is charged to the specified voltage, then discharged through a

while the other pins are floating.

  1. Machine model: A 200 pF capacitor is charged to t he specified voltage, then discharged directly between

connected pin combinations while the other pins are floating.

  1. Charged device model: all pins and the package are charged together to the specified voltage and then

discharged directly to the ground through only one pin. This is done for all pins. Table 2. Operating conditions

  1. Value with respect to V DD pin.
  2. Differential voltages are the non-inverting input termi nal with respect to the inverting input terminal.

2 Electrical characteristics

Table 3. Electrical characteristics at V CC =+ 5 V , VDD =0 V , Vicm =V CC/2, Tamb =2 5 ° C ,

0.6 V/µs

  1. All parameter limits at te mperatures different from 25° C are guaranteed by correlation.
  2. Measurements done at 4 V icm values: Vicm=0 V, Vicm=3.8 V, Vicm=4.2 V, Vicm=5 V.

Table 4. Electrical characteristics at V CC =+ 3 . 3 V , VDD =0 V , Vicm =V CC/2, Tamb = 25°C,

  1. All parameter limits at te mperatures different from 25° C are guaranteed by correlation.

Table 5. Electrical characteristics at V CC =+ 2 . 7 V VDD =0 V , Vicm =V CC/2, Tamb =2 5 ° C ,

  1. All parameter limits at te mperatures different from 25° C are guaranteed by correlation.

Figure 25. Distortion + noise vs. frequency Figure 26. Noise vs. frequency

3 Application note

3.1 Out-of-the-loop compensation technique

Figure 27. Out-of-the-loop compensation schematics the case of a voltage follower configuration with a load resistor of 10 kΩ at 25°C. Figure 28. Gain margin abacus : serial resistor Figure 29. Phase margin abacus : serial

3.2 In-the-loop-comp ensation technique

in the feedback loop (see Figure 30). Figure 30. In-the-loop compensation schematics compensate the original pole (caused by the capacitive load), and thus to improve stability. resistor is in the signal path. capacitors (and with RL = 10 kΩ) in voltage follower configuration. Table 6. Best compensation components for different load capacitor ranges in

  1. Parameter guaranteed by design at 25°C.

4 Package information

4.1 SOT23-5 package information

Figure 31. SOT23-5 package mechanical drawing Table 7. SOT23-5 package mechanical data

4.2 SO-8 package

Figure 32. SO-8 package mechanical drawing Table 8. SO-8 package mechanical data

5 Ordering information

6 Revision history

Table 9. Order codes

  1. Qualification and characterizati on according to AEC Q100 and Q003 or equivalent, advanced screening

according to AEC Q001 & Q 002 or equivalent are on-going.

  1. All information related to the SOT23-5 package is subject to change without notice.

Table 10. Document revision history 01-Oct-2004 1 Preliminary data release for product in development. 02-May-2006 2 Update preliminary data release for product in development. 15-Dec-2006 3 First public release. 03-May-2007 4 Automotive grade products added. Application note section added.