TS4994_V01 STM | Alldatasheet
Document overview
- Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
- PDF pages: 35
Technical content
Datasheet sections
- 1 Application component information
- 2 Absolute maximum ratings and operating conditions
- 3 Electrical characteristics
- 4 Application information
- 4.1 Differential configuration principle
- 4.2 Gain in typical application schematic
- 4.3 Common mode feedback loop limitations
- 4.4 Low and high frequency response
- 4.5 Calculating the influence of mismatching on PSRR performance
- 4.6 CMRR performance
- 4.7 Power dissipation and efficiency
- 4.8 Decoupling of the circuit
- 4.9 Wake-up time: t
- 4.10 Shutdown time
- 4.11 Pop performance
- 4.12 Single-ended input configuration
- 4.13 Demoboard
- 5 Package mechanical data
- 5.1 DFN10 package
- 5.2 MiniSO-8 package
- 6 Revision history
Features
■ Differential inputs ■ Near-zero pop & click ■ 100dB PSRR @ 217Hz with grounded inputs ■ Operating range from VCC = 2.5V to 5.5V ■ 1W rail-to-rail output power @ VCC =5 V , THD = 1%, F = 1kHz, with 8Ω load ■ 90dB CMRR @ 217Hz ■ Ultra-low consumption in standby mode (10nA) ■ Selectable standby mode (active low or active high) ■ Ultra fast startup time: 15ms typ. ■ Available in DFN10 3x3 (0.5mm pitch) & MiniSO-8 ■ All lead-free packages
Description
The TS4994 is an audio power amplifier capable of delivering 1W of continuous RMS output power into an 8Ω load @ 5V. Due to its differential inputs, it exhibits outstanding noise immunity. An external standby mode control reduces the supply current to less than 10nA. An STBY MODE pin allows the standby to be active HIGH or LOW (except in the MiniSO-8 version). An internal thermal shutdown protection is also provided, making the device capable of sustaining short-circuits. The device is equipped with common mode feedback circuitry allowing outputs to be always biased at V CC/2 regardless of the input common mode voltage. The TS4994 is designed for high quality audio applications such as mobile phones and requires few external components.
Applications
■ Mobile phones (cellular / cordless) ■ Laptop / notebook computers ■ PDAs ■ Portable audio devices Order codes TS4994IQT - DFN10 Pin connections (top view) VIN - VO+STBY VDD VIN + STBY MODE BYPASS VO- GND N/C VIN - VO+STBY VDD VIN + STBY MODE BYPASS VO- GND N/C VIN+ VIN- VO+ GND Vcc VO-BYPASS 5 8STBY VIN+ VIN- VO+ GND Vcc VO-BYPASS 5 8STBY TS4994IST - MiniSO-8 Part number Temperature range Package Packing Marking TS4994IQT -40°C to +85°C DFN10 Tape & reel K994 TS4994IST MiniSO-8 K994
1 Application component information
Figure 1. Typical application, DFN10 version Cs Supply bypass capacitor that provides power supply filtering. Cb Bypass capacitor that provides half supply filtering. AV = closed loop gain = R feed/Rin. Rin Inverting input resistor that sets the closed loop gain in conjunction with Rfeed. Optional input capacitor making a high pass filter together with Rin.
8 Ohms
Figure 2. Typical application, MiniSO-8 version
2 Absolute maximum ratings and operating conditions
Table 1. Absolute maximum ratings
- All voltage values are measured with respect to the ground pin.
- The magnitude of the input signal must never exceed V CC + 0.3V / GND - 0.3V.
- The device is protected by a thermal shutdown active at 150°C.
Table 2. Operating conditions
- The minimum current consumption (I STBY) is guaranteed when VSTBY =G N D o r VCC (i.e. supply rails) for the whole
- When mounted on a 4-layer PCB.
3 Electrical characteristics
Table 3. Electrical characteristics for V CC = +5V, GND = 0V, Tamb = 25°C (unless otherwise
- Dynamic measurements - 20*log(rms(V out)/rms (Vripple)). Vripple is the super-imposed sinus signal relative to VCC.
- Transition time from standby mode to fully operational amplifier.
Table 4. Electrical characteristics for V CC = +3.3V (all electrical values are guaranteed with
- Dynamic measurements - 20*log(rms(V out)/rms (Vripple)). Vripple is the super-imposed sinus signal relative to VCC.
- Transition time from standby mode to fully operational amplifier.
Table 5. Electrical characteristics for V CC = +2.6V, GND = 0V, Tamb = 25°C (unless otherwise
- Dynamic measurements - 20*log(rms(V out)/rms (Vripple)). Vripple is the super-imposed sinus signal relative to VCC.
- Transition time from standby mode to fully operational amplifier.
Figure 69. Startup time vs. bypass capacitor
4 Application information
4.1 Differential configuration principle
The TS4994 is a monolithic full-differential input/output power amplifier. The TS4994 also includes a common mode feedback loop that controls the output bias value to average it at V CC/2 for any DC common mode input voltage. This allows the device to always have a maximum output voltage swing, and by consequence, maximize the output power. Moreover, as the load is connected differentially, compared to a single-ended topology, the output is four times higher for the same power supply voltage. The advantages of a full-differential amplifier are:
- Very high PSRR (power supply rejection ratio).
- High common mode noise rejection.
- Virtually zero pop without additional circuitry, giving a faster start-up time compared with conventional single-ended input amplifiers.
- Easier interfacing with differential output audio DAC.
- No input coupling capacitors required due to common mode feedback loop.
- In theory, the filtering of the internal bias by an external bypass capacitor is not necessary. But, to reach maximum performance in all tolerance situations, it is better to keep this option. The main disadvantage is:
- As the differential function is directly linked to the mismatch between external resistors, paying particular attention to this mismatch is mandatory in order to get the best performance from the amplifier.
4.2 Gain in typical application schematic
Typical differential applications are shown in Figure 1 and Figure 2 on page 4. In the flat region of the frequency-response curve (no Cin effect), the differential gain is expressed by the relation: where Rin = Rin1 = Rin2 and Rfeed = Rfeed1 = Rfeed2. Note: For the rest of this section, Av diff will be called AV to simplify the expression.
4.3 Common mode feedback loop limitations
As explained previously, the common mode feedback loop allows the output DC bias voltage to be averaged at VCC/2 for any DC common mode bias input voltage. However, due to VICM limitation of the input stage (see Table 3 on page 6), the common mode feedback loop can play its role only within a defined range. This range depends upon AVdiff VO+ VO– Rin
the values of VCC, Rin and Rfeed (AV). To have a good estimation of the VICM value, use the following formula: with The result of the calculation must be in the range: If the result of the VICM calculation is not in this range, an input coupling capacitor must be used. Example: With VCC=2.5V, Rin =R feed = 20k and Vic = 2V, we find VICM = 1.63V. This is higher than 2.5V - 0.9V = 1.6V, so input coupling capacitors are required. Alternatively, you can change the V ic value.
4.4 Low and high frequency response
In the low frequency region, Cin starts to have an effect. Cin forms, with Rin, a high-pass filter with a -3dB cut-off frequency. FCL is in Hz. In the high-frequency region, you can limit the bandwidth by adding a capacitor (Cfeed) in parallel with Rfeed. It forms a low-pass filter with a -3dB cut-off frequency. FCH is in Hz. While these bandwidth limitations are in theory attractive, in practice, because of low performance in terms of capacitor precision (and by consequence in terms of mismatching), they deteriorate the values of PSRR and CMRR. The influence of mismatching on PSRR and CMRR performance is discussed in more detail in the following sections. Example: A typical application with input coupling and feedback capacitor with F CL =5 0 H z and FCH = 8kHz. We assume that the mismatching between Rin1,2 and Cfeed1,2 can be neglected. If we sweep the frequency from DC to 20kHz we observe the following with respect to the PSRR value:
- From DC to 200Hz, the Cin impedance decreases from infinite to a finite value and the Cfeed impedance is high enough to be neglected. Due to the tolerance of Cin1,2, we VICM VCC Rin× 2V ic Rfeed××+ Vic Diff input+ Diff input-+ 0.6V V ICM VCC 0.9V–≤≤ )Hz(CR2 inin CL ××π×= )Hz(CR2 feedfeed CH ××π×=
must introduce a mismatch factor (Rin1 xC in ≠ Rin2 xC in2) that will decrease the PSRR performance.
- From 200Hz to 5kHz, the Cin impedance is low enough to be neglected when compared with Rin, and the Cfeed impedance is high enough to be neglected as well. In this range, we can reach the PSRR performance of the TS4994 itself.
- From 5kHz to 20kHz, the Cin impedance is low to be neglected when compared to Rin, and the Cfeed impedance decreases to a finite value. Due to tolerance of Cfeed1,2, we introduce a mismatching factor (Rfeed1 xC feed1 ≠ Rfeed2 xC feed2) that will decrease the PSRR performance.
4.5 Calculating the influence of mismatching on PSRR
For calculating PSRR performance, we consider that Cin and Cfeed have no influence. We use the same kind of resistor (same tolerance) and ΔR is the tolerance value in %. The following PSRR equation is valid for frequencies ranging from DC to about 1kHz. The PSRR equation is (ΔR in %): This equation doesn't include the additional performance provided by bypass capacitor filtering. If a bypass capacitor is added, it acts, together with the internal high output impedance bias, as a low-pass filter, and the result is a quite important PSRR improvement with a relatively small bypass capacitor. The complete PSRR equation (ΔR in %, C b in microFarad and F in Hz) is: Example: With ΔR = 0.1% and Cb = 0, the minimum PSRR would be -60dB. With a 100nF bypass capacitor, at 100Hz the new PSRR would be -93dB. This example is a worst case scenario, where each resistor has extreme tolerance. It illustrates the fact that with only a small bypass capacitor, the TS4994 provides high PSRR performance. Note also that this is a theoretical formula. Because the TS4994 has self-generated noise, you should consider that the highest practical PSRR reachable is about -110dB. It is therefore unreasonable to target a -120dB PSRR. )dB( )R10000( 100RLog20PSRR 2 ⎥ ×Δ×≤ PSRR 20 log ×≤ R 100×Δ (1000 R 2) 1F 2 Cb 2 22.2××+×Δ–
four ΔR/R values with a 0.1% tolerance.
4.6 CMRR performance
has no influence in the calculation of the CMRR. We use the same kind of resistor (same tolerance) and ΔR is the tolerance value in %. The following CMRR equation is valid for frequencies ranging from DC to about 1kHz. Example: With ΔR = 1%, the minimum CMRR is -34dB. illustrates the fact that for CMRR, good matching is essential. worst-case conditions (ΔR=0.1%). Figure 73. PSRR vs. frequency with random Figure 74. PSRR vs. frequency with random
random selection of four ΔR/R values with a 0.1% tolerance.
4.7 Power dissipation and efficiency
- Load voltage and current are sinusoidal (Vout and Iout)
- Supply voltage is a pure DC source (VCC) The output voltage is: and
Figure 75. CMR vs. frequency (worst case Figure 76. CMR vs. frequency (worst case Figure 77. CMR vs. frequency with random Figure 78. CMR vs. frequency with random
Therefore, the average current delivered by the supply voltage is: Equation 1 The power delivered by the supply voltage is: Therefore, the power dissipated by each amplifier is: Equation 2 and the maximum value is obtained when: and its value is: Equation 3 Note: This maximum value is only dependent on the power supply voltage and load values. The efficiency is the ratio between the output power and the power supply: Equation 4 The maximum theoretical value is reached when VPEAK = VCC, so: The maximum die temperature allowable for the TS4994 is 125°C. However, in case of overheating, a thermal shutdown set to 150°C, puts the TS4994 in standby until the temperature of the die is reduced by about 5°C. Pout = Vpeak 2RL ICC AVG = 2 Vpeak πRL Psupply VCC ICCAVG (W)⋅= Pdiss Psupply Pout (W)–= Pdiss
22 V CC
π RL ∂Pdiss ∂Pout )W( R Vcc2maxPdiss L π η = Pout Psupply πVpeak 4VCC η = π 4----- = 78.5%
To calculate the maximum ambient temperature Tamb allowable, you need to know:
- The value of the power supply voltage, VCC
- The value of the load resistor, RL
- The Rthja value for the package type Example: VCC =5 V , RL =8 Ω, Rthja = 80°C/W Using the power dissipation formula given above in Equation 3 this gives a result of: Pdissmax = 633mW Tamb is calculated as follows: Equation 5 Therefore, the maximum allowable value for Tamb is: Tamb = 125-80x0.633=74°C
4.8 Decoupling of the circuit
Two capacitors are needed to correctly bypass the TS4994. A power supply bypass capacitor Cs and a bias voltage bypass capacitor Cb. Cs has particular influence on the THD+N in the high frequency region (above 7kHz) and an indirect influence on power supply disturbances. With a value for Cs of 1µF , you can expect similar THD+N performance to that shown in the datasheet. In the high frequency region, if Cs is lower than 1µF , it increases THD+N, and disturbances on the power supply rail are less filtered. On the other hand, if Cs is higher than 1µF , the disturbances on the power supply rail are more filtered. Cb has an influence on THD+N at lower frequencies, but its function is critical to the final result of PSRR (with input grounded and in the lower frequency region).
4.9 Wake-up time: t WU
When the standby is released to put the device ON, the bypass capacitor Cb is not charged immediately. As Cb is directly linked to the bias of the amplifier, the bias will not work properly until the Cb voltage is correct. The time to reach this voltage is called the wake-up time or tWU and is specified in Table 3 on page 6, with Cb=1µF . During the wake-up time, the TS4994 gain is close to zero. After the wake-up time, the gain is released and set to its nominal value. If Cb has a value other than 1µF , refer to the graph in Figure 69 on page 20 to establish the wake-up time. Tamb 125° CR TJHA Pdissmax×–=
4.10 Shutdown time
impedance and the internal circuitry in shutdown mode is a few microseconds. internal switches. This allows a quick discharge of the Cb and Cin capacitors.
4.11 Pop performance
Due to its fully differential structure, the pop performance of the TS4994 is close to perfect. close to zero pop for all possible common applications. this configuration, no pop is heard.
4.12 Single-ended input configuration
configuration using the MiniSO-8 version of the TS4994 as an example. Figure 79. Single-ended input typical application
The component calculations remain the same, except for the gain. In single-ended input configuration, the formula is:
4.13 Demoboard
A demoboard for the TS4994 is available. It is designed for the TS4994 in the DFN10 package. However, we can guarantee that all electrical parameters except the power dissipation are similar for all packages. For more information about this demoboard, refer to Application Note AN2013. in feedOO SE R R Ve VVAv =−= −+
5 Package mechanical data
In order to meet environmental requirements, STMicroelectronics offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an STMicroelectronics trademark. ECOPACK specifications are available at: www.st.com
5.1 DFN10 p ackage
Ref. Dimensions Millimeters Mils A1 0.02 0.05 0.8 2.0 A2 0.70 25.6 A3 0.20 7.9 D 3.00 118.1 E 3.00 118.1 e 0.50 19.7
5.2 MiniSO-8 package
Ref. Dimensions Millimeters Inches A 1.1 0.043 e 0.65 0.026 K 0 °6 ° 0 °6 ° L1 0.10 0.04
6 Revision history
1-Sep-2003 1 Initial release. 1-Oct-2004 2 Curves updated in the document. 2-Jan-2005 4 Update mechanical data on flip-chip package. 2-Apr-2005 4 Remove data on flip-chip package. 15-Nov- 2005 5 Mechanical data updated on DFN10 package. 12-Dec-2006 6 Removed demo board views. Format update.