TS4975_05 STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Stereo Headphone Drive Amplifier with Digital Volume Control via I2C Bus ■ Operating from VCC = 2.5V to 5.5V ■ I²C bus control interface ■ 40mW output power @ V CC =3 . 3 V , THD = 1%, F = 1kHz, with 16 Ω load ■ Ultra-low consumption in stdby mode: 0.6µA ■ Digital volume control range from 18dB to -34dB ■ 14-step digital volume control ■ 9 different output mode selections ■ Pop & click noise reduction circuitry ■ Flip-chip package, 12 x 300µm bumps (lead- free)
Description
The TS4975 is a stereo audio headphone driver capable of delivering up to 102mW per channel of continuous average power into a 16 Ω single- ended load with 1% THD+N from a 5V power supply. The overall gain of these headphone drivers is controlled digitally by volume control registers programmed via the I 2C interface, minimizing the number of external components needed. This device can also easily be driven by an MCU to select the output modes, through the I 2C bus interface. A phantom ground configuration allows one to avoid using bulky capacitors on the outputs of the headphone amplifiers. The TS4975 is packaged in a 1.8mm X 2.3mm Flip Chip package, ideally suited for space- conscious portable applications. It has also an internal thermal shutdown protection mechanism.
Applications
■ Mobile phones (cellular / cordless) ■ PDAs ■ Laptop/notebook computers ■ Portable audio devices Order Codes TS4975EIJT - Flip Chip OUT1 IN1 BYPASS PHG1 VCC SCL PHG2 GND SDA OUT2 IN2 ADD OUT1 IN1 BYPASS PHG1 VCC SCL PHG2 GND SDA OUT2 IN2 ADD Pin out (top view) Part Number Temperature Range Package Packing Marking TS4975EIJT -40, +85°C Flip-chip T ape & Reel A75
1 Absolute Maximum Ratings
Table 1. Key parameters and their absolute maximum ratings Table 2. Operating conditions
- All voltages values are measured with respect to the ground pin.
- The magnitude of input signal must never exceed V CC + 0.3V / GND - 0.3V
- Device is protected in case of over temperature by a thermal shutdown active @ 150°C.
- Exceeding the power derating curves during a long period, may involve abnormal operating condition.
- Human body model, 100pF discharged through a 1.5kOhm resistor, into pin to V CC device.
2 Typical Application Schematics
configuration and in Figure 2, for a phantom ground output configuration. Figure 1. Single-ended configuration
Figure 2. Phantom ground output configuration
3 Electrical Characteristics
Table 3. Electrical characteristics for the I²C interface Table 4. Output noise (all inputs grounded)
- SCL and SDA are CMOS inputs. The nominal input current is about few pA and not 10uA. 10µA refer to the I2C
Table 5. V CC = +2.5 V, GND = 0V, Tamb = 25°C (unless otherwise specified)
- Dynamic measurements - 20*log(rms(V out)/rms(Vripple)). Vripple is an added sinus signal to VCC @ F = 217Hz
Table 6. V CC = +3.3V, GND = 0V, Tamb = 25°C (unless otherwise specified)
- Dynamic measurements - 20*log(rms(V out)/rms(Vripple)). Vripple is an added sinus signal to V CC @ F = 217Hz
Table 7. V CC = +5V, GND = 0V, Tamb = 25°C (unless otherwise specified)
- Dynamic measurements - 20*log(rms(Vout)/rms(V ripple)). Vripple is an added sinus signal to VCC @ F = 217Hz
4 Application Information
as either SE (single-ended) capacitively-coupled output or PHG (phantom ground) output. Section 4.2: Output configuration describes these configurations. This chapter gives information on how to configure the TS4975 in application.
4.1 I²C bus interface
always the slave device and the controlling micro controller MCU is the master device.
- $CCh when the ADD pin is connected to logic low voltage,
- $CEh when ADD pin is connected to logic high voltage. Table 8 summarizes the pin descriptions for the I²C bus interface.
Table 8. I²C bus interface pin descriptions
4.1.1 I²C bus operation
byte consisting of 7-bit slave address and R/W bit. Table 9. The first byte after the START message for addressing the device
- send byte with the I²C 7-bit slave address and with a low level for the R/W bit
- send the data (control register setting) Pin Functional Description SDA This is the serial data pin SCL This is the clock input pin ADD User-setable portion of device’s I2C address A6 A5 A4 A3 A2 A1 A0 R/W 1100 11 A 0 X
All bytes are sent with MSB bit first. The transfer of written data ends with a “stop” message. message and addressing byte with the slave address.
- send byte with the I²C 7-bit slave address and with a high level for the R/W bit
- receive the data (control register value) All bytes are read with MSB bit first. The transfer of read data is ended with “stop” message. When transmitting several data, the data can be read with no need to repeat the “start” message and the byte with slave address. In this case the value of control register is read repeatedly. When the thermo shutdown or pop and click reduction is active, specific values are read from the TS4975 (see Section 4.9: Pop and click performance on page 31 and Section 4.10: Thermo shutdown on page 32 ).
Figure 59. I²C write/read operations Table 10. Ouput mode selection: G from -34 dB to + 18dB (by steps of 4dB) (1)
1 G x In1 G x In2
2 G x In2 G x In1
3 G x In1 G x In1
4 G x In2 G x In2
7 G x In1 SD
8 G x In2 SD
4.1.2 Gain setting operation
channels are set in Standby mode. Table 11. Gain settings truth table Table 12. Output mode settings truth table Table 13. Stand-by mode I²C condition
0 XXX P H G off
Table 14. I²C control byte states
4.1.3 Acknowledge
4.2 Output configuration
that corresponding output is in a high impedance state.
4.2.1 Single-ended configuration
each output is needed to block the V CC/2 voltage and couples the audio signal to the load.
4.2.2 Phantom ground configuration
much poorer crosstalk results.
4.2.3 Shutdown
implemented to reach the best pop performance during chip wake-up.
4.3 Power dissipation and efficiency
- Voltage and current in the load are sinusoidal (V out and Iout).
- Supply voltage is a pure DC source (V CC). Regarding the load we have: and and Single-ended configuration: The average current delivered by the supply voltage is:
Figure 60. Current delivered by supply voltage in single-ended model
Note: This maximum value depends only on power supply voltage and load values. Figure 61. Current delivered by supply voltage in phantom ground mode Note: This maximum value depends only on power supply voltage and load values.
22 V CC
The efficiency is the ratio between the output power and the power supply: The maximum theoretical value is reached when V PEAK = VCC/2, so The TS4975 is a stereo amplifier so it has two independent power amplifiers. Each amplifier produces heat due to its power dissipation. Therefore the maximum die temperature is the sum of each amplifier’s maximum power dissipation. It is calculated as follows: Pdiss 1 = Power dissipation due to the first channel power amplifier. Pdiss 2 = Power dissipation due to the second channel power amplifier. Tot al Pdiss =P diss 1 +P diss 2 (W) In most cases, Pdiss 1 = Pdiss 2, giving: Single ended configuration : Phantom ground configuration:
4.4 Low frequency response
The input coupling capacitor blocks the DC part of the input signal at the amplifier input. In the low-frequency region, Cin starts to have an effect. Cin with Zin forms a first-order, high-pass filter with -3 dB cut-off frequency. Zin is the input impedance of the corresponding input (30 k Ω for In1 & In2). Note: For all inputs, the impedance value remains for all gain settings. This means that the lower cut- off frequency doesn’t change with gain setting. Note also that 30 kΩ is a typical value and there is tolerance around this value (see Chapter 3: Electrical Characteristics on page 5 ). From Figure 53 you could easily establish the C in value for a -3dB cut-off frequency required. η Pout Psupply 4VCC η π 8--- 39.25%== TotalP diss 2Pdiss1= TotalP diss π RL TotalP diss
42 V CC
π RL FCL 2πZin Cin
In single-ended mode the external output coupling capacitors C out are needed. This coupling capacitor Cout with the output load RL also forms a first-order high-pass filter with -3 dB cut off frequency. See Figure 54 to establish the Cout value for a -3dB cut-off frequency required. These two first-order filters form a second-order high-pass filter. The -3 dB cut-off frequency of these two filters should be the same, so the following formula should be respected:
4.5 Decoupling of the circuit
Two capacitors are needed to properly bypass the TS4975 — a power supply capacitor C s and a bias voltage bypass capacitor C b. Cs has a strong influence on the THD+N in high frequency (above 7kHz) and indirectly on the power supply disturbances. With 1 µF , you could expect similar THD+N performances like shown in the datasheet. If Cs is lower than 1 µF , THD+N increases in high frequency and disturbances on power supply rail are less filtered. To the contrary, if Cs is higher than 1 µF, those disturbances an the power supply rail are more filtered. Cb has an influence on THD+N in lower frequency, but its value is critical on the final result of PSRR with input grounded in lower frequency:
- If Cb is lower than 1 µF , THD+N increases at lower frequencies and the PSRR worsens upwards.
- If Cb is higher than 1 µF , the benefit on THD+N and PSRR in the lower frequency range is small. The value of Cb also has an influence on startup time.
4.6 Power-on reset
When power is applied to V CC, an internal Power On Reset holds the TS4975 in a reset state (shutdown) until the supply voltage reaches its nominal value. The Power On Reset has a typical threshold of 1.75V. During this reset state the outputs configuration is the same like in the shutdown mode (see Section 4.2: Output configuration on page 25 ). FCL 2πRLCout 2πZin Cin 2πRLCout
4.7 Notes on PSRR measurement
a device to minimize the impact of power supply disturbance to the output. The PSRR was measured according to the schematic shown in Figure 62. Figure 62. PSRR measurement schematic
- The DC voltage supply (V CC) is fixed
- The AC sinusoidal ripple voltage (V ripple) is fixed
- No bypasss capacitor Cs is used The PSRR value for each frequency is calculated as: RMS is a rms selective measurement. PSRR 20Log RMS Output() RMS Vripple()
4.8 Startup time
startup time will be always lower. Figure 63. Typical startup time versus bypass capacitance
4.9 Pop and click performance
configuration) and the bias voltage bypass capacitor C b. value of Cb will affect the THD+N and PSRR values in lower frequencies. Figure 1 on page 3 and Figure 2 on page 4 ). (1111xxxx binary) can be read from the internal device registry.
4.10 Thermo shutdown
The TS4975 device has internal protection in case of over temperature by thermal shutdown. Thermal shutdown is active when the device reaches temperature 150°C.
4.11 Demoboard
A demoboard for the TS4975 is available. Figure 66, show bottom layer, top layer and the component locations, respectively. Figure 64. Bottom layer Figure 65. Top layer Figure 66. Component location
Figure 67. Demoboard schematic
5 Package Mechanical Data
Figure 68. TS4975 footprint recommendation Figure 69. Pin out (top view) Figure 70. Marking (top view)
- E Lead Free symbol A75 YWW E A75 YWW E
6 Revision History
Nov. 2004 1 Initial release. July 2005 2 Product in full production Nov. 2005 3 The following changes were made in this revision: – Application notes updated – Formatting changes throughout Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this p ublication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicr oelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Ital y - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America