Stereo audio amplifier system with I²C bus interface
Document overview
- Manufacturer or author: STMICROELECTRONICS
- PDF pages: 55
Technical content
Datasheet sections
- 1 Absolute maximum ratings and operating conditions
- 2 Typical application schematic
- 2.1 I 2C interface
- 2.1.1 I²C operation description
- 2.1.2 Gain and mode setting operations
- 2.1.3 Acknowledge bit
- 3 Electrical characteristi cs
- 4 Application information
- 4.1 Output configurations
- 4.1.1 Shutdown
- 4.1.2 Single-ended output configuration (modes 5 and 6)
- 4.1.3 Phantom ground output configuration (modes 3 and 4)
- 4.1.4 BTL output configuration (modes 1, 2, 7)
- 4.2 Power limitation in the phantom ground configuration
- 4.3 Power dissipation and efficiency
- 4.3.1 Single-ended output configuration (modes 5 and 6)
- 4.3.2 Phantom ground output configuration (modes 3, 4):
- 4.3.3 BTL output configuration (modes 1, 2, 7)
- 4.4 Low frequency response
- 4.4.1 Input capacitor C in
- 4.4.2 Output capacitor C out
- 4.5 Single-ended input configuration in modes 1, 3 and
- 4.6 Decoupling of the circuit
- 4.7 Power-on reset
- 4.8 PSRR measurements
- 4.9 Pop and click performance
- 4.10 Thermal shutdown
- 4.11 Demonstration board
Features
■ Operating from VCC = 2.7 V to 5.5 V ■ I2C bus control interface ■ 38 mW output power at VCC =3 . 3V , THD = 1%, F = 1 kHz, with 16 Ω load ■ Ultra low consumption in standby mode: 0.5 µA ■ Digital volume control range from +12 dB to -34 dB ■ 32-step digital volume control ■ Stereo loudspeaker option by I2C ■ 8 different output mode selections ■ Pop and click reduction circuitry ■ Flip-chip package, 18 bumps with 300 µm diameter ■ Lead-free flip chip package ■ Output power limitation on headphone for eardrum damage consideration
Applications
■ Mobile phones (cellular/cordless) ■ PDAs ■ Laptop / notebook computers ■ Portable audio devices
Description
The TS4956 is a complete audio system device with three dedicated outputs, one stereo headphone, one loudspeaker drive and one mono line for a hands-free set. The stereo headphone is capable of delivering more than 25 mW per channel of continuous average power into 16 Ω single-ended loads with 0.3% THD+N from a 5 V power supply. The device functions are controlled via an I 2C bus, which minimizes the number of external components needed. The overall gain and the different output modes of the TS4956 are controlled digitally by the control registers which are programmed via the I²C interface. It has also an internal thermal shutdown protection mechanism. TS4956 - flip-chip 18 Pin connections (top view) RIN LHP- MLO RHP+ MIN VCC SDA LIN VCC GND I2CVCC MIP SRP+ SRN- SCLGND BYPASS PGH RIN LHP- MLO RHP+ MIN VCC SDA LIN VCC GND I2CVCC MIP SRP+ SRN- SCLGND BYPASS PGH Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
1 Absolute maximum ratings and operating conditions
Table 1. Absolute maximum ratings
- All voltage values are measur ed with respect to the ground pin.
- The magnitude of input signal must never exceed V CC + 0.3 V / GND - 0.3 V
- Device is protected in case of over temper ature by a thermal shutdown activated at 150°C.
- Exceeding the power derating curves during a l ong period may involve abnormal operating conditions.
- Human body model, 100 pF discharged through a 1.5 k Ω resistor, into pin to VCC device
Table 2. Operating conditions
- For proper functionality of I2C bus, V CC pins must not be grounded. ESD protection diodes ground data
and clock wires and cause dysfunction of I2C bus in this condition.
- With heat sink surface 120 mm 2.
Table 3. I 2C electrical characteristics
- Must be less than or equal to the power supply voltage V CC of the device.
2 Typical application schematic
Figure 1. Typical application for the TS4956 (modes 1, 2, 3, 4, 5 and 6) Table 4. Description of external components Cs1, Cs2 Supply bypass capacitors which provide power supply filtering. Cb Bypass capacitor which provides half-supply filtering. half-supply voltage on single-ended output. R1 Resistor to keep Cout charged for better pop performance on single-ended output.
8 Ohms
Figure 2. Typical application for the TS4956 (mode 7)
2.1 I 2C interface
TS4956 is always the slave device and the controlling MCU is the master device. connected to this pin must be equal to or less than the TS4956 power supply voltage VCC. The minimum value of the I2CVCC voltage is 2.7 V. 2C commands from the I2C bus. floating) presented in Table 3 on page 4, in order for the circuit to function properly. Table 5 summarizes the pin descriptions for the I²C bus interface.
2.1.1 I²C operation description
control register address is $5Dh. Table 6. First byte after the START message for addressing the device
- send byte with the I²C 7-bit slave address and with the R/W bit set low.
- send the data (control register setting). All bytes are sent with the MSB bit first. The transfer of written data ends with a "stop" message. When transmitting several bits of data, the data can be written without having to repeat the "start" message or address byte with the slave address.
Table 5. I²C bus interface: pin descriptions
- send byte with the I²C 7-bit slave address and with the R/W bit set high.
- receive the data (control register value). All bytes are read with the MSB bit first. The transfer of read data is ended with a "stop" message. When transmitting several bits of data, the data can be read with having to repeat the "start" message and the byte with slave address. In this case the value of the control register is read repeatedly.
Figure 3. I²C read/write operation Table 7. Output mode selection: G from -34.5 dB to + 12 dB (by steps of 1.5 dB) (1)
2 SD SD GX (RIN + LIN) SD
3 GX (MIP + MIN) GX (MIP + MIN) SD SD
4 G x RIN G x LIN SD SD
5 SD SD SD GX (MIP + MIN)
6 SD SD SD GX (RIN + LIN)
7 BTL: G x RIN BTL: G x RIN G x LIN SD
2.1.2 Gain and mode setting operations
Table 8. Gain settings truth table
2.1.3 Acknowledge bit
Table 9. Output mode settings truth table
3 Electrical characteristics
Table 10. V CC = +2.7 V, GND = 0 V, Tamb = 25° C (unless otherwise specified)
- Dynamic measurements - 20*log(rms(V out)/rms(Vripple)). Vripple is an added sinus signal to VCC at f = 217 Hz.
Table 10. V CC = +2.7 V, GND = 0 V, Tamb = 25° C (unless otherwise specified) (continued)
Table 11. V CC = +3.3 V, GND = 0 V, Tamb = 25° C (unless otherwise specified)
20 Hz < F < 20 kHz
- Internal power limitation on headphone ou tputs (see application information).
- Dynamic measurements - 20*log(rms(V out)/rms(Vripple)). Vripple is an added sinus signal to VCC at F = 217 Hz.
Table 11. V CC = +3.3 V, GND = 0 V, Tamb = 25° C (unless otherwise specified) (continued)
Table 12. V CC = +5 V, GND = 0 V, Tamb = 25° C (unless otherwise specified)
- Internal power limitation on headphone ou tputs (see application information).
- Dynamic measurements - 20*log(rms(V out)/rms(Vripple)). Vripple is an added sinus signal to VCC at F = 217 Hz.
Table 12. V CC = +5 V, GND = 0 V, Tamb = 25° C (unless otherwise specified) (continued)
Table 13. Output noise V CC = 2.7 V to 5.5 V (all inputs grounded)
4 Application information
The TS4956 integrates four monolithic power amplifiers and has one differential input and two single-ended inputs. The output amplifiers can be configured in 7 different modes as one SE (single-ended) capacitively-coupled output, two phantom ground headphone outputs and two BTL outputs. Figure 1 on page 5 and Figure 2 on page 6 show these configuration schemes and Table 7 on page 8 describes these configurations in different modes. This chapter gives information on how to configure the TS4956 in an application.
4.1 Output configurations
4.1.1 Shutdown
When the device is in shutdown mode, all of the device’s outputs are in a high impedance state.
4.1.2 Single-ended output configuration (modes 5 and 6)
When the device is woken-up via the I²C interface, output amplifier on output MLO is biased to the VCC/2 voltage. In this configuration an output capacitor, Cout, on the single-ended output is needed to block the VCC/2 voltage and couples the audio signal to the load. VCC/2 voltage is present on this output in all modes (modes 1 to 7) to keep the output capacitor Cout charged and to improve pop performance on this output during the switching between any given mode to mode 5 or 6. When the device is in mode 5 or 6 where the single-ended output MLO is active, all other outputs are in a high impedance state.
4.1.3 Phantom ground outpu t configuration (modes 3 and 4)
In a phantom ground output configuration (modes 3 and 4) the internal buffer is connected to the PHG pin and biased to the VCC/2 voltage. Output amplifiers (pins LHP and RHP) are also biased to the VCC/2 voltage. One end of the load is connected to output amplifier and one to the PHG buffer. Therefore, no output capacitors are needed. The advantage of the PHG output configuration is that there are fewer external components compared to an SE configuration. However, note that in this configuration, the device has a higher power dissipation (see Section 4.3: Power dissipation and efficiency on page 40). All other inactive outputs are in the high impedance state except for the MLO output, which is biased to V CC/2 voltage. To achieve better crosstalk results in this case, each speaker should be connected with a separate PHG wire (two speakers connected with four wires) as shown in Figure 1 on page 5 (instead of using only one common PHG wire for both speakers, that is, two speakers connected with three wires). Obsolete Product(s) - Obsolete Product(s)
4.1.4 BTL output configurat ion (modes 1, 2, 7)
except for the MLO output, which is biased to VCC/2 voltage. BTL means that each end of the load is connected to two single-ended output amplifiers.
4.2 Power limitation in the phantom ground configuration
power is achieved by limiting the output voltage and output current on each amplifier. Ω load resistance and THD+N<1%. limitation with different load resistances. values above 16 Ω and below 32 Ω as explained by Figure 123. Figure 123. Voltage and current limitation on headphones
4.3 Power dissipation and efficiency
- The voltage and current in the load are sinusoidal (Vout and Iout).
- The supply voltage is a pure DC source (VCC). Regarding the load we have: and and
4.3.1 Single-ended output configuration (modes 5 and 6)
Figure 124. Current delivered by supply voltage in a single-ended output configuration
Note: This maximum value depends only on the power supply voltage and load values.
4.3.2 Phantom ground output configuration (modes 3, 4):
Figure 125. Current delivered by supply voltage in a phantom ground output Note: This maximum value depends only on the power supply voltage and load values.
22 V CC
The efficiency is the ratio between the output power and the power supply. sum of each amplifier’s maximum power dissipation. It is calculated as follows. diss 1 = power dissipation due to the first power amplifier. Pdiss 2 = power dissipation due to the second power amplifier.
4.3.3 BTL output configur ation (modes 1, 2, 7)
Figure 126. Current delivered by supply voltage in a BTL output configuration
42 V CC
and the maximum value is obtained when: and its value is: Note: This maximum value depends only on the power supply voltage and load values. The efficiency is the ratio between the output power and the power supply. The maximum theoretical value is reached when VPEAK = VCC, so The TS4956 has one active output BTL power amplifier when in modes 1 and 2. In mode 7, the TS49656 has two active output BTL power amplifiers. Each amplifier produces heat due to its power dissipation. Therefore the maximum die temperature is the sum of each amplifier’s maximum power dissipation. It is calculated as follows.
- Pdiss 1 = power dissipation due to the first BTL power amplifier.
- Pdiss 2 = power dissipation due to the second BTL power amplifier.
- Total Pdiss =P diss 1 +P diss 2 (W) In most cases, Pdiss 1 = Pdiss 2, giving: Pout∂ ∂Pdiss 0= Pdiss MAX 2VCC π2RL η Pout Psupply 4VCC η π 4--- 78.5%== TotalP diss 2Pdiss1= TotalP diss
π RL Obsolete Product(s) - Obsolete Product(s)
4.4 Low frequency response
4.4.1 Input capacitor C in
pass filter with -3 dB cut-off frequency. Zin is the input impedance of the corresponding input. establish the Cin value required for a -3 dB cut-off frequency. Figure 127. 3dB lower cutoff frequency vs. input capacitance
4.4.2 Output capacitor C out
In the single-ended configuration an external output coupling capacitor, Cout, is needed. filter with -3 dB cut off frequency. See Figure 128 to establish the Cout value for a -3 dB cut-off frequency required.
Figure 128. 3dB lower cut off frequency vs. output capacitance
4.5 Single-ended input configuration in modes 1, 3 and 5
input in modes where the differential inputs are active (modes 1, 3 and 5). Figure 129 illustrates this configuration. Figure 129. Single-ended input in modes 1, 3 and 5 for a typical application
4.6 Decoupling of the circuit
Two capacitors are needed to properly bypass the TS4956 — a power supply capacitor C s and a bias voltage bypass capacitor Cb. Cs has a strong influence on the THD+N at high frequencies (above 7 kHz) and indirectly on the power supply disturbances. With a Cs value of about 1 μF , you can expect to obtain THD+N performances similar to those shown in the datasheet. If Cs is lower than 1 μF , THD+N increases in high frequency and disturbances on power supply rail are less filtered. On the contrary, if Cs is higher than 1 μF , disturbances on the power supply rail are more filtered. Cb has an influence on THD+N at lower frequencies, but its value has critical impact on the final result of PSRR with inputs grounded at lower frequencies:
- If Cb is lower than 1μF , THD+N increases at lower frequencies and the PSRR worsens upwards.
- If Cb is higher than 1 μF , the benefit on THD+N and PSRR in the lower frequency range is small. The value of Cb also has an influence on startup time.
4.7 Power-on reset
When power is applied to VCC, an internal power-on reset holds the TS4956 in a reset state (shutdown) until the supply voltage reaches its nominal value. The power-on reset has a typical threshold of 1.75 V. During this reset state the output configuration is the same as in the shutdown mode. Obsolete Product(s) - Obsolete Product(s)
4.8 PSRR measurements
ability of a device to minimize the impact of power supply disturbance to the output. The PSRR was measured with the TS4956 configured as shown in Figure 130. Figure 130. Configuration of TS4956 for PSRR measurement
- The DC voltage supply (VCC) is fixed.
- The AC sinusoidal ripple voltage (Vripple) is fixed.
- No bypass capacitor Cs is used. The PSRR value for each frequency is calculated as: RMS is a rms selective measurement. F F E E D D C C B B A A Bias control Select I2C Mode TS4956 LHP MLO PHG RHP LHP Amplifier Speaker Amplifier RHP Amplif ier PHG Amplifier SCL SDA I2CVCCBYPASS Digital volume SRP+ SRN- MLO Amplifier Stereo Stereo Input Left Input Right LIN RIN Stereo Stereo Input Left Input Right MIP MIN GND GND Vcc Vcc +Cb 1µF
16 Ohms
10 Ohms
4.9 Pop and click performance
The TS4956 has an internal pop and click reduction circuitry which eliminates the output transients, such as, for example, during switch-on or switch-off phases, or during a switch from one output mode to another, or when changing the volume. The performance of this circuitry is closely linked to the values of the input capacitor C in, the output capacitor Cout (for single-ended configuration) and the bias voltage bypass capacitor Cb. The values of Cin and Cout are determined by the lower cut-off frequency value requested. The value of Cb will affect the THD+N and PSRR values at lower frequencies. The TS4956 is optimized to have low pop and click in the typical schematic configurations (Figure 1 on page 5 and Figure 2 on page 6).
4.10 Thermal shutdown
The TS4956 device has an internal thermal shutdown protection in the event of extreme temperatures. Thermal shutdown is active when the device reaches a temperature of 150° C. Obsolete Product(s) - Obsolete Product(s)
4.11 Demonstration board
A demonstration board for the TS4956 is available. which you can find on www.st.com. Figure 131. Demonstration board schematic for the TS4956
5 Package information
specifications, grade definitions and product status are available at: www.st.com. Figure 132. 18-bump flip-chip package Figure 133. Footprint recommendations
5.2 Daisy chain sample
Figure 137. Top view of daisy chain sample
6 Ordering information
Table 14. Order code for daisy chain sample Table 15. Order codes
7 Revision history
Table 16. Document revision history 01-Nov-2005 1 First release corresponding to the preliminary data version. 01-Dec-2005 2 Cancellation of the back coating sale type. 01-May-2006 3 Final datasheet. Chapter 3: Electrical characteristics.