TS488 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 32
Technical content
Datasheet sections
- 1 Typical application schematic
- 2 Absolute maximum ratings and operating conditions
- 3 Electrical characteristics
- 4 Application information
- 4.1 Power dissipation and efficiency
- 4.2 Total power dissipation
- 4.3 Lower cut-off frequency
- 4.4 Higher cut-off frequency
- 4.5 Gain setting
- 4.6 Decoupling of the circuit
- 4.7 Standby mode
- 4.8 Wake-up time
- 4.9 POP performance
- 5 Package mechanical data
- 5.1 MiniSO-8 package
- 5.2 DFN8 package
- 6 Ordering information
- 7 Revision history
Features
■ Pop and click noise protection circuitry ■ Operating range from VCC = 2.2V to 5.5V ■ Standby mode active low (TS488) or high (TS489) ■ Output power: – 120mW @5V, into 16 Ω with 0.1% THD+N max (1kHz) – 55mW @3.3V, into 16 Ω with 0.1% THD+N max (1kHz) ■ Low current consumption: 2.7mA max @5V ■ Ultra low standby current consumption: 10nA typical ■ High signal-to-noise ratio ■ High crosstalk immunity: 102dB (F = 1kHz) ■ PSRR: 70dB typ. (F = 1kHz), inputs grounded @5V ■ Unity-gain stable ■ Short-circuit protection circuitry ■ Available in lead-free MiniSO-8 & DFN8 2mm x 2mm
Description
The TS488/9 is an enhancement of TS486/7 that eliminates pop and click noise and reduces the number of external passive components. The TS488/9 is a dual audio power amplifier capable of driving, in single-ended mode, either a 16Ω or a 32Ω stereo headset. Capable of descending to low voltages, it delivers up to 31mW per channel (into 16Ω loads) of continuous average power with 0.1% THD+N in the audio bandwidth from a 2.5V power supply. An externally-controlled standby mode reduces the supply current to 10nA (typ.). The unity gain stable TS488/9 is configured by external gain- setting resistors.
Applications
■ Headphone amplifier ■ Mobile phone, PDA, computer motherboard ■ High-end TV, portable audio player TS488IST - MiniSO-8 OUT (1) BYPASS GND VCC OUT (2) VIN (2) SHUTDOWN VIN (1) 8OUT (1) BYPASS GND VCC OUT (2) VIN (2) SHUTDOWN VIN (1) 8OUT (1) BYPASS GND VCC OUT (2) VIN (2) SHUTDOWN VIN (1) OUT (1) BYPASS GND VCC OUT (2) VIN (2) SHUTDOWN VIN (1) 8OUT (1) BYPASS GND VCC OUT (2) VIN (2) SHUTDOWN VIN (1) TS488IQT - DFN8 TS489IQT - DFN8 TS489IST - MiniSO-8 Bypass GND Shutdown Vcc OUT (2) OUT (1) 7 VIN (2) VIN (1) Bypass GND Shutdown Vcc OUT (2) OUT (1) 7 VIN (2) VIN (1) Bypass GND Shutdown Vcc OUT (2) OUT (1) 77 VIN (2) VIN (1) Bypass GND Shutdown Vcc OUT (2) OUT (1) 7 VIN (2) VIN (1) Bypass GND Shutdown Vcc OUT (2) OUT (1) 77 VIN (2) VIN (1)
1 Typical application schematic
Figure 1. Typical application for the TS488-TS489 Table 1. Application component information Inverting input resistor that sets the closed loop gain in conjunction with Rfeed. This resistor also forms a high pass filter with Cin (Fc = 1 / (2 x Pi x Rin x Cin)). Cin1,2 Input coupling capacitor that blocks the DC voltage at the amplifier’s input terminal. Feedback resistor that sets the closed loop gain in conjunction with Rin. AV= Closed Loop Gain= -Rfeed/Rin. Cs Supply output capacitor that provides power supply filtering. Cb Bypass capacitor that provides half supply filtering. Output coupling capacitor that blocks the DC voltage at the load input terminal. This capacitor also forms a high pass with RL (Fc = 1 / (2 x Pi x RL x Cout)).
2 Absolute maximum ratings and operating conditions
Table 2. Absolute maximum ratings
- All voltage values are measur ed with respect to the ground pin.
- P diss is calculated with Tamb = 25°C, Tj = 150°C.
- Attention must be paid to continuous power dissipation (VDD x 250mA). Short-circuits can cause excessive
dramatically reduce the product’s life expectancy. Table 3. Operating conditions
- The minimum current consumption (I STBY) is guaranteed at GND (TS488) or VCC (TS489) for the whole
- When mounted on a 4-layer PCB.
3 Electrical characteristics
Table 4. Electrical characteristics at V CC =+ 5 V
- Guaranteed by design and evaluation.
Table 5. Electrical characteristics at V CC =+ 3 . 3 V
- All electrical values ar e guaranteed with correlation measurements at 2.5V and 5V.
- Guaranteed by design and evaluation.
Table 6. Electrical characteristics at V CC =+ 2 . 5 V
- Guaranteed by design and evaluation.
Table 7. Index of graphics
4 Application information
4.1 Power dissipation and efficiency
■ Voltage and current in the load are sinusoidal (Vout and Iout). ■ Supply voltage is a pure DC source (VCC). Figure 78. Current delivered by power supply voltage in single-ended configuration
03 T / 2 2 T
and its value is: Note: This maximum value depends only on power supply voltage and load values. The efficiency is the ratio between the output power and the power supply: The maximum theoretical value is reached when Vpeak = VCC/2, so
4.2 Total power dissipation
The TS488/9 is stereo (dual channel) amplifier. It has two independent power amplifiers. Each amplifier produces heat due to its power dissipation. Therefore the maximum die temperature is the sum of each amplifier’s maximum power dissipation. It is calculated as follows: ■ Pdiss R = Power dissipation due to the right channel power amplifier. ■ Pdiss L = Power dissipation due to the left channel power amplifier. ■ Total Pdiss =P diss R +P diss L (W) Typically, Pdiss R is equal to Pdiss L, giving:
4.3 Lower cut-off frequency
The lower cut-off frequency FCL of the amplifier depends on input capacitors Cin and output capacitors Cout. The input capacitor Cin (output capacitor Cout) in serial with the input resistor Rin (load resistor RL) of the amplifier is equivalent to a first order high pass filter. Assuming that FCL is the lowest frequency to be amplified (with a 3dB attenuation), the minimum value of the Cin (Cout) is: Pdiss MAX VCC π2RL η POUT Psupply 2VCC η π 4--- 78.5%== TotalP diss 2PdissR 2PdissL== TotalP diss
22 V CC
π RL Cin Cout
CL and a roll-off 40db⁄ decade.
4.4 Higher cut-off frequency
Figure 79. Lower cut-off frequency vs. Figure 80. Lower cut-off frequency vs. Figure 81. Higher cut-off frequency vs. feedback capacitor
4.5 Gain setting
4.6 Decoupling of the circuit
Cs and a bias voltage bypass capacitor Cb. ■ If Cb is lower than 1µF, the THD+N improves and the PSRR worsens. ■ If Cb is higher than 1µF, the benefit on the THD+N and PSRR is small. lower the value of Cin, the higher the PSRR.
4.7 Standby mode
(see Figure 82). A time required to change the internal circuit is a few microseconds. Figure 82. Internal equivalent schematic of the TS488 (TS489) in standby mode
4.8 Wake-up time
characteristics table with Cb = 1µF . can be read directly from Figure 83. Figure 83. Typical wake-up time vs. bypass capacitance
4.9 POP performance
dependent on the lower cut-off frequency and PSRR values requested.
With the values above, the result is FCL=25Hz. In this case, τ in = Rin xC in=6.6ms. This value is sufficient with regard to the previous formula, thus we can state that the pop is imperceptible. Connecting the headphones Generally headphones are connected using jack connectors. To prevent a pop in the headphones when plugging in the jack, a pulldown resistor should be connected in parallel with each headphone output. This allows the capacitors C out to be charged even when the headphones are not plugged in. Pulldown resistors with a value of 1 kΩ are high enough to be a negligible load, and low enough to charge the capacitors Cout in less than one second. Note: The pop&click reduction circuitry works properly only when both channels have the same value for the external components Cin, Cout, Rload and Rpulldown.
5 Package mechanical data
In order to meet environmental requirements, STMicroelectronics offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an STMicroelectronics trademark. ECOPACK specifications are available at: www.st.com
5.1 MiniSO-8 p ackage
5.2 DFN8 p ackage
DIM. mm. inch A1 0.02 0.05 0.001 0.002 A3 0.15 0.006 D 2.00 0.079 E 2.00 0.079 aaa 0.15 0.006 bbb 0.10 0.004 ccc 0.10 0.004 QFN8 (2x2) MECHANICAL DATA aaa C aaa C 2x (D/2 xE/2)
4 INDEX AREA
0.08 C NX8 A B C bbb C A B 7(D/2 xE/2) INDEX AREA BOTTOM VIEW SIDE VIEW PIN#1 ID D E A e NX b NX L Exposed Pad NX k D
6 Ordering information
Table 8. Order codes
7 Revision history
Table 9. Document revision history 2-Jan-2006 1 First release corresponding to the product preview version. Minor grammatical and formatting corrections throughout. Update of DFN8 package height.