TS4621B.fm
Document overview
- Manufacturer or author: STMICROELECTRONICS
- PDF pages: 48
Technical content
Datasheet sections
- 1 Absolute maximum ratings and operating conditions
- 2 Typical application sc hematics
- 3 Electrical characteristi cs
- 4 Application information
- 4.1 I 2C bus interface
- 4.1.1 I²C bus operation
- 4.1.2 Control register CR1 - address
- 4.1.3 Control register CR2 - address
- 4.1.4 Control register CR3 - address
- 4.1.5 Summary of output impedance
- 4.2 Wake-up and standby time definition
- 4.3 Overview of the class-G, 2-level headphone amplifier
- 4.4 External component selection
- 4.4.1 Step-down inductor selection (L1)
- 4.4.2 Step-down output capacitor selection (Ct)
- 4.4.3 Full capacitive inverter capacitors selection (C12 and Css)
- 4.4.4 Power supply decoupling capacitor selection (Cs)
- 4.4.5 Input coupling capacitor selection (Cin)
- 4.4.6 Low-pass output filter (Rout and Cout) and
- 4.4.7 Integrated input low-pass filter
- 4.5 Single-ended input configuration
- 4.5.1 Layout recommendations for single-ended operation
- 4.6 Startup phase
- 4.6.1 Auto zero technology
- 4.6.2 Input impedance
- 4.7 Layout recommendations
- 4.7.1 Common mode sense layout
- 4.8 Demonstration board
- 5 Package information
Features
■ Power supply range: 2.3 V to 4.8 V ■ 0.6 mA/channel quiescent current ■ 2.1 mA current consumption with 100 µW/channel (10 dB crest factor) ■ 0.006% typical THD+N at 1 kHz ■ 100 dB typical PSRR at 217 Hz ■ 100 dB of SNR A-weighted at G = 0 dB ■ Zero pop and click ■ I2C interface for volume control ■ Digital volume control range from -60 dB to +4 dB ■ Independent right and left channel shutdown control ■ Integrated high-efficiency step-down converter ■ Low software standby current: 5 µA max ■ Output-coupling capacitors removed ■ Thermal shutdown ■ Flip-chip package: 1.65 mm x 1.65 mm, 400 µm pitch, 16 bumps
Applications
■ Cellular phones, smart phones ■ Mobile internet devices ■ PMP/MP3 players
Description
The TS4621B is a class-G stereo headphone driver dedicated to high audio performance, high power efficiency and space-constrained applications. It is based on the core technology of a low power dissipation amplifier combined with a high- efficiency step-down DC/DC converter for supplying this amplifier. When powered by a battery, the internal step- down DC/DC converter generates the appropriate voltage to the amplifier depending on the amplitude of the audio signal to supply the headsets. It achieves a total 2.1 mA current consumption at 100 µW output power (10 dB crest factor). THD+N is 0.02 % maximum at 1 kHz and PSRR is 100 dB at 217 Hz, which ensures a high audio quality of the device in a wide range of environments. The traditionally bulky output coupling capacitors can be removed. A dedicated common-mode sense pin removes parasitic ground noise. The TS4621B is designed to be used with an output serial resistor. It ensures unconditional stability over a wide range of capacitive loads. The TS4621B is packaged in a tiny 16-bump flip-chip package with a pitch of 400 µm. TS4621BEIJT - flip-chip Balls are underneath Pinout (top view) AVDD SWINL- CMS SDA AGND HPVDD VOUTL VOUTR INL+ INR+ PVSS SCLINR- 4321 A B C D AVDD SWINL- CMS SDA AGND HPVDD VOUTL VOUTR INL+ INR+ PVSS SCLINR- 4321 A B C D Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
1 Absolute maximum ratings and operating conditions
Table 1. Absolute maximum ratings VCC Supply voltage (1) during 1ms.
- All voltage values are measur ed with respect to the ground pin.
- Thermal shutdown is activated when ma ximum junction temperature is reached.
- The device is protected from ov er-temperature by a thermal shutdown mechanism, active at 150° C.
- Exceeding the power derating curves for long periods may provoke abnormal operation.
- Human body model: a 100 pF capacit or is charged to the specified voltage, then discharged through a
while the other pins are floating.
- Machine model: a 200 pF capacitor is charged to the specified voltage, then discharged directly between
connected pin combinations while the other pins are floating.
- The measurement is performed on an evaluati on board, with ESD protection EMIF02-AV01F3.
Table 2. Operating conditions
2 Typical application schematics
Figure 1. Typical application schematics for the TS4621B Table 3. TS4621B pin description
Table 4. TS4621B component description (1) recommended to minimize ΔC/ΔV when VCC =4 . 8V .
6.3 V rating voltage is recommended to minimize ΔC/ΔV when
mandatory for operation of the TS4621B. resistor is mandatory for operation of the TS4621B. L1 3.3 µH Inductor for internal DC/DC step-down converter. References of inductors: refer to Section 4.4.1 for more information.
- Refer to Section 4.4 for a complete description of each component.
3 Electrical characteristics
Table 5. Electrical characteristics of the I²C interface Table 6. Electrical characteristics of the amplifier
- Guaranteed by design and parameter correlation.
- Refer to the application information in Section 4.2 on page 30.
Figure 10. Maximum output power vs. power Figure 11. Maximum output voltage vs. power
10 KΩ600 Ω
Figure 12. Maximum output voltage vs. power Figure 13. Current consumption vs. total Figure 14. Current consumption vs. total Figure 15. Current consumption vs. total
Figure 70. Wake-up time Figure 71. Shutdown time
4 Application information
4.1 I 2C bus interface
microcontroller MCU is the master device. The slave address of the TS4621B is 1100 000x (C0h). Table 8 summarizes the pin descriptions for the I²C bus interface.
4.1.1 I²C bus operation
registers can be accessed. In write mode, only CR1, CR2 and CR3 can be addressed. Table 8. Pin description of the I²C bus interface Table 9. First byte after the START message for addressing the device Table 10. Summary of control registers
Table 11. Control registers at power-up
- send the I²C 7-bit slave address and a low level for the R/W bit.
- send the register address to write to.
- send the data bytes (control register settings). All bytes are sent MSB first. The transfer of written data ends with a "stop" message. When transmitting several data bytes, the data can be written without having to repeat the "start" message or send the byte with the slave address. If several bytes are transmitted, they will be written repeatedly to CR1, CR2 and CR3.
Figure 72. I²C write operations
- send the I²C 7-bit slave address and a low level for the R/W bit.
- send the register address to read.
- send the I²C 7-bit slave address and a high level for the R/W bit.
- receive the data (control register value). All bytes are read MSB first. The transfer of read data ends with a "stop" message. When transmitting several data bytes, the data can be read without having to repeat the "start" message or send the byte with the slave address. If several bytes are transmitted, they are read repeatedly from CR1, CR2, CR3 and CR4. Description Register address D7 D6 D5 D4 D3 D2 D1 D0 CR1 1 0 0 0 0 0 0 0 1 CR2 2 1 1 0 0 0 0 0 0 CR3 3 0 0 0 0 0 0 0 0 CR4 4 0 1 0 0 0 0 0 0 SDA S 11 00 0 0 ACK00 A 7 D7A0A1 ACK P Start condition SLAVE DEVICE ADDRESS DATA BYTES R/W Acknowledge from slave Acknowledge from slave Stop condition A6 D6 D1 D0 D7 D6 D1 D0 REGISTER ADDRESS CR X CRX+1 ACK ACK AM06115 Obsolete Product(s) - Obsolete Product(s)
Figure 73. I²C read operations1
4.1.2 Control regist er CR1 - address 1
the output current threshold will not be reached. modulation on the inputs of the TS4621B. This detection is depicted in Figure 74. Figure 74. Flowchart for short-circuit detection
If a short-circuit is detected three consecutive times on one channel, a flag is raised in the I²C read register CR1.
- SC_L: equals 0 during normal operation, equals 1 when a short-circuit is detected on the left channel.
- SC_R: equals 0 during normal operation, equals 1 when a short-circuit is detected on the right channel. The corresponding channel’s output stage is then set to high impedance mode. An I²C read command allows the reading of the SC_L and SC_R flags but does not reset them. An I²C write command has to be sent to CR1 to reset the flags to 0 and restore normal operation. Thermal shutdown protection: bit T_SH A thermal shutdown protection is implemented to protect the device from overheating. If the temperature rises above the thermal junction of 150°C, the device is put into standby mode and a flag is raised in the read register CR1.
- T_SH: equals 0 during normal operation, equals 1 when a thermal shutdown is detected. When the temperature decreases to safe levels, the circuit switches back to normal operation and the corresponding flag is cleared. Software shutdown: bit SWS When SWS equals 1, the device is set to I²C software shutdown. When SWS equals 0, the negative supply and buck converters are activated. Channel activation: bits HP_EN_L and HP_EN_R When HP_EN_L or HP_EN_R equals 1, the corresponding amplifier channel is enabled. Obsolete Product(s) - Obsolete Product(s)
4.1.3 Control regist er CR2 - address 2
MUTE_R are set to 0, the I²C gain level is applied to the channel.
4.1.4 Control regist er CR3 - address 3
headphone jack with the audio and composite video signal. To set this mode, you must set the HIZ bit to 1 for the targeted output in the CR3 register.
- Maximum input voltage = -1.8 to +1.8 V
- Output impedance = input impedance detected by the video driver. For an example, refer to Chapter 3: Electrical characteristics on page 10 or Figure 18.
Table 12. Volume control register CR2 - address 2
4.1.5 Summary of output impedance
4.2 Wake-up and standby time definition
wake-up start procedure is as follows.
- The master sends a start bit.
- The master sends the device address.
- The slave (TS4621B) answers by an acknowledge bit.
- The master sends the register address.
- The slave (TS4621B) answers by an acknowledge bit.
- The master sends the output mode configuration (CR1).
- If the TS4621B was previous ly in standby mode, the wake-up starts on the falling edge
of the eighth clock signal (SCL) corresponding to the CR1 byte.
- After 12 ms (de-pop sequence time), the TS4621B outputs are operational.
2C bus, the standby time operates as follows.
- The master sends a start bit.
- The master sends the device address.
- The slave (TS4621B) answers by an acknowledge bit.
- The master sends the register address.
- The slave (TS4621B) answers by an acknowledge bit.
- The master sends the output mode configuration (CR1), which corresponds, in this
- The standby time starts on the falling edge of the eighth clock signal (SCL)
corresponding to the CR1 byte.
- After 100 µs, the TS4621B is in standby mode.
Table 13. Summary table for output impedance vs. output mode
4.3 Overview of the class-G, 2-level headphone amplifier
device, the power supply uses two levels: ±1.2 V and ±1.9 V.
0 V, thus eliminating the classical bulky DC blocking output capacitors (typically more than
Figure 75. TS4621B architecture
4.4 External component selection
component is described in the following sections.
4.4.1 Step-down i nductor selection (L1)
- Typical value: 2.2 µH to 3.3 µH (3.3 µH is recommended).
- Maximum current in operating mode: 400 mA
- Minimum inductor value at maximum current: 1.5 µH
- Maximum inductor value at zero current: 4.3 µH
- DC resistance: from 50 mΩ up to 450 mΩ Table 14 shows the part number that should be used according to the inductor value.
4.4.2 Step-down output capacitor selection (Ct)
For the internal DC/DC step-down converter, the TS4621B needs one output capacitor. avoid oscillation of the converter. Therefore the following constraints must be observed.
- Typical capacitor value: 10 µF at DC = 0 V
- Maximum capacitor value: 12 µF at DC = 0 V
- Minimum capacitor value: 4.8 µF at DC = 2 V
- Voltage range across this capacitor: from 1.1 V to 2 V
- Minimum DC ESR value: 5 mΩ A ceramic capacitor in a 0603-type package is also recommended because of its close placement to the TS4621B, which makes it easier to minimize parasitic inductance and resistance that have a negative impact on the audio performance.
Table 14. Recommended inductor
4.4.3 Full capacitive inverter capacit ors selection (C12 and Css)
Two capacitors (C12 and Css) are needed for this internal DC/DC inverter. including self tolerance, DC variation and the minimum ESR to minimize power losses.
- Typical capacitor value: 2.2 µF +/-20 %
- Voltage across these capacitors: from 1.1 V to 2 V
- Minimum capacitor value: 1 µF Again, a ceramic capacitor in a 0603 or 0402-type package is also recommended because of their close placement to the TS4621B, which makes it easier to minimize parasitic inductance and resistance that have a negative impact on the audio performance.
4.4.4 Power supply decoupli ng capacitor selection (Cs)
consideration the ΔC/ΔV variation of this type of ceramic capacitor. bias variation rated at 6.3 V.
4.4.5 Input coupling c apacitor selection (Cin)
DC component coming from the audio signal source. Rin is the single-ended input impedance that can be approximated at about Rindiff/2. Rin also depends on the gain setting. Figure 19 provides the differential input impedance vs. gain. One can also see that Rindiff is minimum for the maximum gain setting (that is, 4 dB). Table 15. Recommended capacitor
Therefore, in most cases, Rin should be set to 4 dB to calculate the minimum input capacitor Cin. Example: At maximum gain G = 4 dB, Rindiff/2 = kΩ/2 = 17 kΩ. However, to take into consideration the worst case, one has to use Rindiff/2 = 25 kΩ/2 = 12.5 kΩ. In this case and for a -3 dB cutoff frequency of 20 Hz, Cin = 0.64 µF . The closest normalized value is 0.68 µF but a 1 µF capacitor is more suitable to take into consideration the capacitor tolerance +/-20 %. If the aim is to have the 20 Hz at -1 dB, the capacitor has to be multiplied by 1.96. As such,
4.4.6 Low-pass output filter (Rout and Cout) and IEC 61000-4-2 ESD
The TS4621B is designed to operate with a passive first-order low-pass filter (as shown in Figure 1.). This low-pass filter is mandatory to ensure correct operation of the TS4621B over the volume range and output capacitance range vs. load. Rout must have a value of 12Ω minimum and Cout a value of 0.8 nF minimum up to 100 nF maximum. Values of 12 Ω and 1 nF are a good starting point for a design to be able to drive a classic headphone (16 Ω, 32 Ω, 60 Ω) and the line-in of any Hi-fi system or sound card. The cutoff frequency of this filter (12 Ω and 1 nF) is approximately 13 MHz and clearly above the audio band. However, this output RC filter is also a part of the IEC 61000-4-2 ESD protection. In most cases, this RC filter is designed with transient absorbers and the final solution can be a discrete solution or an integrated solution. ST Microelectronics’ portfolio has many integrated solutions for ESD, but one dedicated to headphone amplifiers in particular: IPAD (a) reference EMIF02-AV01F3. To fit the IEC 61000-4-2 standard, this audio line IPAD can be added to the output of the TS4621B as shown in Figure 78. a. Copyright STMicroelectronics. Obsolete Product(s) - Obsolete Product(s)
Figure 78. Typical application schematic with IEC 61000-4-2 ESD protection
- 15 kV (air discharge)
- 8 kV (contact discharge) This IPAD has an internal series resistor Rout = 15 Ω +/-20 % and an output capacitor Cout = 3.2 nF +/-25 %.
4.4.7 Integrated i nput low-pass filter
present on each input and filters any out-of-band audio noise coming from the audio source.
4.5 Single-ended input configuration
same value to keep the same PSRR performance as in a differential input configuration. done on the ground of the audio source and not on the ground of the TS4621B itself.
With reference to Figure 80., note that the absolute phase in the audio band is 180°.
4.5.1 Layout recommendati ons for single-ended operation
The connection location of each input that has to be set to ground is extremely important. Figure 81. Incorrect ground connection for single-ended option voltage can be expressed by the following simplified equation from an AC point of view. audio source device (no parasitic AC voltage), it is not necessarily the case for Vgndnoise.
the audio signal and grounded with the ground of the audio source. Figure 82. Correct ground connection for single-ended option
4.6 Startup phase
The TS4621B uses different techniques to reduce the DC current consumption and offer a pop-and-click performance close to none.
4.6.1 Auto zero technology
During the start-up phase, the differential output voltage is sensed and adjusted to 0 V (+/-500 μV) to avoid any pop noise when the amplifier becomes operational. This also helps to minimize extra current consumption due to the load (Icc-extra = VoutDC / Rload).
4.6.2 Input impedance
The TS4621B requires input coupling capacitors. The usual lowest frequency used for the headphone is close to 20 Hz. This frequency means a constant time for a first-order high- pass filter of approximately 1 / (2 x Pi x 20) = 8 ms. To achieve 95 % of the capacitor’s charge, it is necessary to wait 3 x 8 ms = 24 ms, which is out of range for a device with a fast start-up time. Because of the mismatching of all input capacitors and input resistors, if it is decided to start the TS4621B at a time of 8 ms, a voltage difference at the inputs (multiplied by the gain) can create a voltage step on the output and consequently a pop noise. To avoid this issue during the starting phase, the TS4621B accelerates the charging of the input capacitors by reducing the input impedance to 2 kΩ. In such a case, for a 1μF capacitor the 95 % charge is reached in 6 ms. As the start-up time of TS4621B is 12 ms, there remains sufficient time to fully charge the input capacitors and as such eliminate any pop noise.
4.7 Layout recommendations
Particular attention must be given to the correct layout of the PCB traces and wires between the amplifier, load and power supply (in most cases, the battery of the cellular phone). The power and ground traces are critical since they must provide adequate energy and grounding for all circuits. Good practice is to use short and wide PCB traces to minimize voltage drops and parasitic inductance. A track with a width of at least 200 μm for a copper thickness of 18 μm is recommended for bringing energy to the amplifier from the battery. Proper grounding guidelines help improve audio performances, minimize crosstalk between channels, and prevent switching noise from coupling into the audio signal. It is also recommended to use a large-area and multi-via ground plane to minimize parasitic impedance. A multi-layer PCB board allows double or multiple ground planes to be implemented. Most of the time, the top and bottom layers are used as ground planes and provide shielding for tracks routed on the intermediate layers. In addition, to minimize parasitic impedance over the entire surface, a multi-via technique that connects the bottom and top layer ground planes together in many locations is often used. The copper traces that connect the output pins to the load and supply pins should be as wide as possible to minimize the trace resistances. Obsolete Product(s) - Obsolete Product(s)
4.7.1 Common mode sense layout
can create parasitic noise in the headphone and/or line out. removed from the TS4621B outputs. Figure 83. Common mode sense layout example
4.8 Demonstration board
A demonstration board is available at www.st.com with the order code STEVAL-CCA025V1. Figure 84. Demonstration board schematic
5 Package information
specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 87. TS4621B footprint recommendation Figure 88. Pinout
6 Ordering information
Table 16. Order codes
7 Revision history
Table 17. Document revision history 06-Sep-2011 1 Initial release.