TS4405P TSC | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 3
Technical content
Features
- -4.9A, -12V R DS(ON) =5 0 m Ω at -4.5 Volts
- -4.4A, -12V R DS(ON) =7 0 m Ω at -2.5 Volts
- -4.0A, -12V RDS(ON) = 90mΩ at -1.8 Volts
- Low profile package: less than 0.8mm height when mounted on PCB.
- Occupies only 1.21 mm2 of PCB area. Less than 30% of the area of a SC-70.
- Excellent thermal characteristics.
- Lead free solder bumps available. PRELIMINARY DATA SHEET For information only 1 6/8/03 Rev0 Bump Side View SS GD
Electrical Characteristics TA=25°C unless otherwise specified 2 6/8/03 Rev0 Symbol Parameter Test Condition Min Typ Max Units V(BD)SS Drain-Source Breakdow n Voltage VGS=0V, ID=-250µA -11 V IDSS Zero Gate Voltage Drain Current VDS=-12V, VGS=0V -1 µA Zero Gate Voltage Drain Current VDS=-12V, VGS=0V, T=70°C -5 µA IGSS Gate-Body Leakage VGS=±8V, VDS=0V ±100 nA VGS(th) Gate Threshold Voltage VDS=VGS, ID=-250µA -0,58 V Drain-Source On-State Resistance VGS=-4.5V, ID=-1A 50 m Ω Drain-Source On-State Resistance VGS=-2.5V, ID=-1A 70 m Ω Drain-Source On-State Resistance VGS=-1.8V, ID=-1A 90 m Ω Cis s Input Capacitance VDS=-12V, VG=0V, F=1MHZ 300 pF Coss Output Capacitance VDS=-12V, VG=0V, F=1MHZ 200 pF Crss Reverse Transfer Capacitance VDS=-12V, VG=0V, F=1MHZ 80 pF Qg Total Gate Charge VGS=-4.5V, ID=-4A, VDS=-8V 10 nC Qgs Gate Source-Charge VGS=-4.5V, ID=-4A, VDS=-8V 2 nC Qgd Gate Drain-Charge VGS=-4.5V, ID=-4A, VDS=-8V 1 nC VSD Diode Forw ard Voltage IS=-4A, VGS=0V 0.7 V rDS(on) PRELIMINARY DATA SHEET TS4405P
Dimensional Outline and Pad Layout 0.50mm 0.50mm Ø 0.25mm Solder Mask Ø ~ 0.35mm LAND PATTERN RECOMMENDATION SS DG D = Drain Pad S = Source Pad G = Gate Pad SILICON 0.80mm MAX 0.27mm 0.50mm 1.10mm 0.50mm 0.30mm 0.30mmBump Ø 0.37mm 1.10mm 3 6/8/03 Rev0 44XXX MARK ON BACKSIDE OF DIE XXX = Date/Lot Traceability Code Bumps are Eutectic solder 63/37 Sn/Pb PRELIMINARY DATA SHEET TS4405P