TS3V340_10 TI | Alldatasheet
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/C0084/C0083/C0051/C0086/C0051/C0052/C0048 /C0081/C0085/C0065/C0068 /C0083/C0080/C0068/C0084 /C0072/C0073/C0071/C0072/C0262/C0066/C0065/C0078/C0068/C0087/C0073/C0068/C0084/C0072 /C0086/C0073/C0068/C0069/C0079 /C0083/C0087/C0073/C0084/C0067/C0072 /C0087/C0073/C0084/C0072 /C0076/C0079/C0087 /C0065/C0078/C0068 /C0070/C0076/C0065/C0084 /C0079/C0078/C0262/C0083/C0084/C0065/C0084/C0069 /C0082/C0069/C0083/C0073/C0083/C0084/C0065/C0078/C0067/C0069 SCDS172A - JULY 2004 − REVISED DECEMBER 2004 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Low Differential Gain and Phase (DG = 0.2%, DP = 0.1° Typ) /C0068Wide Bandwidth (BW = 500 MHz Typ) /C0068Low Crosstalk (XTALK = −80 dB Typ) /C0068Bidirectional Data Flow, With Near-Zero Propagation Delay /C0068Low and Flat ON-State Resistance on = 3 Ω Typ, ron(flat) = 1 Ω Typ) /C0068VCC Operating Range From 3 V to 3.6 V /C0068Ioff Supports Partial-Power-Down Mode Operation /C0068Data and Control Inputs Provide Undershoot Clamp Diode /C0068Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II /C0068ESD Performance Tested Per JESD 22 − 2000-V Human-Body Model (A114-B, Class II) − 1000-V Charged-Device Model (C101) /C0068Suitable for Both RGB and Composite Video Switching description/ordering information The TI video switch TS3V340 is a 4-bit 1-of-2 multiplexer/demultiplexer with a single switch-enable (EN ) input. When EN is low, the switch is enabled, and the D port is connected to the S port. When EN is high, the switch is disabled, and the high-impedance state exists between the D and S ports. The select (IN) input controls the data path of the multiplexer/demultiplexer. Low differential gain and phase makes this switch ideal for composite and RGB video applications. The device has a wide bandwidth and low crosstalk, making it suitable for high-frequency applications as well.
ORDERING INFORMATION
TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING QFN − RGY Tape and reel TS3V340RGYR TF340 SOIC − D Tube TS3V340D TS3V340SOIC − D Tape and reel TS3V340DR TS3V340 −40°C to 85°C SSOP (QSOP) − DBQ Tape and reel TS3V340DBQR TF340−40 C to 85C TSSOP − PW Tube TS3V340PW TF340TSSOP − PW Tape and reel TS3V340PWR TF340 TVSOP − DGV Tape and reel TS3V340DGVR TF340 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright 2004, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. D D, DBQ, DGV, OR PW PACKAGE (TOP VIEW) RGY PACKAGE (TOP VIEW) 11 6 EN S1D S2D D D S1C S2C S1A S2A D A S1B S2B D B IN V GND CC IN S1A S2A D A S1B S2B D B GND VCC EN S1D S2D D D S1C S2C D C C /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046
/C0084/C0083/C0051/C0086/C0051/C0052/C0048 /C0081/C0085/C0065/C0068 /C0083/C0080/C0068/C0084 /C0072/C0073/C0071/C0072/C0262/C0066/C0065/C0078/C0068/C0087/C0073/C0068/C0084/C0072 /C0086/C0073/C0068/C0069/C0079 /C0083/C0087/C0073/C0084/C0067/C0072 /C0087/C0073/C0084/C0072 /C0076/C0079/C0087 /C0065/C0078/C0068 /C0070/C0076/C0065/C0084 /C0079/C0078/C0262/C0083/C0084/C0065/C0084/C0069 /C0082/C0069/C0083/C0073/C0083/C0084/C0065/C0078/C0067/C0069 SCDS172A - JULY 2004 − REVISED DECEMBER 2004
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description/ordering information (continued) This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. This switch maintains isolation during power off. To ensure the high-impedance state during power up or power down, EN should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTION TABLE INPUTS INPUT/OUTPUT FUNCTIONEN IN INPUT/OUTPUT D FUNCTION L L S1 D port = S1 port L HS 2 D port = S2 port H X Z Disconnect PIN DESCRIPTION PIN NAME DESCRIPTION S1, S2 Analog video I/Os D Analog video I/Os IN Select input EN Switch-enable input
/C0084/C0083/C0051/C0086/C0051/C0052/C0048 /C0081/C0085/C0065/C0068 /C0083/C0080/C0068/C0084 /C0072/C0073/C0071/C0072/C0262/C0066/C0065/C0078/C0068/C0087/C0073/C0068/C0084/C0072 /C0086/C0073/C0068/C0069/C0079 /C0083/C0087/C0073/C0084/C0067/C0072 /C0087/C0073/C0084/C0072 /C0076/C0079/C0087 /C0065/C0078/C0068 /C0070/C0076/C0065/C0084 /C0079/C0078/C0262/C0083/C0084/C0065/C0084/C0069 /C0082/C0069/C0083/C0073/C0083/C0084/C0065/C0078/C0067/C0069 SCDS172A - JULY 2004 − REVISED DECEMBER 2004 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER DEFINITIONS PARAMETER DESCRIPTION R ON Resistance between the D and S ports, with the switch in the ON state IOZ Output leakage current measured at the D and S ports, with the switch in the OFF state IOS Short-circuit current measured at the I/O pins VIN Voltage at IN VEN Voltage at EN C IN Capacitance at the control (EN, IN) inputs C OFF Capacitance at the analog I/O port when the switch is OFF C ON Capacitance at the analog I/O port when the switch is ON VIH Minimum input voltage for logic high for the control (EN, IN) inputs VIL Maximum input voltage for logic low for the control (EN, IN) inputs VIK I/O and control (EN, IN) inputs diode clamp voltage VI Voltage applied to the D or S pins when D or S is the switch input VO Voltage applied to the D or S pins when D or S is the switch output IIH Input high leakage current of the control (EN, IN) inputs IIL Input low leakage current of the control (EN, IN) inputs II Current into the D or S pins when D or S is the switch input IO Current into the D or S pins when D or S is the switch output Ioff Output leakage current measured at the D or S ports, with VCC = 0 tpds Propagation delay measured between S1x and S2x under the specified conditions, measured from 50% of the digital input to 90% of the analog output BW Frequency response of the switch in the ON state, measured at −3 dB XTALK Unwanted signal coupled from channel to channel. Measured in −dB. XTALK = 20 log VO /VI. This is a nonadjacent crosstalk. O IRR OFF isolation is the resistance (measured in −dB) between the input and output with the switch OFF. D G Magnitude variation between analog input and output pins when the switch is ON and the DC offset of composite video signal varies at the analog input pin. In NTSC standard, the frequency of the video signal is 3.58 MHz, and DC offset is from 0 to 0.714 V. D P Phase variation between analog input and output pins when the switch is ON and the DC offset of composite video signal varies at the analog input pin. In NTSC standard, the frequency of the video signal is 3.58 MHz, and DC offset is from 0 to 0.714 V. ICC Static power-supply current ICCD Variation of ICC for a change in frequency in the control (EN, IN) inputs ∆ICC Increase in supply current for each control input that is at the specified voltage level, rather than VCC or GND
/C0084/C0083/C0051/C0086/C0051/C0052/C0048 /C0081/C0085/C0065/C0068 /C0083/C0080/C0068/C0084 /C0072/C0073/C0071/C0072/C0262/C0066/C0065/C0078/C0068/C0087/C0073/C0068/C0084/C0072 /C0086/C0073/C0068/C0069/C0079 /C0083/C0087/C0073/C0084/C0067/C0072 /C0087/C0073/C0084/C0072 /C0076/C0079/C0087 /C0065/C0078/C0068 /C0070/C0076/C0065/C0084 /C0079/C0078/C0262/C0083/C0084/C0065/C0084/C0069 /C0082/C0069/C0083/C0073/C0083/C0084/C0065/C0078/C0067/C0069 SCDS172A - JULY 2004 − REVISED DECEMBER 2004
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functional diagram (positive logic) D A S1A S2A S1B S2B S1C S2C S1D S2D EN IN D C D B D D Control Logic
/C0084/C0083/C0051/C0086/C0051/C0052/C0048 /C0081/C0085/C0065/C0068 /C0083/C0080/C0068/C0084 /C0072/C0073/C0071/C0072/C0262/C0066/C0065/C0078/C0068/C0087/C0073/C0068/C0084/C0072 /C0086/C0073/C0068/C0069/C0079 /C0083/C0087/C0073/C0084/C0067/C0072 /C0087/C0073/C0084/C0072 /C0076/C0079/C0087 /C0065/C0078/C0068 /C0070/C0076/C0065/C0084 /C0079/C0078/C0262/C0083/C0084/C0065/C0084/C0069 /C0082/C0069/C0083/C0073/C0083/C0084/C0065/C0078/C0067/C0069 SCDS172A - JULY 2004 − REVISED DECEMBER 2004 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to ground, unless otherwise specified. 2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. VI and VO are used to denote specific conditions for VI/O. 4. II and IO are used to denote specific conditions for II/O. 5. The package thermal impedance is calculated in accordance with JESD 51-7. 6. The package thermal impedance is calculated in accordance with JESD 51-5. recommended operating conditions (see Note 7) MIN MAX UNIT VCC Supply voltage 3 3.6 V VIH High-level control input voltage (EN, IN) 2 5.5 V VIL Low-level control input voltage (EN, IN) 0 0.8 V VO Analog I/O voltage 0 5.5 V TA Operating free-air temperature −40 85 °C NOTE 7: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
/C0084/C0083/C0051/C0086/C0051/C0052/C0048 /C0081/C0085/C0065/C0068 /C0083/C0080/C0068/C0084 /C0072/C0073/C0071/C0072/C0262/C0066/C0065/C0078/C0068/C0087/C0073/C0068/C0084/C0072 /C0086/C0073/C0068/C0069/C0079 /C0083/C0087/C0073/C0084/C0067/C0072 /C0087/C0073/C0084/C0072 /C0076/C0079/C0087 /C0065/C0078/C0068 /C0070/C0076/C0065/C0084 /C0079/C0078/C0262/C0083/C0084/C0065/C0084/C0069 /C0082/C0069/C0083/C0073/C0083/C0084/C0065/C0078/C0067/C0069 SCDS172A - JULY 2004 − REVISED DECEMBER 2004
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electrical characteristics over recommended operating free-air temperature range, VCC = 3.3 V /C0043 0.3 V (unless otherwise noted)† PARAMETER TEST CONDITIONS MIN TYP ‡ MAX UNIT VIK EN , IN VCC = 3 V, IIN = −18 mA −1.8 V IIH EN , IN VCC = 3.6 V, VIN and VEN = 5.5 V ±1 µA IIL EN , IN VCC = 3.6 V, VIN and VEN = GND ±1 µA IOZ § VCC = 3.6 V, VO = 0 to 5.5 V, VI = 0, Switch OFF ±1 µA IOS ¶ VCC = 3.6 V, VO = 0.5 VCC , VI = 0, Switch ON 50 mA Ioff VCC = 0, VO = 0 to 5.5 V, VI = 0 1 µA ICC VCC = 3.6 V, II/O = 0, Switch ON or OFF 0.7 1.5 mA ∆ICC EN , IN VCC = 3.6 V, One input at 3 V, Other inputs at VCC or GND 30 µA ICCD VCC = 3.6 V, D and S ports open, VEN = GND, VIN input switching 50% duty cycle 0.35 mA/ MHz C IN EN , IN VIN or VEN = 5.5 V, 3.3 V or 0, f = 1 MHz 2.5 3.5 pF C OFF D port VI = 5.5 V, 3.3 V, or 0,f = 1 MHz, Outputs open, Switch OFF 5.5 7 pFC OFF S port VI = 5.5 V, 3.3 V, or 0,f = 1 MHz, Outputs open, Switch OFF 3.5 5 pF C ON VI = 5.5 V, 3.3 V, or 0,f = 1 MHz, Outputs open, Switch ON 10.5 14 pF ron# VCC = 3 V VI = 1 V, IO = 13 mA 3 6 Ωron# VCC = 3 V VI = 2 V, IO = 26 mA 3 6 Ω ron(flat)|| VCC = 3.3 V, VI = 0 to VCC , IO = 26 mA 1 Ω † VI, VO , II, and IO refer to I/O pins. ‡ All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. § For I/O ports, the parameter IOZ includes the input leakage current. ¶ The IOS test is applicable to only one ON channel at a time. The duration of this test is less than 1 s. # Measured by the voltage drop between the D and S terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (D or S) terminals. ||ron(flat) is the difference of ron in a given channel at specified voltages. switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V /C0043 0.3 V, RL = 75 Ω, CL = 20 pF (unless otherwise noted) (see Figures 6 and 7) PARAMETER FROM (INPUT) TO (OUTPUT) MIN TYP MAX UNIT tpd(s) IN D 2 5 ns tON IN or EN S 4 7 ns tOFF IN or EN S 2 7 ns dynamic characteristics over recommended operating free-air temperature range, VCC = 3.3 V /C0043 0.3 V (unless otherwise noted) PARAMETER TEST CONDITIONS TYP ‡ UNIT D G /C0107R L = 150 Ω, f = 3.58 MHz, See Figure 7 0.2 % D P/C0107R L = 150 Ω, f = 3.58 MHz, See Figure 7 0.1 ° BW R L = 150 Ω, See Figure 8 500 MHz XTALK R L = 150 Ω, f = 10 MHz, R IN = 10 Ω, See Figure 9 −80 dB O IRR R L = 150 Ω, f = 10 MHz, See Figure 10 −60 dB ‡ All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. /C0107D G and DP are expressed in absolute magnitude.
8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Figure 3. OFF Isolation vs Frequency Figure 4. Crosstalk vs Frequency
Figure 5. Output Voltage/ON-State Resistance vs Input Voltage
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NOTES: A. C L includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. C. The outputs are measured one at a time, with one transition per measurement. Figure 6. Test Circuit and Voltage Waveforms
NOTES: A. C L includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. C. The outputs are measured one at a time, with one transition per measurement. Figure 7. Test Circuit and Voltage Waveforms
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Figure 8. Test Circuit for Differential Gain/Phase Measurement VEN = 0, and DA is the input, the output is measured at S1A.
Figure 9. Test Circuit for Frequency Response (BW ) D A is the input, the output is measured at S1A. All unused analog I/O ports are left open.
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† A 50-Ω termination resistor is needed for the network analyzer. Figure 10. Test Circuit for Crosstalk (XTALK ) are connected to GND through 10-Ω and 50-Ω pulldown resistors, respectively.
† A 50-Ω termination resistor is needed for the network analyzer. Figure 11. Test Circuit for OFF Isolation (OIRR) are connected to GND through 50-Ω pulldown resistors.
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TS3V340D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS3V340DBQR ACTIVE SSOP/ QSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TS3V340DBQRE4 ACTIVE SSOP/ QSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TS3V340DBQRG4 ACTIVE SSOP/ QSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TS3V340DE4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS3V340DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS3V340DGVR ACTIVE TVSOP DGV 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS3V340DGVRE4 ACTIVE TVSOP DGV 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS3V340DGVRG4 ACTIVE TVSOP DGV 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS3V340DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS3V340DRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS3V340DRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS3V340PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS3V340PWE4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS3V340PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS3V340PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS3V340PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS3V340PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS3V340RGYR ACTIVE VQFN RGY 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TS3V340RGYRG4 ACTIVE VQFN RGY 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. PACKAGE OPTION ADDENDUM www.ti.com 21-Dec-2009 Addendum-Page 1
TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 21-Dec-2009 Addendum-Page 2
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 30-Jul-2010 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TS3V340DGVR TVSOP DGV 16 2000 346.0 346.0 29.0 TS3V340DR SOIC D 16 2500 333.2 345.9 28.6 TS3V340PWR TSSOP PW 16 2000 346.0 346.0 29.0 TS3V340RGYR VQFN RGY 16 3000 346.0 346.0 29.0 PACKAGE MATERIALS INFORMATION www.ti.com 30-Jul-2010 Pack Materials-Page 2
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
3,70 3,50 4,90 5,10 20DIM PINS ** 4073251/E 08/00 1,20 MAX Seating Plane 0,05 0,15 0,25 0,50 0,75 0,23 0,13 11 2 24 13 4,30 4,50 0,16 NOM Gage Plane A 7,90 7,70 382416 4,90 5,103,70 3,50 A MAX A MIN 6,60 6,20 11,20 11,40 9,60 9,80 0,08 M0,070,40 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153
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