TS3USBCA410RSVT

TS3USBCA4_18 TI1 | Alldatasheet

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Technical content

SEL0,1, OEn TS5USBA224 TS3USBCA420 USB 2.0 L/R CC Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TS3USBCA4 SLLSF73A –FEBRUARY 2018–REVISED AUGUST 2018 TS3USBCA4USBType-CSBUMultiplexer

1 Features

1• USB Type-C™ 4:1 (TS3USBCA420) and 3:1 (TS3USBCA410) Multiplexer (MUX) for Analog Audio MIC/AGND, DisplayPort AUX, and Other Signals

• General Purpose MUX for 0 to 3.6 V Differential or Single-ended Signals
• Ultra Low RON of 60 mΩ for the AGND Connections for Low Crosstalk Performance
• Low Total Harmonic Distortion (THD)
• High Bandwidth Channels up to 500 MHz
• Supports Both Pin and I2C Configuration
• Supports Operation from Either 3.3-V ±10% Regulated Supply, or 2.4 to 5.5 V Battery
• Industrial Temperature Range: –40ºC to 85ºC TS3USBCA420I and TS3USBCA410I
• Commercial Temperature Range: 0ºC to 70ºC TS3USBCA420 and TS3USBCA410
• 1.8 mm x 2.6 mm, 16-pin, 0.4 mm Pitch QFN package

2 Applications

• Tablets
• Notebooks
• Desktops
• Gaming Consoles
• VR modules
• Smartphones
• Monitors

3 Description

The TS3USBCA4 is a passive 4:1 (TS3USBCA420) and 3:1 (TS3USBCA410) MUX supporting various types of differential or single-ended signals on the SBU1/SBU2 terminals of a USB Type-C connector to different interfaces. Those signals can be differential DisplayPort auxiliary (AUX), analog audio MIC and AGND, PCIe differential clock, or any other supported generic differential or single-ended signals. The audio path features ultra-low ON-state resistance (RON), low crosstalk and excellent total harmonic distortion (THD). The break-before-make feature prevents signal distortion during signal transfer from one channel to another. The high-speed paths support bandwidth as high as 500 MHz to provide adequate support for DisplayPort AUX, PCIe clock, and other similar signals. Together with low power consumption, these features make this device suitable for portable audio applications. The TS3USBCA4 wide supply range from 2.4 V to

5.5 V gives users the flexibility of powering it from a

single-cell battery, a 3.3-V regulator, or VBUS. It also provides options for both commercial and industrial temperature ranges. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TS3USBCA4 UQFN (16) 1.80 mm × 2.60 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Simplified Schematic

SLLSF73A –FEBRUARY 2018–REVISED AUGUST 2018 www.ti.com Product Folder Links: TS3USBCA4 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Table of Contents

12.1 Receiving Notification of Documentation Updates 36

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (February 2018) to Revision A Page

2MIC_GND1/Ln1 3MIC_GND2/Ln2 4OEn 5SEL1/SCL 6SEL0/SDA 7LnBp 8LnBn

9 GND

10 SBU2

11 SBU1

12 I2C_EN

14 FLIP

15 LnAn

16 LnAp

2MIC_GND1/Ln1 3MIC_GND2/Ln2 4OEn 5SEL1/SCL 6SEL0/SDA 7LnBp 8LnBn

13 LnCn

14 LnCp

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5 Pin Configuration and Functions

16-Pin (RSV) Top View 16-Pin (RSV) Top View Pin Functions PIN I/O DESCRIPTION NAME TS3USBCA420 TS3USBCA410 VCC 1 1 P Power supply. External decoupling capacitors are required close to this pin. MIC_GND1/Ln1 2 2 I/O, CMOS Analog audio MIC/AGND signal connection to audio codec. This pin can also function as a general purpose I/O. MIC_GND2/Ln2 3 3 I/O, CMOS Analog audio MIC/AGND signal connection to audio codec. This pin can also function as a general purpose I/O. OEn 4 4 2 Level I Output Enable: L: Normal Operation H: Standby Mode, I2C registers reset (Default) This pin has an internal weak pull-up. SEL1/SCL 5 5 2 Level I (Failsafe) In Pin Configuration Mode (I2C_EN = L), this pin functions as SEL1 which is used along with SEL0 pin to select switch configurations (Refer to Table 2). This pin has an internal weak pull-down. In I2C Mode (I2C_EN = M or H), this pin functions as SCL pin for I2C clock. When used for I2C clock, pull it up to VI2C with a resistor between 0.62 kΩ and 2.2 kΩ. SEL0/SDA 6 6 2 Level I/O (Failsafe) In Pin Configuration Mode (I2C_EN = L), this pin functions as SEL0 which is used along with SEL1 pin to select switch configurations (Refer to Table 2). This pin has an internal weak pull-down. In I2C Mode (I2C_EN = M or H), this pin functions as SDA pin for I2C data. When used for I2C data, pull it up to VI2C with a resistor between 0.62 kΩ and 2.2 kΩ. LnBp 7 7 I/O, CMOS This pin can be used in single-ended format or as a positive polarity differential pair partner to pin LnBn. It can be used for connection to any generic I/O signals such as for DisplayPort AUX, PCI Express clock, I2C, UART, and debug interfaces. LnBn 8 8 I/O, CMOS This pin can be used in single-ended format or as a negative polarity differential pair partner to pin LnBp. It can be used for connection to any generic I/O signals such as for DisplayPort AUX, PCI Express clock, I2C, UART, and debug interfaces. GND 9 9 G Primary ground connection for the TS3USBCA420. Must be connected to system ground. SBU2 10 10 I/O, CMOS (Failsafe) This pin should be DC coupled to the SBU2 pin of the Type-C receptacle. This pin has an internal nominally 1.6-MΩ pull-down resistor. SBU1 11 11 I/O, CMOS (Failsafe) This pin should be DC coupled to the SBU1 pin of the Type-C receptacle. This pin has an internal nominally 1.6-MΩ pull-down resistor. I2C_EN 12 12 3 Level I This pin enables I2C Mode and sets I2C mode addresses (Refer to Table 5) depending on the pin level defined in Table 1. L: Pin Configuration Mode M: I2C Mode enabled with I2C address ADDR0 H: I2C Mode enabled with I2C address ADDR1 This pin has an internal weak pull-up.

SLLSF73A –FEBRUARY 2018–REVISED AUGUST 2018 www.ti.com Product Folder Links: TS3USBCA4 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Pin Functions (continued) PIN I/O DESCRIPTION NAME TS3USBCA420 TS3USBCA410 LnCn 13 I/O, CMOS This pin can be used in single-ended format or as a negative polarity differential pair partner to pin LnCp. It can be used for connection to any generic I/O signals such as for DisplayPort AUX, PCI Express clock, I2C, UART, and debug interfaces. LnCp 14 I/O, CMOS This pin can be used in single-ended format or as a positive polarity differential pair partner to pin LnCn. It can be used for connection to any generic I/O signals such as for DisplayPort AUX, PCI Express clock, I2C, UART, and debug interfaces. NC 13 Not connected. FLIP 14 I/O, CMOS This pin flips the switches based on type-C plug orientation in pin configuration mode (I2C_EN=L). L: Normal orientation. H: Flipped orientation. This pin has an internal weak pull-down. LnAn 15 15 I/O, CMOS This pin can be used in single-ended format or as a negative polarity differential pair partner to pin LnAp. This pin is preferred for connection to DisplayPort AUX. It can also be used for connection to any generic I/O signals such as for PCI Express clock, I2C, UART, and debug interfaces. LnAp 16 16 I/O, CMOS This pin can be used in single-ended format or as a negative polarity differential pair partner to pin LnAn. This pin is preferred for connection to DisplayPort AUX. It can also be used for connection to any generic I/O signals such as for PCI Express clock, I2C, UART, and debug interfaces. (1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to the GND terminal.

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range unless otherwise noted.(1) MIN MAX UNIT VCC Supply Voltage Range (2) -0.5 6 V VIN_DIFF Differential Voltage at Differential Inputs -4 4 V VIN_SE Input Voltage at Differential Inputs (2) -0.5 6 V VIN_CMOS Input Voltage at CMOS Inputs other than SBU1/SBU2 Pins (2) -0.5 6 V VIN_SBU Input Voltage at SBU1/SBU2 Input-output Pins (2) -0.5 6 V TJ Junction Temperature 105 °C TSTG Storage temperature -65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

VHBM Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V VCDM Electrostatic discharge Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500 V

6.3 Recommended Operating Conditions

Over operating free-air temperature range unless otherwise noted. MIN NOM MAX UNIT TA Ambient temperature for TS3USBCA410 and TS3USBCA420 0 70 °C TA Ambient temperature for TS3USBCA410I and TS3USBCA420I -40 85 °C VCC Supply voltage 2.4 5.0 5.5 V VI2C Supply that external resistors on SDA and SCL are pulled up too 1.7 3.6 V VI/O_DIFF Differential Input-output Voltage 0 1.8 V VPSN Power supply noise 100 mV

www.ti.com SLLSF73A –FEBRUARY 2018–REVISED AUGUST 2018 Product Folder Links: TS3USBCA4 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated (1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. (4) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). (5) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). (6) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

6.4 Thermal Information

UNITRSV (R-PUQFN-N16)

16 PINS

RθJA Junction-to-ambient thermal resistance (1) 107.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance (2) 41.2 °C/W RθJB Junction-to-board thermal resistance (3) 43.6 °C/W ΨJT Junction-to-top characterization parameter (4) 1.1 °C/W ΨJB Junction-to-board characterization parameter (5) 43.6 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance (6) N/A °C/W 6.5 Electrical Characteristics (3 V ≤ VCC ≤ 3.6 V) All minimum/maximum specifications are at TA = -40/85°C, VCC = 3.0 V/3.6 V, unless otherwise noted. Typical specifications are at TA = 25°C, VCC = 3.3 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Power ICC Supply Current OEn = L, DEVICE_ENABLE = 1 45 70 μA IOFF_I2C Device Shutdown Current OEn = L, DEVICE_ENABLE = 0 17 30 μA IOFF_OEN Device Shutdown Current OEn = 3.6 V 0.05 3.5 μA Device Shutdown Current OEn = 1.4 V 4 12 μA SEL0, SEL1 VIH Input-high voltage 1.4 V VIL Input-low voltage 0.4 V IIH Input-high current VIN = VCC 2.5 µA IIL Input-low current VIN = 0 V 1 µA RPD Pull-down resistor 1.6 3.0 5.8 MΩ FLIP VIH Input-high voltage 1.4 V VIL Input-low voltage 0.4 V IIH Input-high current VIN = VCC 2.5 µA IIL Input-low current VIN = 0 V 1 µA RPD Pull-down resistor 1.6 3 5.8 MΩ OEn VIH Input-high voltage 1.4 V VIL Input-low voltage 0.4 V IIH Input-high current VIN=VCC 0.6 µA IIL Input-low current VIN=0 V 6 µA RPU Pull-up resistor 0.6 1.1 2.5 MΩ I2C_EN VIH Input-high voltage 0.85 VCC

SLLSF73A –FEBRUARY 2018–REVISED AUGUST 2018 www.ti.com Product Folder Links: TS3USBCA4 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Electrical Characteristics (3 V ≤ VCC ≤ 3.6 V) (continued) All minimum/maximum specifications are at TA = -40/85°C, VCC = 3.0 V/3.6 V, unless otherwise noted. Typical specifications are at TA = 25°C, VCC = 3.3 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIMH Upper bound of mid-level input voltage. Higher input may be intepreted as logic HIGH.

0.6 VCC

Lower bound of mid-level input voltage. Lower input may be intepreted as logic LOW.

0.4 VCC

VIL Input-low voltage 0.15 VCC IIH Input-high current 2.5 µA IIM Mid-level input current 1.2 µA IIL Input-low current 1 µA RPD Pull-down resistor 1.6 3.0 5.8 MΩ I2C Control Pins SCL, SDA VIH_I2C High-level input voltage I2C mode 1.3 VI2C V VIL_I2C Low-level input voltage I2C mode 0 0.5 V VOL_I2C Low-level output voltage I2C mode; IOL_I2C = 3 mA 0 0.4 V IOL_I2C Low-level output current I2C mode; VOL_I2C = 0.4 V 6 mA II_I2C Input current on SDA pin 0.1*VI2C < Input voltage < 3.6 V -5 5 µA CI_I2C Input capacitance 0.5 10 pF C(I2C_FM_ BUS) I2C bus capacitance for FM (400 kHz) 150 pF R(EXT_I2C _FM) External pull up resistors on both SDA and SCL for FM (400 kHz) C(I2C_FM_BUS) = 150 pF 620 1500 2200 Ω SBU1, SBU2 CSBU_HS Single-ended capacitance at 500MHz looking into SBU pin VIN = 0 V, outputs open, high-speed path enabled 4 11 13 pF CSBU_AU DIO Single-ended capacitance at 500MHz looking into SBU pin VIN = 0 V, outputs open, audio path enabled; TA = 25°C; VCC = 3.3 V 8 10 14 pF CSBU_OFF Single-ended capacitance at 500MHz looking into SBU pin VIN = 0 V, outputs open, OEn=H; TA = 25°C; VCC = 3.3 V 11 14 17 pF RPD Pull-down resistor 0.8 1.6 3.3 MΩ LnA, LnB, LnC: HIGH-SPEED PATH VI_HS Single-ended HS input voltage -0.3 3.6 V CHS_ON Single-ended capacitance at 500 MHz looking into HS pins VIN = 0 V, outputs open, high-speed path enabled 8.5 10.5 pF CHS_AUDI O Single-ended capacitance at 500 MHz looking into HS pins VIN = 0 V, outputs open, audio path enabled; TA = 25°C; VCC = 3.3 V 1.7 2 pF CHS_OFF Single-ended capacitance at 500 MHz looking into HS pins VIN = 0 V, outputs open, OEn=H; TA = 25°C; VCC = 3.3 V 1.7 2 pF RON_HS ON resistance VIN = 0 V, IO = -40 mA 4.9 7.1 Ω ΔRON_HS ON resistance match between pairs of the same channel VIN ≤ 0 V, IO = -40 mA 0.5 Ω RON_FLAT _HS ON resistance flatness (RON_HS(MAX) - RON_HS(MIN)) 0 V ≤ VIN ≤ 3.6 V, IO = -40 mA 1.35 Ω BWHS -3-dB bandwidth RL = 50 Ω, VIN = 0 V, MIC_GND1 pin open, MIC_GND1 pin open; TA = 25°C; VCC = 3.3 V 460 510 550 MHz RJHS Additive random jitter RL = 50 Ω, 10 kHz to 20 MHz offset, f = 100 MHz; TA = 25°C; VCC = 3.3 V 0.012 ps-RMS MIC_GND1, MIC_GND2: AUDIO PATH VI_MIC MIC input voltage -0.3 3.6 V

www.ti.com SLLSF73A –FEBRUARY 2018–REVISED AUGUST 2018 Product Folder Links: TS3USBCA4 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated Electrical Characteristics (3 V ≤ VCC ≤ 3.6 V) (continued) All minimum/maximum specifications are at TA = -40/85°C, VCC = 3.0 V/3.6 V, unless otherwise noted. Typical specifications are at TA = 25°C, VCC = 3.3 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CAUDIO_O N Single-ended capacitance at 500MHz looking into the MIC_GND pins VIN = 0 V, outputs open, audio path enabled; TA = 25°C; VCC = 3.3 V 9.5 12 pF CAUDIO_H S Single-ended capacitance at 500MHz looking into the MIC_GND pins VIN = 0 V, outputs open, high-speed path enabled; TA = 25°C; VCC = 3.3 V 11.5 16 pF CAUDIO_O FF Single-ended capacitance at 500MHz looking into the MIC_GND pins VIN = 0 V, outputs open, OEn=H; TA = 25°C; VCC = 3.3 V 12.5 14.5 pF RON_AUDI O ON resistance for AUDIO path VIN = 0 V, IO = -75 mA 50 80 mΩ BWAUDIO -3-dB bandwidth RL = 50 Ω, VIN = 0 V; TA = 25°C; VCC =

3.3 V 580 630 700 MHz

RL = 50 Ω, VIN = 3.3 V ± 200 mVPP, f =

217 Hz -105 -100 dB

RL = 50 Ω, VIN = 3.3 V ± 200 mVPP, f = 1 kHz -96 -92 dB PSR20K RL = 50 Ω, VIN = 3.3 V ± 200 mVPP, f = 20 kHz -85 -81 dB THD200_ MIC Total harmonic distortion RS=600Ω, RL=600Ω, VIN=1.8V±200mVPP, f=20Hz~20kHz; TA = 25°C; VCC = 3.3 V 0.006 % THD500_ MIC Total harmonic distortion RS=600Ω, RL=600Ω, VIN=1.8V±500mVPP, f=20Hz~20kHz; TA = 25°C; VCC = 3.3 V 0.003 % XTALK_MI CGND Crosstalk between MIC and AGND VIN = 200 mVPP, f = 20 Hz – 20 kHz, RL = 50 Ω; TA = 25°C; -110 -90 dB ISOOFF_ MICGND OFF isolation VIN = 200 mVPP, f = 20 Hz – 20 kHz, RL = 50 Ω; TA = 25°C; -73 -67 dB 6.6 Electrical Characteristics (2.4 V ≤ VCC ≤ 5.5 V) All minimum/maximum specifications are at TA = -40/85°C, VCC = 2.4 V/5.5 V, unless otherwise noted. Typical specifications are at TA = 25°C, VCC = 3.3 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Power ICC Supply Current OEn = L, DEVICE_ENABLE = 1 45 75 μA IOFF_I2C Device Shutdown Current OEn = L, DEVICE_ENABLE = 0 17 40 μA IOFF_OEN Device Shutdown Current OEn = 3.6 V 0.05 5.5 μA Device Shutdown Current OEn = 1.4 V 4 80 μA SEL0, SEL1 VIH Input-high voltage 1.4 V VIL Input-low voltage 0.4 V IIH Input-high current VIN = VCC 3.5 µA IIL Input-low current VIN = 0 V 1 µA RPD Pull-down resistor 1.6 3.0 5.8 MΩ FLIP VIH Input-high voltage 1.4 V VIL Input-low voltage 0.4 V IIH Input-high current VIN = VCC 3.5 µA IIL Input-low current VIN = 0 V 1 µA RPD Pull-down resistor 1.6 3.0 5.8 MΩ OEn VIH Input-high voltage 1.5 V

SLLSF73A –FEBRUARY 2018–REVISED AUGUST 2018 www.ti.com Product Folder Links: TS3USBCA4 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Electrical Characteristics (2.4 V ≤ VCC ≤ 5.5 V) (continued) All minimum/maximum specifications are at TA = -40/85°C, VCC = 2.4 V/5.5 V, unless otherwise noted. Typical specifications are at TA = 25°C, VCC = 3.3 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIL Input-low voltage 0.4 V IIH Input-high current VIN=VCC 1 µA IIL Input-low current VIN=0 V 8 µA RPU Pull-up resistor 0.6 1.1 2.5 MΩ I2C_EN VIH Input-high voltage 0.9 VCC VIMH Upper bound of mid-level input voltage. Higher input may be intepreted as logic HIGH.

0.58 VCC

Lower bound of mid-level input voltage. Lower input may be intepreted as logic LOW.

0.42 VCC

VIL Input-low voltage 0.14 VCC IIH Input-high current 3.5 µA IIM Mid-level input current 1.6 µA IIL Input-low current 1 µA RPD Pull-down resistor 1.6 3.0 5.8 MΩ I2C Control Pins SCL, SDA VIH_I2C High-level input voltage I2C mode 1.3 VI2C V VIL_I2C Low-level input voltage I2C mode 0 0.5 V VOL_I2C Low-level output voltage I2C mode; IOL_I2C = 3 mA 0 0.4 V IOL_I2C Low-level output current I2C mode; VOL_I2C = 0.4 V 4 mA II_I2C Input current on SDA pin 0.1*VI2C < Input voltage < 3.6 V -5 5 µA CI_I2C Input capacitance 0.5 10 pF C(I2C_FM_ BUS) I2C bus capacitance for FM (400 kHz) 150 pF R(EXT_I2C _FM) External pull up resistors on both SDA and SCL for FM (400 kHz) C(I2C_FM_BUS) = 150 pF 620 1500 2200 Ω SBU1, SBU2 CSBU_HS Single-ended capacitance at 500MHz looking into SBU pin VIN = 0 V, outputs open, high-speed path enabled 4 11 13 pF CSBU_AU DIO Single-ended capacitance at 500MHz looking into SBU pin VIN = 0 V, outputs open, audio path enabled; TA = 25°C; VCC = 3.3 V 8 10 14 pF CSBU_OFF Single-ended capacitance at 500MHz looking into SBU pin VIN = 0 V, outputs open, OEn=H; TA = 25°C; VCC = 3.3 V 11 14 17 pF RPD Pull-down resistor 0.8 1.6 3.3 MΩ LnA, LnB, LnC: HIGH-SPEED PATH VI_HS Single-ended HS input voltage -0.3 3.6 V CHS_ON Single-ended capacitance at 500 MHz looking into HS pins VIN = 0 V, outputs open, high-speed path enabled 8.5 10.5 pF CHS_AUDI O Single-ended capacitance at 500 MHz looking into HS pins VIN = 0 V, outputs open, audio path enabled; TA = 25°C; VCC = 3.3 V 1.7 2 pF CHS_OFF Single-ended capacitance at 500 MHz looking into HS pins VIN = 0 V, outputs open, OEn=H; TA = 25°C; VCC = 3.3 V 1.7 2 pF RON_HS ON resistance VIN = 0 V, IO = -40 mA 4.9 7.5 Ω ΔRON_HS ON resistance match between pairs of the same channel VIN ≤ 0 V, IO = -40 mA 0.65 Ω RON_FLAT _HS ON resistance flatness (RON_HS(MAX) - RON_HS(MIN)) 0 V ≤ VIN ≤ 3.6 V, IO = -40 mA 1.35 Ω

www.ti.com SLLSF73A –FEBRUARY 2018–REVISED AUGUST 2018 Product Folder Links: TS3USBCA4 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated Electrical Characteristics (2.4 V ≤ VCC ≤ 5.5 V) (continued) All minimum/maximum specifications are at TA = -40/85°C, VCC = 2.4 V/5.5 V, unless otherwise noted. Typical specifications are at TA = 25°C, VCC = 3.3 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BWHS -3-dB bandwidth RL = 50 Ω, VIN = 0 V; TA = 25°C; VCC =

3.3 V 450 510 670 MHz

RJHS Additive random jitter RL = 50 Ω, 10 kHz to 20 MHz offset, f = 100 MHz; TA = 25°C; VCC = 3.3 V 0.012 ps-RMS MIC_GND1, MIC_GND2: AUDIO PATH VI_MIC MIC input voltage -0.3 3.6 V CAUDIO_O N Single-ended capacitance at 500MHz looking into the MIC_GND pins VIN = 0 V, outputs open, audio path enabled; TA = 25°C; VCC = 3.3 V 9.5 12 pF CAUDIO_H S Single-ended capacitance at 500MHz looking into the MIC_GND pins VIN = 0 V, outputs open, high-speed path enabled; TA = 25°C; VCC = 3.3 V 11.5 16 pF CAUDIO_O FF Single-ended capacitance at 500MHz looking into the MIC_GND pins VIN = 0 V, outputs open, OEn=H; TA = 25°C; VCC = 3.3 V 12.5 14.5 pF RON_AUDI O ON resistance for AUDIO path VIN = 0 V, IO = -75 mA 50 80 mΩ BWAUDIO -3-dB bandwidth RL = 50 Ω, VIN = 0 V; TA = 25°C; VCC =

3.3 V 580 630 720 MHz

RL = 50 Ω, VIN = 3.3 V ± 200 mVPP, f =

217 Hz -105 -96 dB

RL = 50 Ω, VIN = 3.3 V ± 200 mVPP, f = 1 kHz -96 -90 dB PSR20K RL = 50 Ω, VIN = 3.3 V ± 200 mVPP, f = 20 kHz -85 -81 dB THD200_ MIC Total harmonic distortion RS=600Ω, RL=600Ω, VIN=1.8V±200mVPP, f=20HZ~20kHz; TA = 25°C; VCC = 3.3 V 0.006 % THD500_ MIC Total harmonic distortion RS=600Ω, RL=600Ω, VIN=1.8V±500mVPP, f=20Hz~20kHz; TA = 25°C; VCC = 3.3 V 0.003 % XTALK_MI CGND Crosstalk between MIC and AGND VIN = 200 mVPP, f = 20 Hz – 20 kHz, RL = 50 Ω; TA = 25°C; -110 -90 dB ISOOFF_ MICGND OFF isolation VIN = 200 mVPP, f = 20 Hz – 20 kHz, RL = 50 Ω; TA = 25°C; -73 -67 dB 6.7 Switching Characteristics (2.4 V ≤ VCC ≤ 5.5 V) All minimum/maximum specifications are at TA = -40/85°C, VCC = 2.4 V/5.5 V, unless otherwise noted. Typical specifications are at TA = 25°C, VCC = 3.3 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I2C fSCL I2C clock frequency 400 kHz tBUF Bus free time between START and STOP conditions 1.3 µs tHDSTA Hold time after repeated START condition. After this period, the first clock pulse is generated 0.6 µs tLOW Low period of the I2C clock 1.3 µs tHIGH High period of the I2C clock 0.6 µs tSUSTA Setup time for a repeated START condition 0.6 µs tHDDAT Data hold time 0 µs tSUDAT Data setup time 150 ns tR Rise time of both SDA and SCL signals 300 ns

6.10 Timing Diagrams

Figure 1. Power-Up Timing Figure 2. I2C Timing Diagram Definitions

6.11 Typical Characteristics

Figure 3. S3PX Total Harmonic Distortion Figure 4. Off Isolation Figure 5. Power Supply Rejection Figure 6. Crosstalk

7 Parameter Measurement Information

Figure 7. ON-State Resistance for the Analog Audio GND (RON_AGND)

Figure 8. ON-State Resistance for High-Speed Data Paths (RON_HS)

Figure 9. ON-State and OFF-State Output Capacitance for High-Speed Data Paths (CON_HS, COFF_HS)

3.3 V ± 200 mVpp

Figure 10. Power Supply Rejection (PSR)

Figure 11. Total Harmonic Distortion (THD)

Figure 12. Crosstalk Between MIC and AGND (XTALKMICGND)

Figure 13. OFF Isolation (ISOOFF_MICGND)

Figure 14. Turn-ON time (tON) and Turn-OFF time (tOFF) for MIC and AGND

Figure 15. Turn-ON time (tON) and Turn-OFF time (tOFF) for High-Speed Data Paths

Figure 16. Break-Before-Make Time (tBBM)

8 Detailed Description

8.1 Overview

supported generic differential or single-ended signals. make this device suitable for portable audio applications. VBUS. The TS3USBCA4 provides options for both commercial and industrial temperature ranges.

8.2 Functional Block Diagram

Figure 17. Functional Block Diagram

8.3 Feature Description

8.3.1 Analog Audio Path

The TS3USBCA4 supports analog audio switching between the SBU1 and SBU2 pins on one side of the switch. ON resistance and low total harmonic distortion for better audio performance. support flipping MIC and AGND. The audio codec should provide this function.

8.3.2 High-Speed Paths

though either the I2C interface or pin control in TS3USBCA410. to avoid address conflict. The settings for the three levels are shown in Table 1. Table 1. 3-Level Control Pin Settings

8.4 Device Functional Modes

Table 1. Table 2 and Table 3 show the configuration truth table for TS3USBCA420 and TS3USBCA410, respectively. Note in TS3USBCA420 the flipping capability is available only in I2C-configuration mode. Table 2. TS3USBCA420 Switch Configuration Truth Table(1) Table 3. TS3USBCA410 Switch Configuration Truth Table(1)

000 LLL

001 LLH

010 LHL

011 LHH

100 HLL

101 HLH

110 HHL

111 HHH

the DEVICE_ENABLE register. Table 4 shows the details. Table 4. TS3USBCA4 Enable/Disable Truth Table Device is shut down with IOFF_I2C. On-chip bandgap and IO buffers are still on. Device is under reset with IOFF_OEN. On-chip bandgap and IO buffers are off.

8.5 Programming

Table 5. TS3USBCA4 I2C Slave Address

1. The master initiates a write operation by generating a start condition (S), followed by the TS3USBCA4 7-bit
2. The TS3USBCA4 acknowledges the address cycle.
3. The master presents the sub-address (I2C register within TS3USBCA4) to be written, consisting of one byte
4. The TS3USBCA4 acknowledges the sub-address cycle.
5. The master presents the first byte of data to be written to the I2C register.
6. The TS3USBCA4 acknowledges the byte transfer.
7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing

with an acknowledge from the TS3USBCA4.

1. The master terminates the write operation by generating a stop condition (P).
2. The master initiates a read operation by generating a start condition (S), followed by the TS3USBCA4 7-bit
3. The TS3USBCA4 acknowledges the address cycle.
4. The TS3USBCA4 transmit the contents of the memory registers MSB-first starting at register 00h or last read

sub-address specified in the write.

1. The TS3USBCA4 shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master

after each byte transfer; the I2C master acknowledges reception of each data byte transfer.

1. If an ACK is received, the TS3USBCA4 transmits the next byte of data.
2. The master terminates the read operation by generating a stop condition (P).
3. The master initiates a write operation by generating a start condition (S), followed by the TS3USBCA4 7-bit

address and a zero-value “W/R”bit to indicate a write cycle.

1. The TS3USBCA4 acknowledges the address cycle.
2. The master presents the sub-address (I2C register within TS3USBCA4) to be written, consisting of one byte
3. The TS3USBCA4 acknowledges the sub-address cycle.
4. The master terminates the write operation by generating a stop condition (P).

8.6 Register Maps

8.6.1 TS3USBCA4 Registers

in Table 6 should be considered as reserved locations and the register contents should not be modified. Table 6. TS3USBCA4 Registers access types in this section. Table 7. TS3USBCA4 Access Type Codes

8.6.1.1 Revision_ID Register (Offset = 9h) [reset = 0h]

Revision_ID is shown in Figure 18 and described in Table 8. Figure 18. Revision_ID Register Table 8. Revision_ID Register Field Descriptions 3-0 REVISION_ID R 0h Silicon revision.

8.6.1.2 General_1 Register (Offset = Ah) [reset = 0h]

General_1 is shown in Figure 19 and described in Table 9. Figure 19. General_1 Register

Table 9. General_1 Register Field Descriptions 1 DEVICE_ENABLE R/W 0h Controls the switch enable. 0 FLIPSEL R/W 0h Controls the USB-C orientation.

8.6.1.3 General_2 Register (Offset = Bh) [reset = 0h]

General_2 is shown in Figure 20 and described in Table 10. Figure 20. General_2 Register Table 10. General_2 Register Field Descriptions 1-0 SWSEL R/W 0h This field along with FLIPSEL controls the SBU switch connections.

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

cross-switch capability for different USB type-C plug orientations.

9.2 Typical Application

slave address is set to ADDR1. VIO_uP is the supply for the micro-processor IOs. Figure 21. Application of TS3USBCA420 in I2C-Configuration Mode supply for the micro-processor IOs.

Figure 24. Application of TS3USBCA410 in Pin-Configuration Mode

9.2.1 Design Requirements

9.2.2 Detailed Design Procedure

processor and TS3USBCA4, and insert level translators when necessary. effect of the on-chip pull-down resistor to ensure a satisfactory voltage margin for VIM of the I2C_EN pin. low RON of the audio channel, big parasitic capacitance exists between the audio output port and the SBU port.

9.2.3 Application Curves

Figure 25. Max Current vs Contact Resistance

10 Power Supply Recommendations

should follow the minimum and maximum VCC rise and fall times specified in the electrical specifications section.

11 Layout

11.1 Layout Guidelines

• The VCC pin must have de-coupling capacitors placed as closely to the device as possible. Typically recommended capacitors are a 0.1-µF and a 1-µF capacitor.
• The total resistance from SBU1 and SBU2 pins of the type-C connector to the MIC_GND1 and MIC_GND2 pins of the audio codec should be kept low to avoid degrading the crosstalk performance.
• Route the I2C and digital signals away from the audio signals to prevent coupling onto the audio lines.

11.2 Layout Example

Figure 26 shows a layout example of TS3USBCA420. Figure 26. Layout Example

SLLSF73A –FEBRUARY 2018–REVISED AUGUST 2018 www.ti.com Product Folder Links: TS3USBCA4 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.3 Trademarks

E2E is a trademark of Texas Instruments. USB Type-C is a trademark of USB Implementers Forum.

12.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.5 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2018 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TS3USBCA410IRSVR UQFN RSV 16 3000 189.0 185.0 36.0 TS3USBCA410IRSVT UQFN RSV 16 250 189.0 185.0 36.0 TS3USBCA410RSVR UQFN RSV 16 3000 189.0 185.0 36.0 TS3USBCA410RSVT UQFN RSV 16 250 189.0 185.0 36.0 TS3USBCA420IRSVR UQFN RSV 16 3000 189.0 185.0 36.0 TS3USBCA420IRSVT UQFN RSV 16 250 189.0 185.0 36.0 TS3USBCA420RSVR UQFN RSV 16 3000 189.0 185.0 36.0 TS3USBCA420RSVT UQFN RSV 16 250 189.0 185.0 36.0 PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2018 Pack Materials-Page 2

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