TS3L301_07 TI | Alldatasheet
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(TOP VIEW) VDD GND GND VDD GND GND GND VDD GND NC GND GND VDD GND GND SEL 0B1 1B1 GND 1B2 GND 3B1 GND 3B2 GND V DD 4B1 5B1 GND 5B2 GND 7B1 GND 7B2 NC − No internal connection DESCRIPTION/ORDERING INFORMATION TS3L301 16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH WITH LOW AND FLAT ON-STATE RESISTANCE SCDS178C NOVEMBER 2004 REVISED APRIL 2006 Wide Bandwidth (BW 900 MHz Typ) Low Crosstalk TALK dB Typ) Low Bit-to-Bit Skew sk(o) 0.2 ns Max] Low and Flat ON-State Resistance on Ω Typ, r on(flat) 0.7 Ω Typ) Low Input/Output Capacitance ON pF Typ) Rail-to-Rail Switching on Data I/O Ports to V DD Operating Range From V to 3.6 V I off Supports Partial Power-Down-Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 2000-V Human-Body Model (A114-B, Class II) 1000-V Charged-Device Model (C101) Suitable for 10-/100-/1000-Mbit Ethernet Signaling 10/100/1000 Base-T Signal Switching Differential (LVDS, LVPECL) Signal Switching Digital Video Signal Routing Notebook Docking Signal Routing Hub and Router Signal Switching The TS3L301 is a 16-bit to 8-bit multiplexer/demultiplexer local area network (LAN) switch with a single select (SEL) input. The SEL input controls the data path of the multiplexer/demultiplexer. The device provides a low and flat ON-state resistance on and an excellent ON-state resistance match. Low input/output capacitance, high-bandwidth, low skew, and low crosstalk among channels make this device suitable for various LAN applications, such as 10/100/1000 Base-T. ORDERING INFORMATION T A PACKAGE (1) ORDERABLE PART NUMBER TOP-SIDE MARKING TSSOP DGG Tape and reel TS3L301DGGR TS3L301 C to C TVSOP DGV Tape and reel TS3L301DGVR TK301 (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. PRODUCTION DATA information is current as of publication date. Copyright 2004 2006, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
www.ti.com A0 0B1 0B2 SEL 2 48 1B2 A1 1B1 4 47 A2 2B1 2B2 8 42 3B2 A3 3B1 10 41 A4 4B1 4B2 15 35 5B2 A5 5B1 17 34 A6 6B1 6B2 21 29 7B2 A7 7B1 23 28 TS3L301 16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH WITH LOW AND FLAT ON-STATE RESISTANCE SCDS178C NOVEMBER 2004 REVISED APRIL 2006 FUNCTION TABLE INPUT INPUT/OUTPUT FUNCTION SEL An L nB A n nB H nB A n nB PIN
DESCRIPTION
A n Data I/Os nB m Data I/Os SEL Select input LOGIC DIAGRAM (POSITIVE LOGIC) Submit Documentation Feedback
www.ti.com Absolute Maximum Ratings (1) Recommended Operating Conditions (1) TS3L301 16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH WITH LOW AND FLAT ON-STATE RESISTANCE SCDS178C NOVEMBER 2004 REVISED APRIL 2006 over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT V DD Supply voltage range 0.5 4.6 V V IN Control input voltage range (2) (3) 0.5 V V I/O Switch I/O voltage range (2) (3) (4) 0.5 V I IK Control input clamp current V IN mA I I/OK I/O port clamp current V I/O mA I I/O ON-state switch current (5) 128 mA Continuous current through V DD or GND 100 mA DGG package θ JA Package thermal impedance (6) C/W DGV package T stg Storage temperature range 150 C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are with respect to ground, unless otherwise specified. (3) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. (4) V I and V O are used to denote specific conditions for V I/O (5) I I and I O are used to denote specific conditions for I I/O (6) The package thermal impedance is calculated in accordance with JESD 51-7. MIN MAX UNIT V DD Supply voltage 3.6 V V IH High-level control input voltage (SEL) 5.5 V V IL Low-level control input voltage (SEL) 0.8 V V I/O Input/output voltage 5.5 V T A Operating free-air temperature C (1) All unused control inputs of the device must be held at V DD or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs literature number SCBA004. Submit Documentation Feedback
www.ti.com Electrical Characteristics Electrical Characteristics TS3L301 16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH WITH LOW AND FLAT ON-STATE RESISTANCE SCDS178C NOVEMBER 2004 REVISED APRIL 2006 for 1000 Base-T Ethernet switching over recommended operating free-air temperature range, V DD 3.3 V 0.3 V (unless otherwise noted) PARAMETER TEST CONDITIONS (1) MIN TYP (2) MAX UNIT V IK SEL V DD 3.6 I IN mA 0.7 1.2 V I IH SEL V DD 3.6 V IN V DD µ A I IL SEL V DD 3.6 V IN GND µ A I off V DD V O to 3.6 V I µ A I DD V DD 3.6 I I/O Switch ON or OFF 250 600 µ A C IN SEL f MHz, V IN 2.5 pF C OFF B port V I f MHz, Outputs open, Switch OFF 3.5 pF C ON V I f MHz, Outputs open, Switch ON 10.9 pF r on V DD 1.5 V V I V DD I O mA Ω r on(flat) (3) V DD V I 1.5 V and V DD I O mA 0.7 Ω Δ r on (4) V DD 1.5 V V I V DD I O mA 0.2 1.2 Ω (1) V I V O I I and I O refer to I/O pins. V IN refers to the control inputs. (2) All typical values are at V DD 3.3 V (unless otherwise noted), T A (3) r on(flat) is the difference of r on in a given channel at specified voltages. (4) Δ r on is the difference of r on from center A ports to any other port. for Base-T Ethernet switching over recommended operating free-air temperature range, V DD 3.3 V 0.3 V (unless otherwise noted) PARAMETER TEST CONDITIONS (1) MIN TYP (2) MAX UNIT V IK SEL V DD 3.6 I IN mA 0.7 1.2 V I IH SEL V DD 3.6 V IN V DD µ A I IL SEL V DD 3.6 V IN GND µ A I off V DD V O to 3.6 V I µ A I DD V DD 3.6 I I/O Switch ON or OFF 250 600 µ A C IN SEL f MHz, V IN 2.5 pF C OFF B port V I f MHz, Outputs open, Switch OFF 3.5 pF C ON V I f MHz, Outputs open, Switch ON 10.9 pF r on V DD 1.25 V V I V DD I O mA to mA Ω r on(flat) (3) V DD V I 1.25 V and V DD I O mA to mA 0.7 Ω Δ r on (4) V DD 1.25 V V I V DD I O mA to mA 0.2 1.2 Ω (1) V I V O I I and I O refer to I/O pins. V IN refers to the control inputs. (2) All typical values are at V DD 3.3 V (unless otherwise noted), T A (3) r on(flat) is the difference of r on in a given channel at specified voltages. (4) Δ r on is the difference of r on from center A ports to any other port. Submit Documentation Feedback
www.ti.com Switching Characteristics Dynamic Characteristics TS3L301 16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH WITH LOW AND FLAT ON-STATE RESISTANCE SCDS178C NOVEMBER 2004 REVISED APRIL 2006 over recommended operating free-air temperature range, V DD 3.3 V 0.3 R L 200 Ω C L pF (unless otherwise noted) (see Figures and FROM TO PARAMETER MIN TYP (1) MAX UNIT (INPUT) (OUTPUT) t pd (2) A or B B or A 0.25 ns t PZH t PZL SEL A or B 1.5 11.5 ns t PHZ t PLZ SEL A or B 8.5 ns t sk(o) (3) A or B B or A 0.1 0.2 ns t sk(p) (4) 0.1 0.2 ns (1) All typical values are at V DD 3.3 V (unless otherwise noted), T A (2) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance when driven by an ideal voltage source (zero output impedance). (3) Output skew between center port to A to any other port (4) Skew between opposite transitions of the same output in a given device PHL t PLH over recommended operating free-air temperature range, V DD 3.3 V 0.3 V (unless otherwise noted) PARAMETER TEST CONDITIONS TYP (1) UNIT X TALK R L 100 Ω f 250 MHz, See Figure dB O IRR R L 100 Ω f 250 MHz, See Figure dB BW R L 100 Ω See Figure 900 MHz (1) All typical values are at V DD 3.3 V (unless otherwise noted), T A Submit Documentation Feedback
www.ti.com OPERATING CHARACTERISTICS Gain − dB Frequency − MHz 1 10 10,000100 1,000 Gain at 900 MHz, −3 dB −120 −100 −80 −60 −40 −20 Off-Isolation − dB Frequency − MHz 1 10 10,000100 1,000 OFF Isolation at 250 MHz, −39 dB TS3L301 16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH WITH LOW AND FLAT ON-STATE RESISTANCE SCDS178C NOVEMBER 2004 REVISED APRIL 2006 Figure Gain vs Frequency Figure OFF Isolation vs Frequency Submit Documentation Feedback
www.ti.com OPERATING CHARACTERISTICS (continued) −120 −100 −80 −60 −40 −20 Crosstalk − dB Frequency − MHz 1 10 10,000100 1,000 Crosstalk at 250 MHz, −41 dB TS3L301 16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH WITH LOW AND FLAT ON-STATE RESISTANCE SCDS178C NOVEMBER 2004 REVISED APRIL 2006 Figure Crosstalk vs Frequency Submit Documentation Feedback
www.ti.com PARAMETER MEASUREMENT INFORMATION tPZH tPZL CL (see Note A) TEST CIRCUIT 2 × VDD Open GND RL RL NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ /char????????10 MHz, ZO = 50 Ω , tr ≤/char????????2.5 ns, tf ≤/char????????2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. 50 Ω VG1 VDD DUT 50 Ω VIN 50 Ω VG2 50 Ω VI TEST RLS1 VΔCLVDD VI tPLZ/tPZL 3.3 V ±/char????????0.3 V 2 × VDD 200 Ω GND 10 pF 0.3 V Input Generator Input Generator VO tPHZ/tPZH 3.3 V ±/char????????0.3 V GND 200 Ω VDD 10 pF 0.3 V VOH −0.3 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VDD/2 VDD/2 Output Control (VIN) 1.25 V 2.5 V VOH VOL +0.3 V VOH VOL 0 V 1.25 V tPLZ tPHZ Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 VDD (see Note B) VOL TS3L301 16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH WITH LOW AND FLAT ON-STATE RESISTANCE SCDS178C NOVEMBER 2004 REVISED APRIL 2006 (Enable and Disable Times) Figure Test Circuit and Voltage Waveforms Submit Documentation Feedback
www.ti.com PARAMETER MEASUREMENT INFORMATION CL (see Note A) TEST CIRCUIT 2 × VDD Open GND RL RL VOH VOL VOLTAGE WAVEFORMS OUTPUT SKEW [tsk(o)] Data Out at YB1 or YB2 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ /char????????10 MHz, ZO = 50 Ω , tr ≤/char????????2.5 ns, tf ≤/char????????2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. 50 Ω VG1 VDD DUT 50 Ω VIN 50 Ω VG2 50 Ω VI TEST RLS1 CL VDD VI tsk(p) tsk(o) Open Open 200 Ω 200 Ω VDD or GND VDD or GND 10 pF 10 pF Input Generator Input Generator VO (VOH + VOL)/2 VOH VOL Data Out at XB1 or XB2 (VOH + VOL)/2 3.5 V 1.5 V Data In at Ax or Ay 2.5 V tPLHx tPHLx tsk(o) tsk(o) tPLHy tPHLy tsk(o) = tPLHy − tPLHx or tPHLy − tPHLx VOH VOL VOLTAGE WAVEFORMS PULSE SKEW [tsk(p)] Output (VOH + VOL)/2 Input 2.5 V tPLH tPHL tsk(p) = tPLH − tPLH 3.5 V 1.5 V TS3L301 16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH WITH LOW AND FLAT ON-STATE RESISTANCE SCDS178C NOVEMBER 2004 REVISED APRIL 2006 (Skew) Figure Test Circuit and Voltage Waveforms Submit Documentation Feedback
www.ti.com PARAMETER MEASUREMENT INFORMATION Network Analyzer (HP8753ES) EXT TRIGGER BIAS P1 P2 DUT SEL 0B1 VSEL VDD VBIAS CL = 10 pF (see Note A) HP8753ES Setup TS3L301 16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH WITH LOW AND FLAT ON-STATE RESISTANCE SCDS178C NOVEMBER 2004 REVISED APRIL 2006 C L includes probe and jig capacitance. Figure Test Circuit for Frequency Response (BW) Frequency response is measured at the output of the ON channel. For example, when V SEL and A is the input, the output is measured at All unused analog I/O ports are left open. Average RBW kHz V BIAS 0.35 V ST s dBM Submit Documentation Feedback
www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) Network Analyzer (HP8753ES) RL = 100 Ω EXT TRIGGER BIAS P1 P2 DUT SEL 0B1 VSEL VDD VBIAS 1B2 1B1 RL = 100 Ω 2B1 3B1 0B2 3B2 2B2 HP8753ES Setup TS3L301 16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH WITH LOW AND FLAT ON-STATE RESISTANCE SCDS178C NOVEMBER 2004 REVISED APRIL 2006 C L includes probe and jig capacitance. A 50- Ω termination resistor is needed to match the loading of the network analyzer. Figure Test Circuit for Crosstalk TALK Crosstalk is measured at the output of the nonadjacent ON channel. For example, when V SEL and A is the input, the output is measured at A All unused analog input (A) ports are connected to GND, and output (B) ports are left open. Average RBW kHz V BIAS 0.35 V ST s dBM Submit Documentation Feedback
www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) Network Analyzer (HP8753ES) RL = 100 Ω EXT TRIGGER BIAS P1 P2 DUT SEL 0B1 VSEL VDD VBIAS 0B2 A1 1B1 1B2 HP8753ES Setup TS3L301 16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH WITH LOW AND FLAT ON-STATE RESISTANCE SCDS178C NOVEMBER 2004 REVISED APRIL 2006 C L includes probe and jig capacitance. A 50- Ω termination resistor is needed to match the loading of the network analyzer. Figure Test Circuit for Off Isolation IRR OFF isolation is measured at the output of the OFF channel. For example, when V SEL GND and A is the input, the output is measured at All unused analog input (A) ports are connected to ground, and output (B) ports are left open. Average RBW kHz V BIAS 0.35 V ST s dBM Submit Documentation Feedback
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TS3L301DGG ACTIVE TSSOP DGG 48 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS3L301DGGE4 ACTIVE TSSOP DGG 48 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS3L301DGGG4 ACTIVE TSSOP DGG 48 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS3L301DGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS3L301DGGRE4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS3L301DGGRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS3L301DGVR ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS3L301DGVRE4 ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS3L301DGVRG4 ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 27-Sep-2007 Addendum-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 11-Aug-2009 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TS3L301DGGR TSSOP DGG 48 2000 346.0 346.0 41.0 TS3L301DGVR TVSOP DGV 48 2000 346.0 346.0 33.0 PACKAGE MATERIALS INFORMATION www.ti.com 11-Aug-2009 Pack Materials-Page 2
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 4040078/F 12/97
48 PINS SHOWN
0,25 0,15 NOM Gage Plane 6,00 6,20 8,30 7,90 0,75 0,50 Seating Plane 0,27 0,17 A 1,20 MAX M0,08 0,10 0,50 0°–8° 14,10 13,90 48DIM A MAX A MIN PINS ** 12,40 12,60 17,10 16,90 0,15 0,05 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153
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