TS3DS10224RUKR.B

TS3DS10224 TI | Alldatasheet

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Technical content

Select A Input (SAI) Select A Output (SAO) Select B Input (SBI) Select B Output (SBO) Copyright © 2016, Texas Instruments Incorporated Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TS3DS10224 SCDS324E –AUGUST 2011–REVISED OCT 2019 TS3DS10224High-SpeedDifferentialCrosspoint,1:4DifferentialMultiplexerand Demultiplexer,2ChannelDifferential1:2MultiplexerandDemultiplexer,orFan-OutSwitch

1 Features

1• Can be configured for – Differential Crosspoint Switching – Differential Single Channel 1:4 Multiplexer and Demultiplexer – Differential 2-Channel 1:2 Multiplexer and Demultiplexer – Differential Fan-Out of Signal Pair to Two Ports Simultaneously

• Bidirectional Operation
• Fail-Safe Protection: IOFF Protection Prevents Current Leakage in Powered-Down State (VCC = 0 V)
• High BW (1.2 GHz Typical)
• Low RON and CON: – 13-Ω RON Typical – 9-pF CON Typical
• ESD Performance (I/O Pins) – ±8-kV Contact Discharge (IEC61000-4-2) – 2-kV Human-Body Model per JESD22-A114E (to GND)
• ESD Performance (All Pins) – 2-kV Human-Body Model per JESD22-A114E
• Small WQFN package (3.00 mm × 3.00 mm, 0.4-mm pitch)

2 Applications

• Differential Crosspoint Switching
• Desktop and Notebook Computers
• DisplayPort Auxiliary Channel Multiplexing
• USB 2.0 Multiplexing
• Netbooks, eBooks, and Tablets

3 Description

The TS3DS10224 device is a bidirectional differential crosspoint, 1:4, or 1:2 multiplexer and demultiplexer; or fan-out switch for high-speed differential signal applications (up to 720 Mbps). The TS3DS10224 logic table can route any input to any output creating a wide range of possible switching or multiplexing configurations. Common configurations include: differential crosspoint switching, differential 1:4 mux, or differential 2-channel 1:2 multiplexer and demultiplexer. The TS3DS10224 offers a high BW of 1.2 GHz with channel RON of 13 Ω (typical). The TS3DS10224 can also be used to fan out a differential signal pair to two ports simultaneously (fan-out configuration). The BW performance is lower in this configuration. The TS3DS10224 operates with a 3-V to 3.6-V power supply. It features ESD protection of up to ±8-kV contact discharge and 2-kV human-body model on its I/O pins. The TS3DS10224 provides fail-safe protection by isolating the I/O pins with high impedance when the power supply (VCC) is not present. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TS3DS10224 WQFN (20) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Functional Block Diagram

SCDS324E –AUGUST 2011–REVISED OCT 2019 www.ti.com Product Folder Links: TS3DS10224 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Table of Contents

6.5 Electrical Characteristics:

6.6 Electrical Characteristics: Fan-Out 1:2

6.7 Switching Characteristics:

6.8 Switching Characteristics: Fan-Out 1:2

6.9 Dynamic Characteristics:

6.10 Dynamic Characteristics: Fan-Out 1:2

12.2 Receiving Notification of Documentation Updates 25

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (May 2019) to Revision E Page Changes from Revision C (November 2017) to Revision D Page Changes from Revision B (December 2016) to Revision C Page Changes from Revision A (May 2013) to Revision B Page

• Added Device Information table, Pin Configuration and Functions section, Specifications section, ESD Ratings table, Detailed Description section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information Changes from Original (June 2011) to Revision A Page

20 OUTA1+6OUTB1+

19 OUTA1–7OUTB1–

2INA– 14 SAI

18 OUTA0+8OUTB0+

17 OUTA0–9OUTB0–

4INB– 12 SBI

16 ENA10ENB

www.ti.com SCDS324E –AUGUST 2011–REVISED OCT 2019 Product Folder Links: TS3DS10224 Submit Documentation FeedbackCopyright © 2011–2019, Texas Instruments Incorporated

5 Pin Configuration and Functions

NO. NAME

1 INA+ I/O A channel signal path

2 INA– I/O A channel signal path

3 INB+ I/O B channel signal path

4 INB– I/O B channel signal path

5 GND — Ground

6 OUTB1+ I/O B channel signal path

7 OUTB1– I/O B channel signal path

8 OUTB0+ I/O B channel signal path

9 OUTB0– I/O B channel signal path

10 ENB I Enable B channel: LOW = disables channel B and places the signal path in high impedance state,

HIGH = enables channel B.

11 SBO I Select B channel output, controls output selection: LOW = selects OUTB0 signals,

HIGH = selects OUTB1 signals. 12 SBI I Select B channel input, controls input selection: LOW = selects INA signals to pass through the B channel, HIGH = selects INB signals to pass through the B channel.

13 VCC — Power supply

14 SAI I Select A channel input, controls input selection: LOW = selects INB signals to pass through the A channel, HIGH = selects INA signals to pass through the A channel.

15 SAO I Select A channel output, controls output selection: LOW = selects OUTA0 signals,

HIGH = selects OUTA1 signals.

16 ENA I Enable A channel: LOW = disables channel A and places the signal path in high impedance state,

HIGH = enables channel A.

17 OUTA0– I/O A channel signal path

18 OUTA0+ I/O A channel signal path

19 OUTA1– I/O A channel signal path

20 OUTA1+ I/O A channel signal path

SCDS324E –AUGUST 2011–REVISED OCT 2019 www.ti.com Product Folder Links: TS3DS10224 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are with respect to ground, unless otherwise specified. (3) VI and VO are used to denote specific conditions for VIO. (4) The input and output voltage rating may be exceeded if the input and output clamp-current ratings are observed. (5) II and IO are used to denote specific conditions for IIO.

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted).(1) MIN MAX UNIT Supply voltage –0.3 4 V Analog I/O voltage(2)(3)(4) –0.3 VCC + 0.3 V Control input voltage(2)(4), VIN –0.3 VCC + 0.3 V ON-state switch current(5), IIO ±100 mA Continuous current through VCC or GND ±100 mA Storage temperature, Tstg –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 VCharged-device model (CDM), per JEDEC specification JESD22-C101 or ANSI/ESDA/JEDEC JS-002(2) ±1000 (1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating CMOS Inputs (SCBA004). (2) TI recommends pulling down to ground unused I/O pins through a 1-kΩ resistor.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted).(1)(2) MIN MAX UNIT VCC Supply voltage 3 3.6 V VIH High-level control input voltage 0.75 × VCC VCC V VIL Low-level control input voltage 0 0.6 V VIO Input and output voltage 0 VCC V TA Operating free-air temperature –40 85 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) TS3DS10224 UNITRUK (WQFN)

20 PINS

RθJA Junction-to-ambient thermal resistance 45.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.8 °C/W RθJB Junction-to-board thermal resistance 17.1 °C/W ψJT Junction-to-top characterization parameter 0.6 °C/W ψJB Junction-to-board characterization parameter 17.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 3.7 °C/W

www.ti.com SCDS324E –AUGUST 2011–REVISED OCT 2019 Product Folder Links: TS3DS10224 Submit Documentation FeedbackCopyright © 2011–2019, Texas Instruments Incorporated (1) VIN and IIN refer to the digital control input pins. (2) For I/O ports, the parameter IOZ includes the input leakage current.

6.5 Electrical Characteristics: Differential 1:4 or 2‑‑Channel 1:2 Configurations

Minimum and maximum values are at TA = –40°C to 85°C; typical values are at TA = 25°C (unless otherwise noted).(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIK Digital input clamp voltage VCC = 3.6 V, II = –18 mA –1.2 –0.9 V IIN Digital input leakage current VCC = 3.6 V, VIN = 0 to 3.6 V ±2 µA IOZ OFF-state leakage current(2) VCC = 3.6 V, VO = 0 V to 3.6 V, VI = 0 V, Switch OFF ±2 µA IOFF Power off leakage current VCC = 0 V, VIN = VCC or GND,VIO = 0 V to 3.6 V ±5 µA ICC Supply current VCC = 3.6 V, IIO = 0, Switch ON or OFF 50 100 µA CIN Digital input capacitance VCC = 3.3 V, VIN = VCC or GND 3 5 pF CIO(OFF) OFF capacitance VCC = 3.3 V, VIO = 3.3 V or 0, f = 10 MHz, Switch OFF 6 7 pF CIO(ON) ON capacitance VCC = 3.3 V, VIO = 3.3 V or 0, f = 10 MHz, Switch ON 9 10 pF rON ON-state resistance VCC = 3.6 V, VI = VCC, IO = –30 mA 13 19 Ω VCC = 3.3 V, VI = 0.5 V, IO = –30 mA 10 Ω ΔrON ON-state resistance match between channels VCC = 3 V, VI = 0 to VCC, IO = –30 mA 2 2.5 Ω rON(flat) ON-state resistance flatness VCC = 3 V, VI = 1.5 V and VCC, IO = –30 mA 4 6 Ω (1) VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins. (2) For I/O ports, the parameter IOZ includes the input leakage current.

6.6 Electrical Characteristics: Fan-Out 1:2 Configurations

TA = –40°C to 85°C; typical values are at VCC = 3.3 V, TA = 25°C (unless otherwise noted).(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIK Digital input clamp voltage VCC = 3.6 V, II = –18 mA –1.2 –0.9 V IIN Digital input leakage current VCC = 3.6 V, VIN = 0 to 3.6 V ±2 µA IOZ OFF-state leakage current(2) VCC = 3.6 V, VO = 0 V to 3.6 V, VI= 0 V, Switch OFF ±2 µA IOFF Power off leakage current VCC = 0 V, VIN = VCC or GND, VIO = 0 V to 3.6 V ±5 µA ICC Supply current VCC = 3.6 V, IIO = 0, Switch ON or OFF 50 100 µA CIN Digital input capacitance VCC = 3.3 V, VIN = VCC or GND 3 5 pF CIO(OFF) OFF capacitance VCC = 3.3 V, VIO = 3.3 V or 0, f = 10 MHz, Switch OFF 6 7 pF CIO(ON) ON capacitance VCC = 3.3 V, VIO = 3.3 V or 0, f = 10 MHz, Switch ON 12 13 pF rON ON-state resistance VCC = 3.6 V, VI = VCC, IO = –30 mA 13 19 Ω ΔrON ON-state resistance match between channels VCC = 3 V, VI = 0 to VCC, IO = –30 mA 2 2.5 Ω rON(flat) ON-state resistance flatness VCC = 3 V, VI = 1.5 V and VCC, IO = –30 mA 4 6 Ω (1) The propagation delay is the calculated RC time constant of the typical ON-State resistance of the switch and the specified load capacitance when driven by an ideal voltage source(zero output impedance). (2) Output skew between center channel and any other channel. (3) Skew between opposite transitions of the same output ( |tPHL – tPLH| ).

6.7 Switching Characteristics: Differential 1:4 or 2‑‑Channel 1:2 Configurations

TA = –40°C to 85°C, VCC = 3.3 V ± 10%, GND = 0 V (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tpd Propagation delay(1) RL = 50 Ω, CL = 2 pF 50 ps tON SAI, SAO, SBI, or SBO to OUTAx or OUTBx RL = 50 Ω, CL = 2 pF 40 100 ns tOFF SAI, SAO, SBI, or SBO to OUTAx or OUTBx RL = 50 Ω, CL = 2 pF 20 30 ns tsk(o) Timing difference between output channels(2) RL = 50 Ω, CL = 2 pF 40 ps tsk(p) Timing difference between propagation delays(3) RL = 50 Ω, CL = 2 pF 40 ps

SCDS324E –AUGUST 2011–REVISED OCT 2019 www.ti.com Product Folder Links: TS3DS10224 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated (1) The propagation delay is the calculated RC time constant of the typical ON-State resistance of the switch and the specified load capacitance when driven by an ideal voltage source (zero output impedance). (2) Output skew between center channel and any other channel. (3) Skew between opposite transitions of the same output ( |tPHL – tPLH| ).

6.8 Switching Characteristics: Fan-Out 1:2 Configurations

TA = –40°C to 85°C, VCC = 3.3 V ± 10%, GND = 0 V (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tpd Propagation delay(1) RL = 50 Ω, CL = 2 pF 140 ps tON SAI, SAO, SBI, or SBO to OUTAx or OUTBx R = 50 Ω, CL = 2 pF 40 100 ns tOFF SAI, SAO, SBI, or SBO to OUTAx or OUTBx RLL = 50 Ω, CL = 2 pF 20 30 ns tsk(o) Timing difference between output channels(2) RL = 50 Ω, CL = 2 pF 60 ps tsk(p) Timing difference between propagation delays(3) RL = 50 Ω, CL = 2 pF 60 ps

6.9 Dynamic Characteristics: Differential 1:4 or 2‑‑Channel 1:2 Configurations

TA = –40°C to 85°C; typical values are at VCC = 3.3 V ± 10% and TA = 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS TYP UNIT BW Bandwidth RL = 50 Ω, Switch ON 1.2 GHz OISO OFF Isolation RL = 50 Ω , f = 250 MHz –30 dB XTALK Crosstalk RL = 50 Ω , f = 250 MHz –30 dB

6.10 Dynamic Characteristics: Fan-Out 1:2 Configurations

TA = –40°C to 85°C; typical values are at VCC = 3.3 V ± 10% and TA = 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS TYP UNIT BW Bandwidth RL = 50 Ω, Switch ON 500 MHz OISO OFF Isolation RL = 50 Ω , f = 250 MHz –30 dB XTALK Crosstalk RL = 50 Ω , f = 250 MHz –30 dB

6.11 Typical Characteristics

6.11.1 Single-Channel 1:4 or Dual-Channel 1:2 Configurations

Figure 1. ON-Resistance vs VIN Figure 2. Insertion Loss vs Frequency Figure 3. Off Isolation vs Frequency Figure 4. Crosstalk vs Frequency

6.11.2 Fan-Out 1:2 Configurations

Figure 5. ON-Resistance vs VIN Figure 6. Insertion Loss vs Frequency Figure 7. Off Isolation vs Frequency Figure 8. Crosstalk vs Frequency

NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics:PRR ≤ 10 MHz, ZO = 50 Ω, t r ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement.

7 Parameter Measurement Information

Figure 9. Test Circuit and Voltage Waveforms

NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, t r ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. Figure 10. Test Circuit and Voltage Waveforms

Select A Input (SAI) Select A Output (SAO) Select B Input (SBI) Select B Output (SBO) Copyright © 2016, Texas Instruments Incorporated TS3DS10224 SCDS324E –AUGUST 2011–REVISED OCT 2019 www.ti.com Product Folder Links: TS3DS10224 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The TS3DS10224 is a 3-V, bidirectional, differential crosspoint, differential 1:4, 2-channel differential 1:2 multiplexer and demultiplexer, or fan-out switch for high-speed differential signal applications. The TS3DS10224 can route any input to any output creating a wide range of possible switching or multiplexing configurations. Differential crosspoint switching, differential 1:4 mux, or 2-channel differential 1:2 multiplexer and demultiplexer are commonly used configurations of the device. Additionally the TS3DS10224 can also be used to fan out a differential signal pair to two ports simultaneously (fan-out configuration). However, the BW performance is lower in this configuration.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Fail-Safe Protection

IOFF protection prevents current leakage in powered down state (VCC = 0 V). The TS3DS10224 device places the signal paths in a high-impedance state when the device is not powered. This isolates the data bus if the IC loses power on the supply pin.

8.4 Device Functional Modes

8.4.1 Enable and Disable

place them in a high-impedance (Hi-Z) state. Table 1. Enable and Disable Function Table

8.4.2 Differential Crosspoint Switch

reversible connector in USB Type-C applications. the Select A Input (SAI) and Select B Input (SBI) pins. Table 2. Differential Crosspoint Switch Function Table

Figure 14. Differential Crosspoint Switch Block Diagram

The TS3DS10224 can be configured to be differential 2-channel 1:2 mux. (SAO) and Select B Output (SBO) pins. Table 3. 2-Channel 1:2 Mux Function Table Figure 15. 2-Channel 1:2 Block Diagram

The TS3DS10224 can be configured as differential 1-channel 1:4 mux. Output (SAO) and Select B Output (SBO) pins. Unused pins INB+ and INB– must be left floating in this configuration. Table 4. 1-Channel 1:4 Mux Function Table Figure 16. 1-Channel 1:4 Mux Functional Block Diagram

8.4.5 Fan-Out 1:2 Configuration

The TS3DS10224 can be configured in a differential fan-out 1:2 mux. The truth table below shows that the inputs INA or INB can be routed to output A or output B simultaneously. by toggling the Select A Output (SAO) and Select B Output (SBO) pins. Unused pins INB+ and INB– must be left floating in this configuration. Table 5. Fan-Out 1:2 Function Table Figure 17. Fan-Out 1:2 Functional Block Diagram

SCDS324E –AUGUST 2011–REVISED OCT 2019 www.ti.com Product Folder Links: TS3DS10224 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Table 6. SAI SBI SA0 SBO OUTA0 OUTA1 OUTB0 OUTB1 FUNCTIONAL MODE 0 0 0 0 INB — INA — Crosspoint, 1-channel 1:4 mux 0 0 0 1 INB — — INA 1-channel 1:4 mux 0 0 1 0 — INB INA — 1-channel 1:4 mux 0 0 1 1 — INB — INA 1-channel 1:4 mux 0 1 0 0 INB — INB — 0 1 0 1 INB — — INB 0 1 1 0 — INB INB — 0 1 1 1 — INB — INB 1 0 0 0 INA — INA — Fan-out 1:2 configuration 1 0 0 1 INA — — INA Fan-out 1:2 configuration 1 0 1 0 — INA INA — Fan-out 1:2 configuration 1 0 1 1 — INA — INA Fan-out 1:2 configuration 1 1 0 0 INA — INB — Crosspoint, 2-channel 1:2 mux, 1-channel 1:4 mux 1 1 0 1 INA — — INB 2-channel 1:2 mux,1-channel 1:4 mux 1 1 1 0 — INA INB — 2-channel 1:2 mux,1-channel 1:4 mux 1 1 1 1 — INA — INB 2-channel 1:2 mux,1-channel 1:4 mux

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TS3DS10224 device can be configured for a variety of applications which makes this a great utility device. The most unique feature of this device is the ability to operate as a differential crosspoint switch.

9.2 Typical Applications

Figure 18. 1-Channel Differential 1:4 Mux Application

9.2.1.1 Design Requirements

The thermal pad may be left floating or connected to ground.

9.2.1.2 Detailed Design Procedure

9.2.1.3 Application Curves

Figure 19. 480-Mbps USB 2.0 Eye Diagram Through Path Figure 20. 480-Mbps USB 2.0 Eye Diagram With Device Figure 21. 2-Channel Differential Crosspoint Switch Schematic

9.2.2.1 Design Requirements

9.2.3 Fan-Out Switch

Figure 22. Fan-Out Switch Schematic

9.2.3.1 Design Requirements

The bandwidth performance is lower in this application (500 MHz).

Figure 23. 2-Channel Differential 1:2 SPDT Switch Schematic

10 Power Supply Recommendations

out lower frequency noise and to provide better load regulation across the frequency spectrum.

11 Layout

11.1 Layout Guidelines

• The thermal pad may be left floating or connected to the ground plane
• Place supply-bypass capacitors as close to the VCC pin as possible and avoid placing the bypass capacitors near the positive and negative traces.
• The high-speed positive and negative traces must always be matched and the lengths must not exceed 4 inches; otherwise, the eye diagram performance may be degraded. In layout, the impedance of positive and negative traces must match the cable characteristic differential impedance for optimal performance.
• Route the high-speed signals using a minimum of vias and corners to reduce signal reflections and impedance changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference from the other layers of the board. Be careful when designing test points on twisted pair lines; through-hole pins are not recommended.
• When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This reduces reflections on the signal traces by minimizing impedance discontinuities.
• Do not route signal traces under or near crystals, oscillators, clock signal generators, switching regulators, mounting holes, magnetic devices, or ICs that use or duplicate clock signals.
• Avoid stubs on the high-speed signal traces because they cause signal reflections.
• Route all high-speed signal traces over continuous GND planes, with no interruptions.
• Avoid crossing over anti-etch, commonly found with plane splits.
• Due to high-frequency signal traces, TI recommends a printed-circuit board with at least four layers; two signal layers separated by a ground and power layer as shown in Figure 24.

Figure 24. Four-Layer Board Stack-Up number of signal vias reduces EMI by reducing inductance at high frequencies.

0603 Cap

11.2 Layout Example

Figure 25. WQFN Layout Example

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following: Implications of Slow or Floating CMOS Inputs (SCBA004)

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 10-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TS3DS10224RUKR Active Production WQFN (RUK) | 20 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ZTB TS3DS10224RUKR.A Active Production WQFN (RUK) | 20 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ZTB TS3DS10224RUKR.B Active Production WQFN (RUK) | 20 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ZTB TS3DS10224RUKRG4 Active Production WQFN (RUK) | 20 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ZTB TS3DS10224RUKRG4.A Active Production WQFN (RUK) | 20 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ZTB TS3DS10224RUKRG4.B Active Production WQFN (RUK) | 20 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ZTB (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 10-Nov-2025 Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TS3DS10224RUKR WQFN RUK 20 3000 346.0 346.0 33.0 TS3DS10224RUKRG4 WQFN RUK 20 3000 346.0 346.0 33.0 Pack Materials-Page 2

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. WQFN - 0.8 mm max heightRUK 20 PLASTIC QUAD FLATPACK - NO LEAD3 x 3, 0.4 mm pitch 4229651/A

www.ti.com PACKAGE OUTLINE C SEE TERMINAL DETAIL 20X 0.25 0.15 1.7 0.05 20X 0.5 0.3

0.8 MAX

(DIM A) TYP OPT 02 SHOWN 0.05 0.00 16X 0.4 1.6 A 3.1 2.9 B 3.1 2.9 0.25 0.15 0.5 0.3 WQFN - 0.8 mm max heightRUK0020B PLASTIC QUAD FLATPACK - NO LEAD 4222676/A 02/2016 DIMENSION A OPTION 01 (0.1) OPTION 02 (0.2) PIN 1 INDEX AREA 0.08 C SEATING PLANE 5 11 6 10 20 16 (OPTIONAL) PIN 1 ID

0.1 C A B

0.05 EXPOSED THERMAL PAD

21 SYMM

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 4.000 DETAIL OPTIONAL TERMINAL TYPICAL

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MIN

0.05 MAX

20X (0.2) 20X (0.6) ( ) TYP VIA 0.2 16X (0.4) (2.8) (2.8) (0.6) TYP ( 1.7) (R ) TYP 0.05 WQFN - 0.8 mm max heightRUK0020B PLASTIC QUAD FLATPACK - NO LEAD 4222676/A 02/2016 SYMM 6 10 1620 SYMM LAND PATTERN EXAMPLE SCALE:20X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED METAL SOLDER MASK OPENINGSOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED)

www.ti.com EXAMPLE STENCIL DESIGN 20X (0.6) 20X (0.2) 16X (0.4) (2.8) (2.8) 4X ( 0.75) (0.47) TYP (0.47) TYP (R ) TYP0.05 WQFN - 0.8 mm max heightRUK0020B PLASTIC QUAD FLATPACK - NO LEAD 4222676/A 02/2016 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM METAL TYP SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL EXPOSED PAD 21: 78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X SYMM 6 10 1620

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