TS3DDR32611 TI1 | Alldatasheet
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CH0CH1CH2CH3CH4CH5CH6CH7CH8CH9CH10CH11CH12CH13 CKE0CKE1 VTT Regulator OBT_EN VTT_EN PGND VTTSNS VTT VDD3.3V Supply GND VDDQ TS3DDR32611 CH14CH15CH16CH17CH18CH19CH20CH21CH22 CH24 RESET_N VREF VLDOIN CH23 CH25 TS3DDR32611 www.ti.com SCDS347A –AUGUST 2013–REVISED SEPTEMBER 2013 1APeakSink/SourcePCDDR3TerminationRegulatorwithIntegratedIsolationSwitchand LowPowerModeOperation Check for Samples: TS3DDR32611 1FEATURES DESCRIPTION The TS3DDR32611 is a sink/source double data rate• VDD Range – 3.0V to 3.6V type III (PCDDR3) termination regulator with a 1%• RON 1.75Ω typical accuracy buffered reference output. It has built-in
- Channel Count – 26 termination SPST switches that can be disconnected when the memory system undergoes lower speed• VDDQ – Input Voltage 1.2V to 3.5V operation without the need of voltage termination.• VTT – VDDQ/2 typical with 1A sink/source Turning off these switches enables significant powercapability saving on the memory system. The switches on-state
- VREF – VDDQ/2±1% × VDDQ resistance has a typical value of only 1.75Ω which helps retain signal integrity on the signal lines.• Switch Time – (TON/OFF) 100ns Max
- IDD Supply Current The TS3DDR32611 is powered from a 3.3V supply. The VDDQ pin takes 1.2V to 1.8V input while the– High Speed Mode (IDD,HS) 220 µA Max output voltage at VTT pin is tracking 1/2 × VDDQ. The– Low Speed Mode (IDD,LS) 220 µA Max regulator’s VTT output is capable of sinking/sourcing – Power Down Mode (IDD,PD) 5 µA Max up to 1A current, while the VREF pin output is 1/2VDDQ±1% × VDDQ with 5mA current• Special Features sinking/sourcing capability. The TS3DDR32611 has 4– 1.8-V Compatible Control Inputs (VTT_EN, modes of operation: high speed, low speed, VREFODT_EN) mode and power down mode, depending on the – High current Sinking/Sourcing Capability: control signals VTT_EN and ODT_EN. These 1A Max different modes of operation provide flexibility to establish a memory system’s performance and power• 48-Ball ZQC Package (4mm x 4mm, 0.5mm consumption.pitch) The TS3DDR32611 is situated within a small 48 balls BGA package with only 4mm x 4mm in size, whichAPPLICATIONS makes it a perfect candidate to be used in mobile• Double Data Rate type 3 (PCDDR3) termination applications.and regulation in mobile devices SWITCH DIAGRAM Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2013, Texas Instruments IncorporatedProducts conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
C B A 1 2 3 VTT VTT GND VLDO IN CH23 CH21 VDDQ VDD CH22 VTT EN CH24 CH20 PGND VTT REF VTT SNS NC GND ODT EN CH25 CH19 GND GND GND CH15 CH11 CH7 CH17 CH13 CH9 CH16 CH12 CH8 GND GND GND GND GND GND CH18 CH14 CH10 CH1 CH3 CH5 CH4 CH2 CH0 CH6 F E D G 4 5 6 7 Switch I/O GND LDO Power LDO I/O Control C B A 7 6 5 VTTVTTGND VLDO INCH23CH21 VDDQVDDCH22 VTT ENCH24CH20 PGNDVTT REF VTT SNSNCGND ODT ENCH25CH19 GNDGNDGND CH15CH11CH7 CH17CH13CH9 CH16CH12CH8 GNDGNDGND GNDGNDGND CH18CH14CH10 CH1 CH3 CH5 CH4 CH2 CH0 CH6 F E D G 4 3 2 1 NC TS3DDR32611 SCDS347A –AUGUST 2013–REVISED SEPTEMBER 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DIE SIZE: 4.0 mm × 4.0 mm BUMP PITCH: 0.5 mm TS3DDR32611 Pin Mapping(1) 7 6 5 4 3 2 1 G CH5 CH9 CH13 CH17 CH22 VDD VDDQ F CH3 CH7 CH11 CH15 CH21 CH23 VLODIN E CH1 GND GND GND GND VTT VTT D CH0 GND GND GND GND NC VTTSNS C CH2 GND GND GND VREF PGND B CH4 CH8 CH12 CH16 CH20 CH24 VTT_EN A CH6 CH10 CH14 CH18 CH19 CH25 ODT_EN (1) The NC must be floating, and cannot be connected to anything. PIN FUNCTIONS PIN TYPE DESCRIPTION NO. NAME C4, C5, C6, D3, D4, D5, GND — Signal GroundD6, E3, E4, E5, E6 E1, E2 VTT O Power output for VTT LDO, need to connect 10-μF or greater MLCC for stability C1 PGND — Power GND for VTT LDO D1 VTTSNS I VTT LDO voltage sense input F1 VLDOIN I Power supply input for VTT/ VTTREF C2 VREF O VREF buffered reference output. Need to connect 0.22-μF or greater MLCC for stability. B1 VTT_EN I Enable signal for VTT and VREF output A1 ODT_EN I Enable signal for Switch G1 VDDQ I VDDQ input, reference input for VREF G2 VDD I Device power supply input 3.3 V typical D7, E7, C7, F7, B7, G7, A7, F6, B6, G6, A6, F5, B5, G5, A5, F4, B4, G4, CH0-CH25 I/O Switch input or output A4, A3, B3, F3, G3, F2, B2, A2 D2 NC — Not connected, must be floating and cannot be connected to any signal
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www.ti.com SCDS347A –AUGUST 2013–REVISED SEPTEMBER 2013 FUNCTION TABLE STATE VTT_EN(1) ODT_EN(1) VTT VREF SWITCH Power Down mode(2) L L OFF(Discharge) OFF(Discharge) Disabled Low Speed mode H L ON ON Disabled High Speed mode H H ON ON Enabled (1) The VTT_EN and ODT_EN pins has 6MΩ weak pull-down resistor to GND to make its default value to be LOW. (2) For VTT_EN= L and ODE_EN= H, the TS3DDR32611 will also stays in the power down mode. However, there will be an increased leakage current of up to max 25µA depending on the voltage level of ODT_EN and is thus not a recommended setting to use. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted)(1) (2) MIN MAX UNIT VDD Supply voltage range(3) –0.3 5.5 V VCTRL Control input (VTT_EN, ODT_EN) voltage range(3) –0.3 5.5 V VDDQ VDDQ input voltage range(3) –0.3 3.6 V VLDOIN VLDOIN input voltage range(3) –0.3 3.6 V VTT, VREF VTT, VREF output voltage range(3) –0.3 3.6 V VTTSNS VTTSNS input voltage range(3) –0.3 3.6 V PGND PGND input voltage range(3) –0.3 0.3 V HBM Electrostatic discharge QSS 009-105 (JESD22-A114A) 2 kV CDM Electrostatic discharge QSS 009-147 (JESD22-C101B.01) 500 V TJ Junction temperature –40 125 °C TA Operating free-air temperature –55 150 °C (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum. (3) All voltages are with respect to GND, unless otherwise specified. PACKAGE THERMAL IMPEDANCE(1) TYP UNIT θJA Package thermal impedance ZQC package 101(2) °C/W (1) The package thermal impedance is calculated in accordance with JESD 51-7. (2) 69.2°C/W With 4 Central GND vias when layout. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VDD Supply voltage range(1) 3.0 3.6 V VCTRL Control input (VTT_EN, ODT_EN) voltage range(1) 0 3.6 V VDDQ VDDQ input voltage range(1) 1.2 1.5 V VLDOIN VLDOIN input voltage range(1) VTT+0.4 1.5 V VTT, VREF VTT, VREF output voltage range(1) 0 0.75 V VTTSNS VTTSNS input voltage range(1) 0 0.75 V PGND PGND input voltage range(1) –0.1 0.1 V TA Operating free-air temperature –40 85 °C (1) All voltages are with respect to GND, unless otherwise specified. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links :TS3DDR32611
SCDS347A –AUGUST 2013–REVISED SEPTEMBER 2013 www.ti.com
ELECTRICAL CHARACTERISTICS
TA = –40°C to 85°C, Typical values are at VDD = 3.3V, TA = 25°C, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT VDD supply current in high No load, VTT_EN=ODT_EN= 1.8V,IVDD(HS) VDD = 3.3V 150 220 µAspeed mode(1) VDDQ=1.5 V No load, VTT_EN=1.8V,VDD supply current in lowIVDD(LS) VDD = 3.3V 150 220 µAspeed mode(1) ODT_EN= 0V, VDDQ=1.5V VDD supply current in power No load, VTT_EN=0V,ODT_EN= 0V,IVDD(PD) VDD = 3.3V 1 5 µAdown mode(1) VDDQ=1.5V VLDOIN supply current in high or No load, VTT_EN=H, ODT_EN= H orIVLDOIN VDD = 3.3V 1 5 µAlow speed mode L, VDDQ=1.5V VLDOIN supply current in power No load, VTT_EN=L, ODT_EN=H orIVLDOIN(PD) VDD = 3.3V 1 5 µAdown mode L, VDDQ=1.5V VTT OUTPUT VTT Output voltage VDDQ/2 V |IVTT|< 60 mA -20 ±15 20 Output voltage tolerance to VDDQ = 1.25V,VTTTOL |IVTT|< 550 mA -35 ±25 35 mV1/2VDDQ 1.35V, 1.5V |IVTT|< 1 A -60 ±35 60 IVTT(SRC) Source current limit VDDQ = 1.5 V VTT=VTTSNS=0.6 V 1000 mA IVTT(SINK) Sink current limit VDDQ = 1.5 V VTT=VTTSNS=0.9 V 1000 mA Max Source or Sink currentIVTT(max) VDDQ = 1.5 V VTT=VTTSNS=0 V 1.5 Acapability VTT_EN=L, ODT_EN=H or L,IVTT(DIS) VTT Discharge current VDDQ = 0 V 10 mAVTT = 0.5 V, TA=25°C IVTTSNS(BIAS) VTTSNS Input Bias current VTTSNS=VREF No load, VTT_EN=H, ODT_EN= H –0.1 0.1 µA VREF OUTPUT VREF Output voltage VDDQ/2 V IVREF(SRC) Source current limit VDDQ = 1.5V VREF=0 V 10 mA IVREF(SINK) Sink current limit VDDQ = 0V VREF=1.5 V 10 mA VTT_EN=L,ODT_EN=H or L,VVREF(DIS) VREF Discharge current VDDQ = 0V 2 mAVREF=0.5 V, TA = 25°C VDDQ INPUT IVDDQ VDDQ input current VDDQ = 1.5V 30 40 µA ISOLATION SWITCH RON ON-state resistance VDD = 3.3V VI/O = 0.75 V, |IVTT|= 18 mA 1.75 4 Ω RON, FLAT ON-state resistance flatness VDD = 3.3V VI/O = 0 V to 0.75 V, |IVTT|= 18 mA 0.2 0.4 Ω ON-state resistance matchΔRON VDD = 3.3V VI/O = 0.75 V, |IVTT|= 18 mA 0.2 Ωbetween channels DIGITAL CONTROL INPUTS (VTT_EN, ODT_EN) VIH Input logic high VDD = 3.0 V to 3.6 V 1.3 V VIL Input logic low VDD = 3.0 V to 3.6 V 0.6 V VLHYST Hysteresis voltage 0.5 V ILK Input leak current –1 1 µA OVER-TEMPERATURE PROTECTION Shutdown temperature 150 TOTP Over temperature protection °C Hysteresis 30 (1) For ODT_EN and VTT_EN, If the VIH is less than 1.8V but more than Max VIH, or VIL is more than 0V but less than Max VIL, it will cause the IVDD has the max 25µA increase based on the voltage at ODT_EN and VTT_EN.
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www.ti.com SCDS347A –AUGUST 2013–REVISED SEPTEMBER 2013 DYNAMIC CHARACTERISTICS TA = –40°C to 85°C, Typical values are at VCC = 3.3V, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Switching time between lowtON /OFF RL = 50Ω, CL = 5pF VDD = 3.0 V to 3.6 V 100 nsspeed and high speed mode VDD = 3.0V to 3.6V,tRAMP(VTT) VTT ramp time CVTT= 20 µF 50 µsIVTT=0 VDD = 3.0V to 3.6V,tRAMP(VREF) VREF ramp time CVREF= 220 nF 30 µsIVREF =0 Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links :TS3DDR32611
Figure 1. VTT Load Regulation (0.75V) Figure 2. VTT Load Regulation (0.675V) Figure 3. VTT Load Regulation (0.625V) Figure 4. VREF Load Regulation (0.75V) Figure 5. VREF Load Regulation (0.675V) Figure 6. VREF Load Regulation (0.625V)
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Figure 7. Start-up Waveform for VTT (Power-down to High Figure 8. Start-up Waveform for VREF (Power-down to High
SCDS347A –AUGUST 2013–REVISED SEPTEMBER 2013 www.ti.com
REVISION HISTORY
Changes from Original (August 2013) to Revision A Page
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www.ti.com 3-Oct-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TS3DDR32611ZQCR ACTIVE BGA MICROSTAR JUNIOR ZQC 48 2500 Green (RoHS & no Sb/Br) SNAGCU Level-2-260C-1 YEAR XSL2611 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TS3DDR32611ZQCR BGA MI CROSTA R JUNI OR PACKAGE MATERIALS INFORMATION www.ti.com 30-Oct-2013 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TS3DDR32611ZQCR BGA MICROSTAR JUNIOR ZQC 48 2500 336.6 336.6 31.8 PACKAGE MATERIALS INFORMATION www.ti.com 30-Oct-2013 Pack Materials-Page 2
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