TS3842BCD

TS3842B TSC | Alldatasheet

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Technical content

Features

High Performance Current Mode Controller Trimmed Oscillator Discharge Current for Precise Duty Cycle Control Current Mode Operation to 500KHz Automatic Feed Forward Compensation Latching PWM for Cycle-By-Cycle Current Limiting Internally Trimmed Reference with Undervoltage Lockout High Current Totem Pole Output Undervoltage Lockout with Hystersis Low Start-Up and Operating Current SOP-8 DIP-8 5.0V Reference Latching PWM VCC Undervoltage Lockout Oscillator Error Amplifier 7(12) VC 7(11) Output 6(10) Power Ground 5(8) 3(5) Current Sense Input Vref 8(14) 4(7) 2(3) 1(1) R T/CT V oltage Feedback Input R R Vref Undervoltage Lockout Output Compensation VCC The document contains information on a new product.Specifications and information herein are subject to change without notice. Designed for Off-Line and DC-to-DC converter applications. TS3842/3843BCD DIP-8 TS3842/3843BCS SOP-8 -20 to +85/G43a DEVICE (Ambient) PACKAGEOPERATING TEMPERATURE

Total Power Supply and Zener Current (I CC +IZ) 30 mA Output Current Source or Sink (Note 1) Io 1.0 A Output Energy (Capacitive Load per Cycle) W 5.0 µJ Current Sense and Voltage Feedback Inputs Vin -0.3 to +5.5 V Error Amp Output Sink Current Io 10 mA Power Dissipation and Thermal Characteristics Plastic DIP Maximum Power Dissipation @ TA=25/G43a Thermal Resistance Junction to Air Plastic SOP Maximum Power Dissipation @ TA=25/G43a Thermal Resistance Junction to Air PD R θJA PD R θJA 862 145 1.25 100 mW /G43a/W W /G43a/W Operating Junction Temperature T J 0 to +150 /G43a Operating Ambient Temperature T A -20 to +85 /G43a Storage Temperature Range Tstg -25 to +150 /G43a

Electrical Characteristics

CHARACTERISTIC SYMBOL MIN TYP MAX UNIT Reference Output Voltage (Io=1.0mA,TJ = 25/G43a) Vref 4.9 5.0 5.1 V Line Regulation (VCC =12V to 25V) Regline - 2.0 20 mV Load Regulation (Io =1.0mA to 20mA) Regload - 3.0 25 mV Temperature Stability Ts - 0.2 - mV//G43a Total Output Variation over Line,Load ,and Temperature Vref 4.82 - 5.18 V Output Noise Voltage (f = 10Hz to 10kHz, TJ=25/G43a) Vn - 50 - µV Long Term Stability ( TA=125/G43a for 1000 Hours) S- 5 . 0 - m V Output Short Circuit Current Isc -30 -85 180 mA OSCILLATOR SECTION Frequency TJ=25/G43a 47 52 57 TA=Tlow to Thigh 46 - 60 Frequency Change with Voltage (VCC =12V to 25V) /G4d4fosc//G4d4V -0 . 2 1 . 0 % Frequency Change with Temperature TA=Tlow to Thigh Oscillator Voltage Swing ( Peak-to-Peak) Vosc - 1.6 - V Discharge Current (Vosc=2.0V) TJ=25/G43a 7.5 8.4 9.3 TA=Tlow to Thigh 7.2 - 9.5 KHz mA /G4d4fosc//G4d4T Fosc Idischg -5 . 0- REFFRENCE SECTION VCC =15V (Note 2), RT=10K, CT=3.3nF, TA=Tlow to Thigh (Note 3), unless otherwise noted.

CHARACTERISTIC SYMBOL MIN TYP MAX UNIT ERROR AMPLIFIER SECTION Voltage Feedback Input (Vo=2.5V) VFB 2.42 2.5 2.58 V Input Bias Current (VFB =5.0V) I IB - -0.1 -2.0 /G97A Open-Loop Voltage Gain (Vo=2.0V to 4.0V) AVOL 65 90 - dB Unity Gain Bandwidth (TJ=25/G43a) BW 0.7 1.0 - MHz Power Supply Rejection Radio (VCC =12V to 25V) PSRR 60 70 - dB Output Current Sink (Vo=1.1V, VFB =2.7V) I sink 2.0 12 - Source ( Vo=5.0V, VFB =2.3V) I Source -0.5 -1.0 - Output Voltage Swing High State (RL=15K to ground, VFB =2.3V) V OH 5.0 6.2 - Low State (RL=15K to Vref, VFB =2.7V) V OL -0 . 8 1 . 1 CURRENT SENSE SECTION Current Sense Input Voltage Gain (Note 4&5) Av 2.85 3.0 3.15 V/V Maximum Current Sense Input Threshold(Note 4) Vth 0.9 1.0 1.1 V Power Supply Rejection Radio VCC =12V to 25V,Note 4 Input Bias Current IIB - -2.0 -10 µA Propagation Delay(Current Sense Input to Output) tPLH(IN/OUT) -1 5 0 3 0 0 n s mA PSRR - 70 - dB V VCC =15V (Note 2), RT=10K, CT=3.3nF, TA=Tlow to Thigh (Note 3), unless otherwise noted.

Note: 1.Maximum package power dissipation limits must be observed. 2. Adjust VCC above the Start-Up threshold before setting to 15V. 3. Low duty cycle pulse technique are used during test to maintain junction temperature as close to ambient as possible. Tlow = -20/G43a ,Thigh = +85/G43a 4. This parameter is measured at the latch trip point with VFB = 0V. /G2b3/G2b3/G2b3/G2b3/G2b3/G4d4/G4d4/G4d4/G4d4/G4d4V Output Compensation 5. Comparator gain is defined as : Av = /G4d4/G4d4/G4d4/G4d4/G4d4V Current Sense Input CHARACTERISTIC SYMBOL MIN TYP MAX UNIT OUTPUT SECTION Output Voltage Low State (Isink=20mA) VOL -0 . 1 0 . 4 (Isink=200mA) - 1.6 2.2 High State (Isource=20mA) VOH 13 13.5 - (Isource=200mA) 12 13.4 - Output Voltage with UVLO Activated VCC =6.0V,Isink=1.0mA Output Voltage Rise Time (CL=1.0nF,TJ=25/G43a) tr - 50 150 ns Output Voltage Fall Time (CL=1.0nF,TJ=25/G43a) tf - 50 150 ns UNDERVOLTAGE LOCKOUT SECTION Start-Up Threshold TS3842B 14.5 16 17.5 TS3843B 7.8 8.4 9.0 Minimum Operating Voltage After Turn-On TS3842B 8.5 10 11.5 TS3843B 7.0 7.6 8.2 PWM SECTION Duty Cycle Maximum DCmax 94 96 - Minimum DCmin - - 0 TOTAL DEVICE Power Supply Current Start-Up, V CC = 14V - 0.25 0.5 Operating (Note 2) - 12 17 Power Supply Zener Voltage (ICC =25mA) Vz 30 36 - V V VOL (UVLO) ICC mA Vth V VCC(min) V -0 . 1 1 . 1 V VCC =15V (Note 2), RT=10K, CT=3.3nF, TA=Tlow to Thigh (Note 3), unless otherwise noted.

Two undervoltage lockout comparators have been incorporated to guarantee that the IC is fully functional before the output stage is enabled. The positive power supply terminal (Vcc) and the reference output (Vref) are each monitored by separate comparators. Each has built-in hysteresis to prevent erratic output behavior as their respective thresholds are crossed. The large hysteresis and low start-up current of the TS3842B makes it ideally suited in off-line converter applications where efficient bootstrap start-up technique (Figure 33). 36V zener is connected as a shunt regulator from Vcc to ground. Its purpose is to protect the IC from excessive voltage that can occur during system start-up. The minimum operating voltage for the TS3842B is 11V. Output These devices contain a single totem pole output stage that was specifically designed for direct drive of power MOSFET’s. It is capable of up to ±1.0A peak drive current and has a typical rise and fall time of 50 ns with a 1.0nF load. Additional internal circuitry has been added to keep the output in a sinking mode whenever an undervoltage lockout is active. This characteristic eliminates the need for an external pull-down resistor. The SOP-8 surface mount package provides separate pins for Vc(output supply) and Power Ground. Proper implementation will significantly reduce the level of switching transient noise imposed on the control circuitry. This becomes particularly useful when reducing the Ipk(max) clamp level. The separate Vc supply input allows the designer added flexibility in tailling the drive voltage independent of Vcc. A zener clamp is typically connected to this input when driving power MOSFETs in systems where Vcc is greater than 20V. Figure 25 shows proper power and control ground connections in a current sensing power MOSFET application. Reference The 5.0V bandgap reference is trimmed to ±2.0% on the TS3842B. Its primary purpose to supply charging current to the oscillator timing capacitor. The reference has short circuit protection and is capable of providing in excess of 20mA for powering additional control system circuitry. Design Considerations Do not attempt to construct the converter on wire wrap or plug-in prototype boards. High frequency circuit layout techniques are imperative to prevent pulsewidth jitter. This is usually caused by excessive noise pick-up imposed on the Current Sense or Voltage Feedback inputs. Noise immunity can be improved by lowering circuit impedances at these points. The printed circuit layout should contain a ground plane with low-current signal and high-current switch and output grounds returning separate paths back to the input filter capacitor. Ceramic bypass capacitors (0.1µF) connected directly to Vcc,Vc, and Vref may be required depending upon circuit layout.

Undervoltage Lockout(contd.) This provides a low impedance path for filtering the high frequency noised. All high current loops should be kept as short as possible using heavy copper runs to minimize radiated EMI. The Error Amp compensation circuitry and the converter output voltage divider should be located close to the IC and as far as possible from the power switch and other noise generating components. Current mode converters can exhibit subharmonic oscillations when operating at a duty cycle greater than 50% with continuous inductor current. This instability is independent of the regula- tors closed loop characteristics and is caused by the simultaneous operating conditions of fixed frequency and peak current detecting. Figure 19(A) shows the phenomenon graphically. At t switch conduction begins causing the inductor current to rise at a slope of m1. This slope is a function of the input voltage divided by the inductance. At t1, the Current Sense Input reaches the threshold established by the control voltage. This causes the switch to turn off and the current to decay at a slope of m2, until the next oscillator cycle. This unstable condition can be shown if a perturbation is added to the control voltage, resulting in a small /G4d4/G4d4/G4d4/G4d4/G4d41(dashed line). With a fixed oscillator period, the current decay time is reduced, and the minimum current at switch turn-on(t2) is increased by /G4d4/G4d4/G4d4/G4d4/G4d41+/G4d4/G4d4/G4d4/G4d4/G4d41m 2/m1. The minimum current at the next cycle (t3) decreases to (/G4d4/G4d4/G4d4/G4d4/G4d41+ /G4d4/G4d4/G4d4/G4d4/G4d41m 2/m1)(m2/m1). This perturbation is multiplied by m2/m1 on each succeeding cycle, alternately increasing and decreasing the inductor current at switch turn-on. Several oscillator cycles may be required before the inductor current reaches zero causing the process to commence again. If m2/ m 1 is greater than 1, the converter will be unstable. Figure 19(B) shows that by adding an artificial ramp that is synchronized with the PWM clock to the control voltage, the /G4d4/G4d4/G4d4/G4d4/G4d41 perturbation will decrease to zero on succeeding cycles. This compensating ramp (m3) must have a slope equal to or slightly greater than m2/2 for stability. With m2/2 slope compensation, the average inductor current follows the control voltage yielding true current mode operation. The compensating ramp can be derived from the oscillator and added to either the Voltage Feedback or Current Sense inputs (Figure 32). Figure 19 - Continuous Current Waveforms Control V oltage Inductor Current Oscillator Period Control Voltage Inductor Current Oscillator Period (A) (B) m 1 m 2 t0 t1 t2 t3 m 3 m 2 t4 t5 t6 m 1 11 m 2 m 1 11 m 2 m 1 m 2 m 1

Undervoltage Lockout(contd.) Figure 33-27 Watt Off-Line Regulation All outputs are at nominal load currents unless otherwise noted. MUR110+ S R R R 5.0V Ref Q Bias EA 5(9) 7(1 1) 6(10) 5(8) 3(5) 0.5 MTP 4N50 1(1) 2(3) 4(7) 8(14) 10k 4700pF 470pF 150k100 pF 18k 4.7k 0.01 100 1.0k

115 Vac

4.7W MDR 202 250 56k 4.7k 3300 pF 1N4935 1N4935 ++ 68 1N4937 1N4937 680pF 2.7k 1000 1000 2200 1000 5.0V/4.0A 5.0V RTN 12V/0.3A -12V/0.3A MUR110 MBR1635 Osc 7(12) Comp/Latch Vref 1.0mA R 1.0V +12V RTN- TEST CONDITIONS RESULTS Line Regulation: 5.0V =50mV or ±0.5% ±12V =24mV or ±0.1% Load Regulation: 5.0V Vin=115Vac, Iout =1.0A to 4.0A =300mV or ±3.0% ±12V Vin=115Vac,Iout=100mA to 300mA =60mV or ±0.25% Output Ripple: 5.0V 40mVp-p ±12V 80 Vp-p Efficiency Vin=115Vac 70% Vin=95 to 130 Vac Vin=115Vac Primary : 45 Turns #26 AWG Secondary ±12V :

9 Turns #30 AWG (2 strands )

Bifiliar Wound. Secondary 5.0V :

4 Turns (six strands) #26

Hexfiliar Wound. Secondary Feedback :

10 Turns #30 AWG (2 strands)

Bifiliar Wound. Core : Ferroxcube EC35-3C8 Bobbin : Ferroxcube EC35PCB1 Gap : ≅@0.10” for a primary induc- tance of 1.0mH. L1: 15µH at 5.0A, Coilcraft 27156. L2,L3: 25µH at 1.0A, Coilcraft 27157.

Undervoltage Lockout(contd.) Figure 34-33 Watt Off-Line Flyback Converter with Soft-Start and Primary Power Limiting Coilcraft 11-464-16, 0.025” gap in each leg Bobbin : Coilcraft 37-573 Windings: Primary, 2 each: 75 turns #26 Awg Bifilar wound Feedback: 15 turns #26 Awg Secondary , 5.0V: 6 turns #22 Awg Bifilar wound Secondary , 5.0V: 14 turns #24 Awg Bifilar wound Coilcraft Z7156. 15 µF @ 5.0A L2,L3 Coilcraft Z7157. 25µF @ 1.0A Optional R.F .I Filter Cold T 1.0A 3 each

0.0047 UL / CSA

200V 7.5K 25K 2.2M 0.01 33K 22K Pout Pout 5.0K 0.01 6.8K 27K 2.7K 1.5K 8.2K 11K 654 0.001 47K E CVcc Comp PJ34060 Vref C T R TD T Gnd 200 47 MPS MPS A05 A55 10/25V 1.0 100 /10V 2200 /10V 1000 /25V 1000 /25V /35V /35V Common 5.0V /3.0A 12V /0.75A 12V /0.75A 1N4934 47 / 25V MJE 13005 TEST CONDITIONS RESULTS Line Regulation 5.0V Vin=95 to 135 Vac, Io=3.0A 20mV 0.40% Line Regulation± 12V Vin=95 to 135 Vac, Io=±0.75A 52mV 0.26% Line Regulation 5.0V Vin=115 Vac, Io=1.0 to 4.0A 476mV 9.5% Line Regulation± 12V Vin=115 Vac, Io=±0.4 to ±0.9A 300mV 2.5% Vin=115 Vac, Io(5.0V)=3.0A Io(±12V)=±0.75A Efficiency 74%

PIN NO. FUNCTION DESCRIPTION

1 Compensation This pin is the Error Amplifier output and is made available

2 Voltage Feedback

This is the inverting input of the Error Amplifier. It is normally connected to the switching power supply output through a resistor divider.

3 Current Sense

A voltage proportional to inductor current is connected to this input. The PWM uses this information to terminate the output switch conduction.

4 R T/CT

The Oscillator Frequency and maximum Output duty are programmed by connecting resistor RT to Vref and capacitor C T to ground operation to 500kHz is possible 5G n d This pin is the combined control circuitry and power ground (8-pin package only). 6O u t p u t This output directly drives the gate of a power MOSFET. Peak current up to 1.0A are sourced and sunk by this pin. 7 Vcc This pin is the positive supply of the control IC. 8V r e f This pin is the reference output. It provides charging current for capacitor CT through resistor RT. 1 4 DIP-8 SOP-8 PIN : 1. Compensation 2. Voltage feedback 3. Current Sense 4. R T / CT 5. Gnd 6. Output 7. V CC 8. Vref

Current Sense Comparator and PWM Latch The TS3842B operate as a current mode controller, whereby output switch conduction is initiated by the oscillator and terminated when the peak inductor current reaches the threshold level estab- lished by the Error Amplifier Output/Compensation (Pin 1). Thus the error signal controls the peak inductor current on a cycle-by-cycle basis. The Current Sense Comparator PWM Latch configu- ration used ensures that only a single appears at the Output during any given oscillator cycle. The inductor current is converted to a voltage by inserting the ground referenced sense resistor R S in series with the source of output switch Q1. This voltage is monitored by the Current Sense Input (Pin 3) and compared to a level derived from the Error Amp Output. The peak inductor current under normal operating conditions is controlled by the voltage at pin 1 where: I PK = [V(Pin 1) - 1.4V] / 3RS Abnormal operating conditions occur when the power supply output is overloaded or if output voltage sensing is lost. Under these conditions, the Current Sense Comparator threshold will be internally clamped to 1.0V. Therefore the maximum peak switch current is: IPK (MAX) = 1.0V / RS When designing a high power switching regulator it becomes desirable to reduce the internal clamp voltage in order to keep the power dissipation of RS to a reasonable level. A simple method to adjust this voltage is shown in Figure 22. The two external diodes are used to compensate the internal diodes yielding a constant clamp voltage over temperature. Erratic operation due to noise pickup can result if there is an excessive reduction of the I PK (max) clamp voltage. A narrow spike on the leading edge of the current waveform can usually be observed and may cause the power supply to exhibit an instability when the output is lightly loaded. This spike is due to the power transformer interwinding capacitance and output rectifier recovery time. The addition of an RC filter on the Current Sense Input with a time constant that approximates the spike duration will usually eliminate the instability: refer to Figure 26. R f(MIN) = [3x(1.0V)+1.4V] / 0.5mA = 8800Ω the load is removed, or at the beginning of a soft-start interval (Figure 23,24). The Error Amp minimum feedback resistance is limited by the amplifier’s source current (0.5mA) and the re- quired output voltage (V OH ) to reach the comparator’s 1.0V clamp level:

R J F X 45 A B P DK C G M O DIP-8 A B J G D K L M C MIN MAX MIN MAX A 4.80 5.00 0.189 0.196 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G K 0.10 0.25 0.004 0.009 M 0 °7 °0 °7 ° P 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019 1.27BSC 0.05BSC SYMBOLS MILLIMETERS INCHES MIN MAX MIN MAX A 9.07 9.32 0.357 0.367 B 6.22 6.48 0.245 0.255 C 3.18 4.43 0.125 0.135 D 0.35 0.55 0.019 0.020 G J 0.29 0.31 0.011 0.012 K 3.25 3.35 0.128 0.132 L 7.75 8.00 0.305 0.315 M- 1 0 ° -1 0 ° 2.54BSC 0.10BSC SYMBOLS MILLIMETERS INCHES