TS3005

TS3005 TOUCHSTONE | Alldatasheet

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© 2013 Touchstone Semiconductor, Inc. All rights reserved.

FEATURES

 Ultra Low Supply Current: 1.35μA at 49Hz  Supply Voltage Operation: 1.55V to 5.25V  Single Resistor Sets FOUT at 50% Duty Cycle  3-pin User-Programmable FOUT Period:  1.7ms ≤ tFOUT ≤ 33hrs  FOUT Period Accuracy: 3%  FOUT Period Drift: 0.02%/ºC  Single Resistor Sets Output Frequency  Separate PWM Control and Buffered Output  FOUT/PWMOUT Output Driver Resistance: 160Ω

APPLICATIONS

Portable and Battery-Powered Equipment Low-Parts-Count Nanopower Oscillator Compact Micropower Replacement for Crystal and Ceramic Oscillators Micropower Pulse-width Modulation Control Micropower Pulse-position Modulation Control Micropower Clock Generation Micropower Sequential Timing

DESCRIPTION

The TS3005 is a single -supply, second -generation Touchstone Semi oscillator/timer fully specified to operate at a supply voltage range of 1.55V to 5.25V while consuming less than 1.5 μA(max) supply current. Requiring only a resistor to set the base output fr equency ( or output period) at 49 Hz (or 20.5ms) with a 50% duty cycle, the TS3005 timer/oscillator is compact, easy-to-use, and versatile. Optimized for ultra-long life, low frequency, battery-powered/portable applications, the TS3005 joins the TS3001, TS3002, TS3003, TS3004, and TS3006 in Touchstone’s CMOS timer family in its “NanoWatt Analog™” series of high -performance analog integrated circuits. The TS3005 output period can be user -adjusted from 1.7ms to 33hrs without additional components. In addition, the TS3005 represents a 25% reduction in pcb area and a factor-of-10 lower power consumption over other CMOS -based integrated circuit oscillators/timers. When compared against industry - standard 555 -timer-based products, the TS3005 offers up to 84% reduction in pcb area and over three orders of magnitude lower power consumption. The TS3005 is fully specified over the -40°C to +85°C temperature range and is available in a low -profile, 10-pin 3x3mm TDFN package with an exposed back-side paddle. A 1.55V to 5.25V, 1.35µA, 1.7ms to 33hrs Silicon Timer TYPICAL APPLICATION CIRCUIT TS3005, 5 Weeks and 5 Days Counter Circuit The Touchstone Semiconductor logo and “NanoWatt Analog” are registered trademarks of Touchstone Semiconductor, Incorporated.

Continuous Power Dissipation (TA = +70°C) 10-Pin TDFN (Derate at 13.48mW/°C above +70°C) ... 1078mW Electrical and thermal stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not implied. Exposure to any absolute maximum rating conditions for extended periods may affect device reliability and lifetime. PACKAGE/ORDERING INFORMATION ORDER NUMBER PART MARKING CARRIER QUANTITY TS3005ITD1033TP 3005I Tape & Reel ----- TS3005ITD1033T Tape & Reel 3000 Lead-free Program: Touchstone Semiconductor supplies only lead-free packaging. Consult Touchstone Semiconductor for products specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

VDD = 3V, VPWM_CNTRL= VDD, RSET = 4.32MΩ, RLOAD(FOUT) = Open Circuit, CLOAD(FOUT) = 0pF, CLOAD(PWM) = 0pF, CPWM = 47pF, FDIV2:0 = 000 unless otherwise noted. Values are at TA = 25°C unless otherwise noted. See Note 1. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage VDD 1.55 5.25 V Supply Current IDD CPWM = VDD 1.35 1.5 µA -40°C ≤ TA ≤ 85°C 1.9 1.47 1.7 FOUT Period Line Regulation ΔtFOUT/V 1.55V ≤ VDD ≤ 5.25V 0.17 %/V FOUT Duty cycle 49 51 % FOUT Period Temperature Coefficient ΔtFOUT/ΔT 0.02 %/°C PWMOUT Duty Cycle DC(PWMOUT) 0.08 0.12 % VPWM_CNTRL= 0V 0.02 0.03 PWMOUT Duty Cycle Line Regulation ΔDC(PWMOUT)/V 1.55V < VDD < 5.25V, FDIV2:0 = 000 -3 % CPWM Sourcing Current ICPWM FDIV2:0 = 000, 001 930 1050 nA -40°C ≤ TA ≤ 85°C 810 1150 FDIV2:0 000, 001 97 nA UVLO Hysteresis VUVLO (VDD=1.55V) – (VDD_SHUTDOWN VOLTAGE) 150 250 mV FOUT, PWMOUT Rise Time tRISE See Note 2, CL = 15pF 10 ns FOUT, PWMOUT Fall Time tFALL See Note 2, CL = 15pF 10 ns FOUT Jitter See Note 3 0.001 % RSET Pin Voltage V(RSET) 0.3 V FDIV Input Current IFDIV 10 nA -40°C ≤ TA ≤ 85°C 20 Maximum Oscillator Frequency Fosc RSET= 360K 586 Hz High Level Output Voltage, FOUT and PWMOUT VDD - VOH IOH = 1mA 160 mV Low Level Output Voltage, FOUT and PWMOUT VOL IOL = 1mA 140 mV Dead Time TDT FOUT edge falling and PWMOUT edge rising 106 ns Note 1: All devices are 100% production tested at TA = +25°C and are guaranteed by characterization for TA = TMIN to TMAX, as specified. Note 2: Output rise and fall times are measured between the 10% and 90% of the VDD power-supply voltage levels. The specification is based on lab bench characterization and is not tested in production. Note 3: Timing jitter is the ratio of the peak-to-peak variation of the period to the mean of the period. The specification is based on lab bench characterization and is not tested in production.

SUPPLY CURRENT - µA 10.4 20.8 Supply Current vs FOUT Period 0 31.2 41.6 52 SUPPLY VOLTAGE - Volt PERIOD - ms 2.29 3.03 20.4 20.3 20.7 FOUT Period vs Supply Voltage 1.55 3.77 20.5 20.6 4.51 CLOAD- pF SUPPLY CURRENT - µA 10 20 Supply Current vs CLOAD(FOUT) 0 30 5.25 TEMPERATURE - ºC SUPPLY CURRENT - µA 1.3 1.1 Supply Current vs Temperature 1.4 1.5 1.2 -15 10 -40 35 60 85 SUPPLY VOLTAGE - Volt START-UP TIME - ms Start-up Time vs Supply Voltage TEMPERATURE - ºC PERIOD - ms -15 10 19.5 FOUT Period vs Temperature -40 35 20.5 60 85 21.5 TYPICAL PERFORMANCE CHARACTERISTICS VDD = 3V, VPWM_CNTRL= VDD, RSET = 4.32MΩ, RLOAD(FOUT) = Open Circuit, CLOAD(FOUT) = 0pF, CLOAD(PWM) = 0pF, CPWM = VDD, FDIV2:0 = 000 unless otherwise noted. Values are at TA = 25°C unless otherwise noted. 20.8

TYPICAL PERFORMANCE CHARACTERISTICS VDD = 3V, VPWM_CNTRL= VDD, RSET = 4.32MΩ, RLOAD(FOUT) = Open Circuit, CLOAD(FOUT) = 0pF, CLOAD(PWM) = 0pF, CPWM = VDD, FDIV2:0 = 000 unless otherwise noted. Values are at TA = 25°C unless otherwise noted. RSET - MΩ PERIOD - ms 2 4 Period vs RSET 0 6 8 10 PERCENT OF UNITS - % SUPPLY CURRENT - µA Supply Current Distribution 1.26 10% 15% 20% 25% 30% 35% 1.3 1.34 1.38 FOUT and PWMOUT VDD = 3V, CLOAD = 15pF, VPWM_CNTRL= VDD, CPWM = 10nF 5ms/DIV FOUT 2V/DIV PWMOUT 2V/DIV FOUT and PWMOUT VDD = 5V, CLOAD = 15pF, VPWM_CNTRL= VDD, CPWM = 10nF 5ms/DIV FOUT 2V/DIV PWMOUT 2V/DIV FOUT VDD = 3V, CLOAD = 15pF 5ms/DIV FOUT VDD = 5V, CLOAD = 15pF 5ms/DIV FOUT 1V/DIV FOUT 1V/DIV

1 FOUT

Fixed Frequency Output. A push -pull output stage with an output resistance of 160 Ω. FOUT pin swings from GND to VDD. For lowest power operation, capacitance loads should be minimized and resistive loads should be maximized. 2,3,4 FDIV2:0 Frequency Divider Input. Various combinations of these inputs will change the FOUT frequency for a fixed value of RSET. Refer to Table 1.

5 PWMOUT

Pulse-width Modulated Output. A push-pull output stage with an output resistance of 160 Ω, the PWMOUT pin is wired anti-phase with respect to FOUT and swings from GND to VDD. For lowest power operation, capacitance loads should be minimized and resistive loads should be maximized.

6 PWM_CNTRL

PWM Output Pulse Control Pin. Applying a voltage between GND and V RSET will reduce the duty cycle of the PWMOUT output that is set by the capacitor connected to the CPWM pin. Connect PWM_CNTRL to VDD for fixed PWM OUT output pulse time (determined only by capacitor at CPWM). 7 GND Ground. Connect this pin to the system’s analog ground plane.

8 CPWM

PWMOUT Pulse Width Programming Capacitance Input. A target capacitance connected from this pin to GND sets the duty cycle of the PMW output . Minimize any stray capacitance on this pin. The voltage on this pin will swing from GND to VRSET. Connect CPWM to VDD to disable PWM function (saves PWM current).

9 VDD

Power Supply Voltage Input. The supply voltage range is 1.55V ≤ VDD ≤ 5.25V. Bypass this pin with a 0.1uF ceramic coupling capacitor in close proximity to the TS3005.

10 RSET

FOUT Programming Resistor Input. A 4.32MOhm resistor connected from this pin to ground sets the T3005 ’s internal oscillator’s output period to 20ms (49 Hz). For opti mal performance, the composition of the RSET resistor shall be consistent with a tolerance of 1% or lower. The RSET pin voltage is approximately 0.3V.

The TS3005 is a user-programmable oscillator where the period of the square wave at its FOUT terminal is generated by an external resistor connected to the RSET pin. The output period is given by: t O T (s = 8 V2 0 x RS T x 512 1.08 11 Equation 1. FOUT Frequency Calculation where FDIV2:0 = 0 to 7 RSET (MΩ) tFOUT 0.360 59.67min 1 1.09hrs 2.49 6.87hrs 4.32 11.93hrs 6.81 18.81hrs 9.76 26.93hrs 12 33.1hrs Table 2: tFOUT vs RSET for FDIV2:0 = 111(7) FDIV 2:0 tFOUT(s) FOUT (Hz) ICPWM (A) 000 1.7ms-56.88ms 586-17.578 1µ 001 13.65ms-455.16ms 73.25-2.197 1µ 010 109.17ms-3.64 9.16-0.2746 100n 011 877.19ms-29.15 1.14-0.0343 100n 100 7.01-233.1 0.143-0.00429 100n 101 55.94-31.09min 0.0178-0.536mHz 100n 110 7.49min-4.146hrs 0.0022-0.0670mHz 100n 111 59.67min-33.1hrs 0.279mHz-8.381µHz 100n Table 1: FOUT and PWMOUT Frequency Range per FDIV2:0 Combination

With an RSET = 4.32MΩ and FDIV2:0=111, the FOUT period is approximately 715.88 minutes with a 50% duty cycle. As de sign aids, Tables 2 lists TS3004 ’s typical FOUT period for various standard values for RSET and FDIV2:0 = 111(7). The output period can be user-adjusted from 1.7 ms to 33hrs without additional components . Frequency divider inputs FDIV2:0 can be set to a logic state HIGH or LOW in order to set the desired frequency as shown in to Table 1. The TS3005 also provides a separate PWM output signal at its PWMOUT terminal that is anti-phase with respect to FOUT. A dead time of approximately 106ns exists between FOUT and PWMOUT. To adjust the pulse width of the PWMOUT output, a single capacitor can be placed at the CPWM pin. To determine the capacitance need ed for a desired pulse width, the following equation is to be used: C WM( = ulse Width(s x C WM VC WM 300mV Equation 2. CPWM Capacitor Calculation where I CPWM and V CPWM is the current supplied and voltage applied to the CPWM capacitor, respectively. The pulse width is determined based on the period of FOUT and should never be greater than the period at FOUT. Make sure the PWM_CNTRL pin is set to at least 400mV when calculating the pulse wid th of PWMOUT. Note V CPWM is approximately 300mV, which is the RSET voltage. Also note that I CPWM is either 1µA or 100nA. Refer to Table 1. The PWMOUT output pulse width can be adjusted further after selecting a CPWM capacitor This can be achieved by applying a voltage to the PWM_CNTRL pin between V RSET and GND. With a voltage of at least VRSET, the pulse width is set based on E quation 2. For example, with a period of 20.5m s( 49Hz) a 10nF capacitor at the CPWM pin generates a pulse width of approximately 3ms. This can be calculated using equation 2. By reducing the PWM_CNTRL voltage from VRSET 300mV to GND, the pulse width can be reduced further. Note that a s the FOUT frequency increases, the amount of pulse width reduction reduces and vice versa. Furthermore, if the PWMOUT output is half the frequency of the FOUT output, this means your CPWM capacitor is too large and as a result, the pulse width is greater than the FOUT perio d. In this case, u se E quation 2 and reduce the capacitor value to less than the period. Connect CPWM to VDD to disable the PWM function and in turn, save power. Connect PWM_CNTRL to VDD for a fixed PWMOUT output pulse width, which is determined by the CPWM pin capacitor only. APPLICATIONS INFORMATION Minimizing Power Consumption To keep the TS3005’s power consumption low, resistive loads at the FOUT and PWMOUT terminals increase dc power consumption and therefore should be as large as possible. Capacitive loads at the FOUT and PWMO UT terminals increase the TS3005’s transient power consumption and, as well, should be as small as possible. One ch allenge to minimizing the TS3005’s transient power consumption is the probe capacitance of oscilloscopes and frequ ency counter instruments. Most instruments exhibit an input capacitance of 15pF or more. Unless buffered, the increase in transient load current can be as much as 400nA. To minimize capacitive loading, the technique shown in Figure 1 can be used. In this circuit, the principle of series-connected capacitors can be used to reduce the effecti ve capacitive load at the TS3005’s O T and PWMOUT terminals. To determine the optimal value for C EXT once the probe capacitance is known by simply solving for CEXT using the following expression: or example, if the instrument’s input probe capacitance is 15pF and the desired effective load Figure 1: Using an External Capacitor in Series with Probes Reduces Effective Capacitive Load. C T = 1 C OA ( C RO Equation 3:External Capacitor Calculation

5 Weeks and 5 Days Counter Circuit with TS3005

is available via output 1QD. Figure 3. To achieve a divide by two function with the

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630 Alder Drive, Milpitas, CA 95035 TS3005DS r1p0

+1 (408) 215 - 1220 ▪ www.touchstonesemi.com RTFDS PACKAGE OUTLINE DRAWING Information furnished by Touchstone Semiconductor is believed to be accurate and reliable. However, Touchstone Semiconductor does not assume any responsibility for its use nor for any infringements of patents or other rights of third parties that may result from its use , and all information provided by Touchstone Semiconductor and its suppliers is provided on an AS IS basis, WITHOUT WARRANTY OF ANY KIN D. Touchstone Semiconductor reserves the right to change product specifications and product descriptions at any time without any advance notice. No license is granted by implication or otherwise under any patent or patent rights of Touchstone Semiconductor. Touchstone Semiconductor assumes no liability for applications assistance or customer product design. Customers are responsible for thei r products and applications using Touchstone Semiconductor components. To minimize the risk associated with customer pr oducts and applications, customers should provide adequate design and operating safeguards. Trademarks and registered trademarks are the property of t heir respective owners. BOTTOM VIEW 3.00±0.05 3.00±0.05 TOP VIEW Pin 1 DOT BY MARKING NOTE!  All dimensions in mm.  Compliant with JEDEC MO-229 SIDE VIEW 0.25±0.05 0.50 BSC 2.30±0.10 1.60±0.10 CO.35 Dap Size 2.65X1.90 mm 0.40±0.05 0.30Ref 0.75±0.05 0.00±0.05 10-Pin TDFN33 Package Outline Drawing (N.B., Drawings are not to scale)