TS2012 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 30
Technical content
Datasheet sections
- 1 Absolute maximum ratings and operating conditions
- 2 Typical application
- 3 Electrical characteristics
- 3.1 Electrical characteristic tables
- 3.2 Electrical characteristic curves
- 4 Application information
- 4.1 Differential configuration principle
- 4.2 Gain settings
- 4.3 Common mode feedback loop limitations
- 4.4 Low frequency response
- 4.5 Decoupling of the circuit
- 4.6 Wake-up time (t
- 4.7 Shutdown time
- 4.8 Consumption in shutdown mode
- 4.9 Single-ended input configuration
- 4.10 Output filter considerations
- 5 Package information
- 6 Ordering information
- 7 Revision history
Features
■ Operating range from VCC=2.5V to 5.5V ■ Standby mode active low ■ Output power per channel : 1.35W @5V or 0.68W @ 3.6V into 8Ω with 1% THD+N max. ■ Output power per channel : 2.2W @5V into 4Ω with 1% THD+N max. ■ Four gains select : 6, 12, 18, 24 dB ■ Low current consumption ■ PSRR: 70dB typ @ 217Hz with 6dB gain. ■ Fast start-up phase: 1ms ■ Thermal shutdown protection ■ QFN20 4x4mm lead-free package
Applications
■ Cellular phone ■ PDA ■ Flat panel TV
Description
The TS2012 is a stereo fully differential class D power amplifier. Able to drive up to 1.35W into an 8Ω load at 5V per channel. It achieves outstanding efficiency compared to typical class AB audio amps. The device has four different gain settings utilizing two discrete pins: G0 and G1. Pop & click reduction circuitry provides low on/off switch noise while allowing the device to start within 1ms. Two standby pins (active low) allow each channel to be switched off independently. The TS2012 is available in a QFN20 package in 4x4 mm dimension. Gain Select PWM H Bridge LIN + LIN - AV LOUT+ LOUT- CC PVCC PVCC STBY L STBY R Gain Select PWM H BridgeRIN - RIN + ROUT+ ROUT- Oscillator Standby Control 300k 300k 300k 300k AGND PGND PGND 12 13 TS2012IQT - QFN20 (4x4) G1 G0 Lout+ PVCC PGND PVCC Rout+ PGND NC STBYL STBYR AVCC Lin+ Lin- AGND Rin- Lout- NC Rout- Rin+ 67 8 91 0 1617181920 G1 G0 Lout+ PVCC PGND PVCC Rout+ PGND NC STBYL STBYR AVCC Lin+ Lin- AGND Rin- Lout- NC Rout- Rin+ 67 8 91 0 1617181920 Pin connections (top view) Block diagram
1 Absolute maximum ratings and operating conditions
Table 1. Absolute maximum ratings
- All voltage values are measur ed with respect to the ground pin.
- The magnitude of the input signal must never exceed V CC + 0.3V / GND - 0.3V.
- The device is protected in case of over te mperature by a thermal shutdown active @ 150°C.
- Exceeding the power derating curves during a long period will cause abnormal operation.
- Human body model: 100 pF discharged through a 1.5 k Ω resistor between two pins of the device, done for
all couples of pin combinations with other pins floating.
- Machine model: a 200 pF cap is charged to the spec ified voltage, then discharged directly between two
combinations with other pins floating.
Table 2. Operating conditions
- I V oo I ≤ 40mV max with all differential gains except 24dB. For 24dB gain, input decoupling caps are
- Without any signal on V STBY, the device is in standby (internal 300kΩ +/-20% pull-down resistor).
- Minimum current consumption is obtained when V STBY = GND.
- Between G0, G1pins and GND, there is an internal 300kΩ (+/-20%) pull-down resistor. When pins are
2 Typical application
Figure 1. Typical application schematics
4 LC Output Filter 8 LC Output FilterΩ Ω
1 FVCCCs
1 Fμ 1 Fμ
Table 3. External component descriptions CS, CSL, CSR Supply capacitor that provides power supply filtering. Table 4. Pin descriptions
1 G1 Gain select pin (MSB)
2 Lout+ Left channel positive output
3 PVCC Power supply
4 PGND Power ground
5 Lout- Left channel negative output
6 NC No internal connection
7 STBYL Standby pin (active low) for left channel output
8 STBYR Standby pin (active low) for right channel output
9 AVCC Analog supply
10 NC No internal connection
11 Rout- Right channel negative output
12 PGND Power ground
13 PVCC Power supply
14 Rout+ Right channel positive output
15 G0 Gain select pin (LSB)
16 Rin+ Right channel positive differential input
17 Rin- Right channel negative differential input
18 AGND Analog ground
19 Lin- Left channel negative differential input
20 Lin+ Left channel positive differential input
3 Electrical characteristics
3.1 Electrical characteristic tables
Table 5. V CC = +5V, GND = 0V, Vic=2.5V, Tamb = 25°C (unless otherwise specified)
- Dynamic measurements - 20*log(rms(V out)/rms(Vripple)). Vripple is the superimposed sinus signal to VCC @ f = 217Hz.
Table 5. V CC = +5V, GND = 0V, Vic=2.5V, Tamb = 25°C (unless otherwise specified) (continued)
Table 6. V CC = +3.6V, GND = 0V, Vic=1.8V, Tamb = 25°C (unless otherwise specified)
- Dynamic measurements - 20*log(rms(V out)/rms(Vripple)). Vripple is the superimposed sinus signal to VCC @ f = 217Hz.
Table 6. V CC = +3.6V, GND = 0V, Vic=1.8V, Tamb = 25°C (unless otherwise specified) (continued)
Table 7. V CC = +2.5V, GND = 0V, Vic=1.25V, Tamb = 25°C (unless otherwise specified)
3.2 Electrical characteristic curves
- RL+ 15µH or 30µH = pure resistor + very low series resistance inductor
- Filter = LC output filter (1µF+30µH for 4Ω and 0.5µF+60µH for 8Ω) All measurements are done with CSL=CSR=1µF and CS=100nF (see Figure 2), except for the PSRR where CSL,R is removed (see Figure 3).
Figure 2. Test diagram for measurements
- Dynamic measurements - 20*log(rms(V out)/rms(Vripple)). Vripple is the superimposed sinus signal to VCC @ f = 217Hz.
15 H or 30 Hμμ
Figure 3. Test diagram for PSRR measurements
Table 8. Index of graphics
4 Application information
4.1 Differential configuration principle
topology, the output is four times higher for the same power supply voltage.
- High PSRR (power supply rejection ratio)
- High common mode noise rejection
- Virtually zero pop without additional circuitry, giving a faster start-up time compared with conventional single-ended input amplifiers
- Easier interfacing with differential output audio DAC
- No input coupling capacitors required thanks to common mode feedback loop
4.2 Gain settings
the logic level of the G0 and G1 pins, as shown in Table 9.
4.3 Common mode feedback loop limitations
CC/2 for any DC common mode bias input voltage. common mode feedback loop can fulfil its role only within the defined range. Table 9. Gain settings with G0 and G1 pins
4.4 Low frequency response
If a low frequency bandwidth limitation is required, it is possible to use input coupling capacitors. In the low frequency region, the input coupling capacitor Cin starts to have an effect. Cin forms, with the input impedance Zin, a first order high-pass filter with a -3dB cut- off frequency (see Table 5 to Table 7): So, for a desired cut-off frequency FCL Cin is calculated as follows: with FCL in Hz, Zin in Ω and Cin in F . The input impedance Zin is for the whole power supply voltage range, typically 30kΩ . There is also a tolerance around the typical value (see Table 5 to Table 7). Y ou can also calculate the tolerance of the FCL:
4.5 Decoupling of the circuit
Power supply capacitors, referred to as CS,CSL,CSR are needed to correctly bypass the TS2012. The TS2012 has a typical switching frequency of 280kHz and output fall and rise time about 5ns. Due to these very fast transients, careful decoupling is mandatory. A 1µF ceramic capacitor between each PVCC and PGND and also between AVCC and AGND is enough, but they must be located very close to the TS2012 in order to avoid any extra parasitic inductance created by a long track wire. Parasitic loop inductance, in relation with di/dt, introduces overvoltage that decreases the global efficiency of the device and may cause, if this parasitic inductance is too high, a TS2012 breakdown. In addition, even if a ceramic capacitor has an adequate high frequency ESR value, its current capability is also important. A 0603 size is a good compromise, particularly when a 4Ω load is used. Another important parameter is the rated voltage of the capacitor. A 1µF/6.3V capacitor used at 5V, loses about 50% of its value. With a power supply voltage of 5V, the decoupling value, instead of 1µF , could be reduced to 0.5µF . As C S has particular influence on the THD+N in the medium to high frequency region, this capacitor variation becomes decisive. In addition, less decoupling means higher overshoots which can be problematic if they reach the power supply AMR value (6V). FCL Cin FCLmax 1.103 F CL⋅= FCLmin 0.915 F CL⋅=
4.6 Wake-up time (t wu)
When the standby is released to set the device ON, there is a delay of 1ms typically. The TS2012 has an internal digital delay that mutes the outputs and releases them after this time in order to avoid any pop noise. Note: The gain increases smoothly (see Figure 44) from the mute to the gain selected by the G1 and G0 pin (Section 4.2).
4.7 Shutdown time
When the standby command is set, the time required to set the output stage considered into high impedance and to put the internal circuitry in shutdown mode, is typically 1ms. This time is used to decrease the gain and avoid any pop noise during shutdown. Note: The gain decreases smoothly until the outputs are muted (see Figure 44).
4.8 Consumption in shutdown mode
Between the shutdown pin and GND there is an internal 300kΩ (+-/20%) resistor. This resistor forces the TS2012 to be in shutdown when the shutdown input is left floating. However, this resistor also introduces additional shutdown power consumption if the shutdown pin voltage is not 0V. With a 0.4V shutdown voltage pin for example, you must add 0.4V/300kΩ=1.3µA in typical (0.4V/240kΩ=1.66µA in maximum for each shutdown pin) to the standby current specified in Table 5 to Table 7. Of course, this current will be provided by the external control device for standby pins.
4.9 Single-ended input configuration
It is possible to use the TS2012 in a single-ended input configuration. However, input coupling capacitors are mandatory in this configuration. The schematic diagram in Figure 45 shows a typical single-ended input application.
Figure 45. Typical application for single-ended input configuration
4.10 Output filter considerations
different for each configuration, it is difficult to provide a one-size-fits-all solution.
- Reduce, as much as possible, the distance between the TS2012 output pins and the speaker terminals.
- Use a ground plane for “shielding” sensitive wires.
- Place, as close as possible to the TS2012 and in series with each output, a ferrite bead with a rated current of minimum 2.5A and impedance greater than 50Ω at frequencies above 30MHz. If, after testing, these ferrite beads are not necessary, replace them by a short-circuit.
- Allow extra footprint to place, if necessary, a capacitor to short perturbations to ground (see Figure 46). VCCCsL TS2012 Gain Select Gain Select Standby Control PWM H Bridge PWM H Bridge Oscillator LIN + LIN - RIN - RIN + STBY L STBY R AVAGND PGND PGND LOUT+ LOUT- CC PVCC PVCC ROUT+ ROUT- Left speaker Right speaker Cin Cin Left Input Cin Cin Right Input Standby Control VCC CsRVCCCs 100nF Gain Select Control
Figure 46. Ferrite chip bead placement in Figure 1 on page 5 as close as possible to the TS2012.
5 Package information
Figure 47. QFN20 package mechanical drawing
Figure 48. QFN20 package footprint copper area can be electrically connected to pin 4, 12, 18 (PGND, AGND) or left floating. Table 10. QFN20 package mechanical data
6 Ordering information
7 Revision history
Table 11. Order code Table 12. Document revision history 17-Dec-2007 1 First release.