TS2007FC STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 28
Technical content
Datasheet sections
- 1 Absolute maximum ratings and operating conditions
- 2 Application information
- 3 Electrical characteristics
- 3.1 Electrical characteristics tables
- 3.2 Electrical characteristic curves
- 4 Application information
- 4.1 Differential configuration principle
- 4.2 Gain settings
- 4.3 Common mode feedback loop limitations
- 4.4 Low frequency response
- 4.5 Circuit decoupling
- 4.6 Wake-up time (t
- 4.7 Shutdown time
- 4.8 Consumption in shutdown mode
- 4.9 Single-ended input configuration
- 4.10 Output filter considerations
- 4.11 Short-circuit protection
- 4.12 Thermal shutdown
- 5 Package information
- 6 Ordering information
- 7 Revision history
Features
■ Operates from VCC=2.4 V to 5.5 V ■ Standby mode active low ■ Output power: 1.4 W at 5 V or 0.5 W at 3.0 V into 8 Ω with 1% THD+N max. ■ Output power: 2.3 W at 5V or 0.75 W at 3.0 V into 4 Ω with 1% THD+N max. ■ Two fixed gain selects: 6 dB or 12 dB ■ Low current consumption ■ Efficiency: 86% typical ■ Signal-to-noise ratio: 90 dB typical ■ PSRR: 68 dB typical at 217 Hz with 6 dB gain ■ PWM base frequency: 280 kHz ■ Low pop and click noise ■ Thermal shutdown protection ■ Output short-circuit protection ■ Flip-chip lead-free 9-bump package with back coating in option.
Applications
■ Cellular phone ■ PDA ■ Notebook PC
Description
The TS2007FC is a class D power audio amplifier. Able to drive up to 1.4 W into an 8 Ω load at 5 V, it achieves better efficiency than typical class AB audio power amplifiers. This device can switch between two gain settings, 6 dB or 12 dB via a logic signal on the gain select pin. Pop and click reduction circuitry provides low on/off switch noise and allows the device to start within 1 ms typically. A standby mode function (active low) keeps the current consumption down to 1 μA typical. The TS2007FC is available in a 9-bump flip-chip lead-free package. TS2007EIJT - 9-bump flip-chip Pinout (top view) OUT- GND OUT+ GS IN+ VCC STBY VCC IN-
1 Absolute maximum ratings and operating conditions
Table 1. Absolute maximum ratings (AMR)
- All voltage values are measur ed with respect to the ground pin.
- The magnitude of input signal must never exceed V CC + 0.3 V / GND - 0.3 V
- The device is protected in case of over te mperature by a thermal shutdown active @ 150° C.
- Exceeding the power derating curves during a l ong period provokes abnormal operating conditions.
- Human body model: 100 pF discharged through a 1.5 k Ω resistor between two pins of the device, done for
all couples of pin combinations with other pins floating.
- Machine model: a 200 pF cap is charged to the spec ified voltage, then discharged directly between two
combinations with other pins floating.
- Implemented short-circuit protec tion protects the amplifier against damage by short-circuit between
positive and negative outputs and between outputs and ground.
Table 2. Operating conditions
- |V oo| ≤ 35 mV max with both differential gains.
- Without any signal on V STBY, the device is in standby (internal 300 kΩ pull down resistor).
- Minimum current consumption is obtained when V STBY = GND.
- Without any signal on GS pin, the device is in a 6 dB gain configuration (internal 300 kΩ pull up resistor).
- With mounted on 4-layer PCB.
2 Application information
Figure 1. Typical application Note: See Section 4.10: Output filter considerations on page 23. Table 3. External component description Cs Supply capacitor that provides power supply filtering. Table 4. Pin description
3 Electrical characteristics
3.1 Electrical characteristics tables
Table 5. V CC = +5 V, GND = 0 V, Vic = 2.5 V, Tamb = 25°C (unless otherwise specified)
20 Hz < F< 20 kHz, Gain = 6 dB, ΔVICM = 200 mVpp
- Standby mode is active when V STBY is tied to GND.
- Dynamic measurement - 20*log(rms(V out)/rms(Vripple)). Vripple is the superimposed sinus signal to VCC @ F =217 Hz.
- Independent of gain configuration (6 or 12 dB) and between IN+ or IN- and GND.
Table 6. V CC = +4.2 V, GND = 0 V, Vic = 2.1 V, Tamb = 25°C (unless otherwise specified)
- Standby mode is active when V STBY is tied to GND.
- Dynamic measurements - 20*log(rms(V out)/rms(Vripple)). Vripple is the superimposed sinus signal to VCC @ F = 217 Hz.
- Independent of Gain configuration (6 or 12 dB) and between IN+ or IN- and GND.
Table 7. V CC = +3.6 V, GND = 0 V, Vic = 1.8 V, Tamb = 25°C (unless otherwise specified)
- Standby mode is active when V STBY is tied to GND.
- Dynamic measurements - 20*log(rms(V out)/rms(Vripple)). Vripple is the superimposed sinus signal to VCC @ F= 217 Hz.
- Independent of gain configuration (6 or 12 dB) and between IN+ or IN- and GND.
Table 8. V CC = +3.0 V, GND = 0 V, Vic = 1.5 V, Tamb = 25°C (unless otherwise specified)
- Standby mode is active when V STBY is tied to GND.
- Dynamic measurements - 20*log(rms(V out)/rms(Vripple)). Vripple is the superimposed sinus signal to VCC @ F = 217 Hz.
- Independent of Gain configuration (6 or 12 dB) and between IN+ or IN- and GND.
Table 9. V CC = +2.7 V, GND = 0 V, Vic = 1.35 V, Tamb = 25°C (unless otherwise specified)
- Standby mode is active when V STBY is tied to GND.
- Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the superimposed sinus signal to VCC @ F= 217 Hz.
- Independent of Gain configuration (6 or 12 dB) and between IN+ or IN- and GND.
3.2 Electrical characteristic curves
- RL+ 15 µH or 30 µH = pure resistor + very low series resistance inductor
- Filter = LC output filter (1 µF+ 30 µH for 4 Ω and 0.5 µF+15 µH for 8 Ω) All measurements are done with CS1 = 1 µF and CS2 = 100 nF (Figure 2), except for the PSRR where CS1 is removed (Figure 3).
Figure 2. Test diagram for measurements Figure 3. Test diagram for PSRR measurements
15 H or 30 Hμμ
For quick reference, a list of the graphs shown in this section is provided in Table 10. Table 10. Index of graphs
4 Application information
4.1 Differential configuration principle
topology, the output is four times higher for the same power supply voltage. A fully-differential amplifier has the following advantages.
- High PSRR (power supply rejection ratio).
- High CMRR (common mode noise rejection).
- Virtually zero pop without additional circuitry, giving a faster start-up time than conventional single-ended input amplifiers.
- Easy interfacing with differential output audio DACs.
- No input coupling capacitors required since there is a common mode feedback loop.
4.2 Gain settings
on the logic level of the GS pin. the gain is 6 dB. In standby mode, this internal resistor is disconnected (HiZ input).
4.3 Common mode feedback loop limitations
CC/2 for any DC common mode bias input voltage. mode feedback loop can fulfill its role only within the defined range.
4.4 Low frequency response
capacitors. In the low frequency region, the input coupling capacitor Cin has a greater effect. frequency (see Table 5 to Table 9). Table 11. GS pin gains
So, for a desired cut-off frequency FCL we can calculate Cin: with FCL in Hz, Zin in Ω and Cin in F . The input impedance Zin is for the whole power supply voltage range, typically 75 kΩ. There is also a tolerance around the typical value (see Table 5 to Table 9). With regard to the tolerance, you can also calculate tolerance of the FCL:
4.5 Circuit decoupling
A power supply capacitor, referred to as CS, is needed to correctly bypass the TS2007. The TS2007 has a typical switching frequency of 280 kHz and output fall and rise time of less than or equal to 5 ns. Due to these very fast transients, careful decoupling is mandatory. A 1 µF ceramic capacitor is enough, but it must be located very close to the TS2007 in order to avoid any extra parasitic inductance created by a long track wire. Parasitic loop inductance, in relation with di/dt, introduces overvoltage that decreases the global efficiency of the device and may cause, if this parasitic inductance is too high, a TS2007 breakdown. For filtering low frequency noise signals on the power line, it is recommended to use a capacitor C S of at least 1 µF . In addition, even if a ceramic capacitor has an adequate high frequency ESR (equivalent series resistance) value, its current capability is also important. A 0603 size is a good compromise, particularly when a 4 Ω load is used. Another important parameter is the rated voltage of the capacitor. A 1 µF/6.3 V capacitor used at 5 V, loses about 50% of its value: with a power supply voltage of 5 V, the decoupling value, instead of 1 µF , could be reduced to 0.5 µF . As C S has particular influence on the THD+N in the medium to high frequency region, this capacitor variation becomes decisive. In addition, less decoupling means higher overshoots which can be problematic if they reach the power supply AMR value (6 V).
4.6 Wake-up time (t wu)
When the standby is released to set the device ON, there is a wait of 1 ms typically. The TS2007 has an internal digital delay that mutes the outputs and releases them after this time in order to avoid any pop noise. Note: The gain increases smoothly (see Figure 42 and Figure 43) from the mute to the gain selected by the GS pin (Section 4.2). FCL Cin FCLmax 1.103 F CL⋅= FCLmin 0.915 F CL⋅=
4.7 Shutdown time
into high impedance and to put the internal circuitry in shutdown mode, is typically 1 ms. This time is used to decrease the gain and avoid any pop noise during shutdown. Note: The gain decreases smoothly until the outputs are muted (see Figure 42 and Figure 43).
4.8 Consumption in shutdown mode
the TS2007 to be in shutdown when the shutdown input is left floating. drives the standby pin of the amplifier. the shutdown current specified in Table 5 to Table 9.
4.9 Single-ended input configuration
shows a typical single-ended input application. Figure 44. Typical application for single-ended input configuration
4.10 Output filter considerations
configuration, it is difficult to provide a one-size-fits-all solution. However, to decrease the probability of EMI issues, there are several simple rules to follow.
- Reduce, as much as possible, the distance between the TS2007 output pins and the speaker terminals.
- Use a ground plane for shielding sensitive wires.
- Place, as close as possible to the TS2007 and in series with each output, a ferrite bead with a rated current of minimum 2.5 A and impedance greater than 50Ω at frequencies above 30 MHz.
- Allow extra footprint to place, if necessary, a capacitor to short perturbations to ground (Figure 45).
Figure 45. Ferrite chip bead placement page 24, that consists of L1, C1, L2 and C2 as close as possible to the TS2007 outputs. response of the output filter and compensates this limitation.
Figure 46. LC output filter with RC network
4.11 Short-circuit protection
from being damaged if there are fault conditions on the amplifier outputs. GND), the short-circuit protection detects this situation and puts the amplifier into standby.
4.12 Thermal shutdown
Table 12. Example of component choice
5 Package information
Figure 47. 9-bump flip-chip pinout (top view) Figure 48. Marking (top view)
3 OUT- GND OUT+
- Logo: ST
- First two digits for part number: K7
- Third digit for assembly plant: X
- Three digit date code: YWW
- Dot indicates pin A1
- E symbol for lead free K7 X YWW E K7 X YWW E
Figure 49. 9-bump flip-chip package mechanical data
- Die size: 1.57 mm x 1.57 mm ±30 µm
- Die height (including bumps): 600 µm
- Bump diameter: 315 µm ±50 µm
- Bump diameter before reflow: 300 µm ±10 µm
- Bump height: 250 µm ±40 µm
- Die height: 350 µm ±20 µm
- Pitch: 500 µm ±50 µm
- Back coating layer height*: 40 µm ±10 µm
- Coplanarity: 50 µm max * Optional 600µm 40µm 600µm 40µm 1.57 mm 1.57 mm 0.5mm 0.5mm ∅ 0.25mm 1.57 mm 1.57 mm 0.5mm 0.5mm ∅ 0.25mm
6 Ordering information
7 Revision history
Table 13. Order codes Table 14. Document revision history 19-Aug-2008 1 Initial release.