TS2007 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 29
Technical content
Datasheet sections
- 1 Absolute maximum ratings and operating conditions
- 2 Typical application
- 3 Electrical characteristics
- 3.1 Electrical characteristic tables
- 3.2 Electrical characteristic curves
- 4 Application information
- 4.1 Differential configuration principle
- 4.2 Gain settings
- 4.3 Common mode feedback loop limitations
- 4.4 Low frequency response
- 4.5 Decoupling of the circuit
- 4.6 Wake-up time (t
- 4.7 Shutdown time
- 4.8 Consumption in shutdown mode
- 4.9 Single-ended input configuration
- 4.10 Output filter considerations
- 5 Package information
- 6 Ordering information
- 7 Revision history
Features
■ Operating range from VCC=2.4V to 5.5V ■ Standby mode active low ■ Output power: 1.4W @5V or 0.45W @ 3.0V into 8Ω with 1% THD+N max. ■ Output power: 2.3W @5V or 0.75W @ 3.0V into 4Ω with 1% THD+N max. ■ Fixed gain select: 6dB or 12dB ■ Low current consumption ■ Efficiency: 88% typ. ■ Signal-to-noise ratio: 94dB typ. ■ PSRR: 63dB typ @ 217Hz with 6dB gain. ■ PWM base frequency: 280kHz ■ Low pop & click noise ■ Thermal shutdown protection ■ DFN8 3x3mm package
Applications
■ Cellular phone ■ PDA ■ Notebook PC
Description
The TS2007 is a class D power audio amplifier. Able to drive up to 1.4W into an 8 Ω load at 5V, it achieves outstanding efficiency compared to typical class AB audio power amplifier. This device allows to switch between two different gains: 6 or 12dB via a logic signal on the GS pin. A pop & click reduction circuitry provides low on/off switch noise while allowing the device to start within 5ms. A standby function (active low) allows to lower the current consumption down to 10nA typ. The TS2007 is available in DFN8 3x3mm lead- free packages. TS2007IQT - DFN8 TS2007IQT - DFN8
1 Absolute maximum ratings and operating conditions
Table 1. Absolute maximum ratings
- All voltage values are measur ed with respect to the ground pin.
- The magnitude of the input signal must never exceed V CC + 0.3V / GND - 0.3V.
- The device is protected in case of over te mperature by a thermal shutdown active @ 150°C.
- Exceeding the power derating curves during a long period will cause abnormal operation.
Table 2. Operating conditions
- I V oo I ≤ 35mV max with both differential gains.
- Without any signal on V STBY, the device is in standby (internal 300kΩ pull down resistor).
- Minimum current consumption is obtained when V STBY = GND.
- When mounted on 4-layer PCB.
2 Typical application
Figure 1. Typical application schematics Table 3. External component descriptions CS Supply capacitor that provides power supply filtering.
4 LC Output Filter
8 LC Output Filter
Table 4. Pin descriptions
1 STBY Standby pin ( active low )
2 GS Gain select input
3 IN+ Positive differential input
4 IN- Negative differential input
5 OUT - Negative differential output
6 VCC Power supply
7 GND Ground
8 OUT+ Positive differential output
3 Electrical characteristics
3.1 Electrical characteristic tables
Table 5. V CC = +5V, GND = 0V, Vic=2.5V, Tamb = 25°C (unless otherwise specified)
- Standby mode is active when V STBY is tied to GND.
- Dynamic measurements - 20*log(rms(V out)/rms(Vripple)). Vripple is the superimposed sinus signal to VCC @ f = 217Hz.
- Independent of Gain configuration (6 or 12dB) and between IN+ or IN- and GND.
Table 5. V CC = +5V, GND = 0V, Vic=2.5V, Tamb = 25°C (unless otherwise specified) (continued)
Table 6. V CC = +4.2V, GND = 0V, Vic=2.1V, Tamb = 25°C (unless otherwise specified)(1)
- All electrical values ar e guaranteed with correlation measurements at 2.4V and 5V.
- Standby mode is active when V STBY is tied to GND.
- Dynamic measurements - 20*log(rms(V out)/rms(Vripple)). Vripple is the superimposed sinus signal to VCC @ f = 217Hz.
- Independent of Gain configuration (6 or 12dB) and between IN+ or IN- and GND.
Table 7. V CC = +3.6V, GND = 0V, Vic=1.8V, Tamb = 25°C (unless otherwise specified)(1)
- All electrical values ar e guaranteed with correlation measurements at 2.4V and 5V.
- Standby mode is active when V STBY is tied to GND.
- Dynamic measurements - 20*log(rms(V out)/rms(Vripple)). Vripple is the superimposed sinus signal to VCC @ f = 217Hz.
- Independent of Gain configuration (6 or 12dB) and between IN+ or IN- and GND.
Table 8. V CC = +3.0V, GND = 0V, Vic=1.5V, Tamb = 25°C (unless otherwise specified)(1)
- All electrical values ar e guaranteed with correlation measurements at 2.4V and 5V.
- Standby mode is active when V STBY is tied to GND.
- Dynamic measurements - 20*log(rms(V out)/rms(Vripple)). Vripple is the superimposed sinus signal to VCC @ f = 217Hz.
- Independent of Gain configuration (6 or 12dB) and between IN+ or IN- and GND.
Table 9. V CC = +2.4V, GND = 0V, Vic=1.2V, Tamb = 25°C (unless otherwise specified)
- Standby mode is active when V STBY is tied to GND.
- Dynamic measurements - 20*log(rms(V out)/rms(Vripple)). Vripple is the superimposed sinus signal to VCC @ f = 217Hz.
- Independent of Gain configuration (6 or 12dB) and between IN+ or IN- and GND.
3.2 Electrical characteristic curves
- RL+ 15μH or 30μH = pure resistor + very low series resistance inductor
- Filter = LC output filter (1μF+30μH for 4Ω and 0.5μF+60μH for 8Ω) All measurements are done with CS1=1μF and CS2=100nF (see Figure 2, except for the PSRR where CS1 is removed (see Figure 3).
Figure 2. Test diagram for measurements Figure 3. Test diagram for PSRR measurements
15 H or 30 Hμμ
Table 10. Index of graphics
4 Application information
4.1 Differential configuration principle
The TS2007 is a monolithic fully-differential input/output class D power amplifier. The TS2007 also includes a common-mode feedback loop that controls the output bias value to average it at V CC/2 for any DC common mode input voltage. This allows the device to always have a maximum output voltage swing, and by consequence, maximize the output power. Moreover, as the load is connected differentially compared to a single-ended topology, the output is four times higher for the same power supply voltage. The advantages of a full-differential amplifier are:
- High PSRR (power supply rejection ratio)
- High common mode noise rejection
- Virtually zero pop without additional circuitry, giving a faster start-up time compared to conventional single-ended input amplifiers
- Easier interfacing with differential output audio DAC
- No input coupling capacitors required thanks to common mode feedback loop
4.2 Gain settings
In the flat region of the frequency-response curve (no input coupling capacitor or internal feedback loop + load effect), the differential gain can be set to either 6 or 12 dB depending on the logic level of the GS pin: Note: Between the GS pin and V CC there is an internal 300kΩ resistor. When the pin is floating the gain is 6 dB.
4.3 Common mode feedback loop limitations
As explained previously, the common mode feedback loop allows the output DC bias voltage to be averaged at V CC/2 for any DC common mode bias input voltage. Due to the Vic limitation of the input stage (see Table 2: Operating conditions on page 3), the common mode feedback loop can fulfil its role only within the defined range.
4.4 Low frequency response
If a low frequency bandwidth limitation is required, it is possible to use input coupling capacitors. In the low frequency region, the input coupling capacitor Cin starts to have an effect. Cin forms, with the input impedance Zin, a first order high-pass filter with a -3dB cut- off frequency (see Table 5 to Table 9). GS Gain (dB) Gain (V/V) 1 6dB 2 01 2 d B4
So, for a desired cut-off frequency FCL we can calculate Cin: with FCL in Hz, Zin in Ω and Cin in F . The input impedance Zin is for the whole power supply voltage range, typically 75kΩ . There is also a tolerance around the typical value (see Table 5 to Table 9). With regard to the tolerance, you can also calculate tolerance of the FCL:
4.5 Decoupling of the circuit
A power supply capacitor, referred to as CS, is needed to correctly bypass the TS2007. The TS2007 has a typical switching frequency of 280kHz and output fall and rise time about 5ns. Due to these very fast transients, careful decoupling is mandatory. A 1µF ceramic capacitor is enough, but it must be located very close to the TS2007 in order to avoid any extra parasitic inductance created by a long track wire. Parasitic loop inductance, in relation with di/dt, introduces overvoltage that decreases the global efficiency of the device and may cause, if this parasitic inductance is too high, a TS2007 breakdown. In addition, even if a ceramic capacitor has an adequate high frequency ESR value, its current capability is also important. A 0603 size is a good compromise, particularly when a 4Ω load is used. Another important parameter is the rated voltage of the capacitor. A 1µF/6.3V capacitor used at 5V, loses about 50% of its value. With a power supply voltage of 5V, the decoupling value, instead of 1µF , could be reduced to 0.5µF . As C S has particular influence on the THD+N in the medium to high frequency region, this capacitor variation becomes decisive. In addition, less decoupling means higher overshoots which can be problematic if they reach the power supply AMR value (6V).
4.6 Wake-up time (t wu)
When the standby is released to set the device ON, there is a wait of 5ms typically. The TS2007 has an internal digital delay that mutes the outputs and releases them after this time in order to avoid any pop noise. Note: The gain increases smoothly (see Figure 49) from the mute to the gain selected by the GS pin (Section 4.2). FCL Cin FCLmax 1.103 F CL⋅= FCLmin 0.915 F CL⋅=
4.7 Shutdown time
used to decrease the gain and avoid any pop noise during shutdown. Note: The gain decreases smoothly until the outputs are muted (see Figure 49).
4.8 Consumption in shutdown mode
the TS2007 to be in shutdown when the shutdown input is left floating. shutdown pin voltage is not 0V. shutdown current specified in Table 5 to Table 9.
4.9 Single-ended input configuration
shows a typical single-ended input application. Figure 50. Typical application for single-ended input configuration
4.10 Output filter considerations
different for each configuration, it is difficult to provide a one-size-fits-all solution.
- Reduce, as much as possible, the distance between the TS2007 output pins and the speaker terminals.
- Use a ground plane for “shielding” sensitive wires.
- Place, as close as possible to the TS2007 and in series with each output, a ferrite bead with a rated current of minimum 2.5A and impedance greater than 50Ω at frequencies above 30MHz. If, after testing, these ferrite beads are not necessary, replace them by a short-circuit.
- Allow extra footprint to place, if necessary, a capacitor to short perturbations to ground (see Figure 51).
Figure 51. Ferrite chip bead placement in Figure 1 on page 4 as close as possible to the TS2007.
5 Package information
Figure 52. Pinout (top view) Figure 53. Marking (top view) Figure 54. Recommended footprint for the TS2007 DFN8 package
Figure 55. DFN8 package mechanical data copper area can be electrically connected to pin7 or left floating.
- The dimension of L is not compliant with JEDEC MO-248 which recommends 0.40mm +/-0.10mm.
6 Ordering information
7 Revision history
Table 11. Order code 11-Jan-2007 1 Initial release (preliminary data). electrical characteristics curves and application information.