TS12A44513PWR

TS12A44513_10 TI | Alldatasheet

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D OR PW PACKAGE...TS12A44513 (TOP VIEW) 1 14 2 13 3 12 4 11 5 10 6 9 NO1 COM1 NC2 COM2 IN2 IN3 GND 7 8 IN1 IN4 NC4 COM4 COM3 NO3 D OR PW PACKAGE...TS12A44514 (TOP VIEW) 1 14 2 13 3 12 4 11 5 10 6 9 NO1 COM1 NO2 COM2 IN2 IN3 GND 7 8 IN1 IN4 NO4 COM4 COM3 NO3 D OR PW PACKAGE...TS12A44515 (TOP VIEW) 1 14 2 13 3 12 4 11 5 10 6 9 NC1 COM1 NC2 COM2 IN2 IN3 GND 7 8 IN1 IN4 NC4 COM4 COM3 NC3 DESCRIPTION/ORDERING INFORMATION TS12A44513 TS12A44514 TS12A44515 www.ti.com SCDS247 OCTOBER 2008 LOW ON-STATE RESISTANCE QUAD SPST CMOS ANALOG SWITCHES 2-V to 12-V Single-Supply Operation Specified Low OFF-Leakage Currents: Specified ON-State Resistance: nA at C Ω Max With 12-V Supply nA at C Ω Max With 5-V Supply Specified Low ON-Leakage Currents: Ω Max With 3.3-V Supply nA at C R DSON Matching nA at C 2.5 Ω (Max) at V Low Charge Injection: 11.5 pC (12-V Supply) Ω (Max) at V Fast Switching Speed: t ON ns, t OFF ns (12-V Supply) 3.5 Ω (Max) at 3.3 V Break-Before-Make Operation ON t OFF TTL/CMOS-Logic Compatible With 5-V Supply Available in TSSOP-14 Package, SOIC-14 The TS12A44513/TS12A44514/TS12A44515 are quad single pole/single throw (SPST), low-voltage wide range, single-supply CMOS analog switches, with very low switch ON-state resistance. The TS12A44513 has two switches normally closed (NC) and two switches normally open (NO), the TS12A44514 switches are normally open (NO), the TS12A44515 switches are normally closed (NC). These CMOS switches can operate continuously with a single supply between V and Each switch can handle rail-to-rail analog signals. The OFF-leakage current maximum is only nA at C or nA at All digital inputs have 0.8-V to 2.4-V logic thresholds, ensuring TTL/CMOS-logic compatibility when using a 5-V supply. Please be aware that an important notice concerning availability, standard warranty, and use in critical

applications

sheet. PRODUCTION DATA information is current as of publication date. Copyright 2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

(1) (2) THERMAL IMPEDANCE TS12A44513 TS12A44514 TS12A44515 SCDS247 OCTOBER 2008 www.ti.com ORDERING INFORMATION T A PACKAGE (1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING Reel of 2500 TS12A44513DR TS12A44513 SOIC D Reel of 2500 TS12A44514DR TS12A44514 Reel of 2500 TS12A44515DR TS12A44515 C to C Reel of 2000 TS12A44513PWR YD4513 TSSOP PW Reel of 2000 TS12A44514PWR YD4514 Reel of 2000 TS12A44515PWR YD4515 (1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com voltages referenced to GND MIN MAX UNIT V Supply voltage range 0.3 V V NC V NO Analog voltage range (3) 0.3 V 0.3 V V COM I NC I NO Analog Current range -20 mA I COM Continuous current into any terminal mA Peak current, NO or COM (pulsed at ms, 10% duty cycle) mA ESD per method 3015.7 2000 V T A Operating temperature range C D package 1.15 Mounted on JEDEC 4-layer board (JESD P D Power dissipation W 51-7), No airflow, T A T J 125 C PW package 0.88 T stg Storage temperature range 150 C Lead temperature (soldering, 300 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum (3) Voltages exceeding V or GND on any signal terminal are clamped by internal diodes. Limit forward-diode current to maximum current rating. UNIT D package 133 Mounted on JEDEC 1-layer board (JESD 51-3), No airflow PW package 167 Thermal impedance, θ JA C/W junction to free air D package Mounted on JEDEC 4-layer board (JESD 51-7), No airflow PW package 112 Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TS12A44513 TS12A44514 TS12A44515

(1) TS12A44513 TS12A44514 TS12A44515 www.ti.com SCDS247 OCTOBER 2008 V 4.5 V to 5.5 V INH 2.4 V INL 0.8 T A C to C (unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS T A MIN TYP (2) MAX UNIT Analog Switch Analog signal range V COM V NO V NC V V C V 4.5 V COM 3.5 ON-state resistance r on Ω I COM mA Full C ON-state resistance V COM r on(flat) Ω flatness I COM mA Full ON-state resistance C V 4.5 I COM mA, matching between Δ r on Ω V NO or V NC V T MIN to T MAX channels (3) C NO, NC I NO(OFF), V 5.5 V COM nA OFF leakage current (4) I NC(OFF) V NO or V NC 4.5 V Full C COM V 5.5 V COM I COM(OFF) nA OFF leakage current (4) V NO or V NC 4.5 V Full C COM V 5.5 V COM 4.5 I COM(ON) nA ON leakage current (4) V NO or V NC 4.5 V Full Digital Control Input (IN) Input logic high V IH Full 2.4 V V Input logic low V IL Full 0.8 V Input leakage current I IH I IL V IN V V Full 0.01 µ A Dynamic C 100 Turn-on time t ON see Figure ns Full 125 C Turn-off time t OFF see Figure ns Full C L nF, V NO Charge injection (5) Q C C 1.5 pC R S Ω See Figure NO, NC C NO(OFF) f MHz, See Figure C pF OFF capacitance C NC(OFF) COM C COM(OFF) f MHz, See Figure C pF OFF capacitance COM C COM(ON) f MHz, See Figure C pF ON capacitance Digital input capacitance C I V IN V V C pF R L Ω C L pF, Bandwidth BW C 530 MHz V NO V RMS f 100 kHz R L Ω C L pF, OFF isolation O ISO C dB V NO V RMS f 100 kHz R L Ω C L pF, Total harmonic distortion THD C 0.09 V NO V RMS f 100 kHz Supply C 0.05 V supply current I V IN V or V µ A Full 0.1 (1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum. (2) Typical values are at T A (3) Δ r ON r ON(MAX) r ON(MIN) (4) Leakage parameters are 100% tested at maximum-rated hot operating temperature, and are ensured by correlation at (5) Specified by design, not production tested Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TS12A44513 TS12A44514 TS12A44515

(1) TS12A44513 TS12A44514 TS12A44515 SCDS247 OCTOBER 2008 www.ti.com V 11.4 V to 12.6 V INH V INL 0.8 T A C to C (unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS T A MIN TYP (2) MAX UNIT Analog Switch Analog signal range V COM V NO V NC V V C 6.5 V 11.4 V COM ON-state resistance r on Ω I COM mA Full V 11.4 C 1.5 ON-state resistance r on(flat) V COM Ω flatness Full I COM mA ON-state resistance C 2.5 V 11.4 I COM mA, matching between Δ r on Ω V NO or V NC V T MIN to T MAX channels (3) C NO, NC I NO(OFF), V 12.6 V COM nA OFF leakage current (4) I NC(OFF) V NO or V NC V Full C COM V 12.6 V COM I COM(OFF) nA OFF leakage current (4) V NO or V NC V Full C COM V 12.6 V COM I COM(ON) nA ON leakage current (4) V NO or V NC V Full Digital Control Input (IN) Input logic high V IH Full V V Input logic low V IL Full 0.8 V Input leakage current I IH I IL V IN V V Full 0.001 µ A Dynamic C Turn-on time t ON See Figure ns Full C Turn-off time t OFF See Figure ns Full C L nF, V NO Charge injection (5) Q C C 10.5 pC R S Ω See Figure NO, NC C NO(OFF) f MHz, See Figure C pF OFF capacitance C NC(OFF) COM C COM(OFF) f MHz, See Figure C pF OFF capacitance COM C COM(ON) f MHz, See Figure C 21.5 pF ON capacitance Digital input capacitance C I V IN V V C pF R L Ω C L pF, Bandwidth BW C 530 MHz V NO V RMS f 100 kHz R L Ω C L pF, OFF isolation O ISO C dB V NO V RMS f 100 kHz R L Ω C L pF, Total harmonic distortion THD C 0.07 V NO V RMS f 100 kHz Supply C 0.05 V supply current I V IN V or V µ A Full 0.2 (1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum. (2) Typical values are at T A (3) Δ r ON r ON(MAX) r ON(MIN) (4) Leakage parameters are 100% tested at maximum-rated hot operating temperature, and are ensured by correlation at (5) Specified by design, not production tested Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TS12A44513 TS12A44514 TS12A44515

(1) TS12A44513 TS12A44514 TS12A44515 www.ti.com SCDS247 OCTOBER 2008 V V to 3.6 T A C to C (unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS T A MIN TYP (2) MAX UNIT Analog Switch Analog signal range V COM V NO V NC V V C V V COM 1.5 ON-state resistance r on Ω I NO mA, Full V C ON-state resistance r on(flat) V COM 1.5 Ω flatness Full I COM mA ON-state resistance C 3.5 V 2.7 I COM mA, matching between Δ r on Ω V NO or V NC 1.5 V T MIN to T MAX 4.5 channels (3) C NO, NC I NO(OFF), V 3.6 V COM nA OFF leakage current (4) I NC(OFF) V NO or V NC V Full C COM V 3.6 V COM I COM(OFF) nA OFF leakage current (4) V NO or V NC V Full C COM V 3.6 V COM I COM(ON) nA ON leakage current (4) V NO or V NC V Full Digital Control Input (IN) Input logic high V IH Full 2.4 V V Input logic low V IL Full 0.8 V Input leakage current I IH I IL V IN V V Full 0.01 µ A Dynamic C 120 Turn-on time (5) t ON See Figure ns Full 175 C Turn-off time (5) t OFF See Figure ns Full 120 Charge injection (5) Q C C L nF, See Figure C 0.5 pC NO, NC C NO(OFF) f MHz, See Figure C pF OFF capacitance C NC(OFF) COM C COM(OFF) f MHz, See Figure C pF OFF capacitance COM C COM(ON) f MHz, See Figure C pF ON capacitance Digital input capacitance C I V IN V V C pF R L Ω C L pF, Bandwidth BW C 510 MHz V NO V RMS f 100 kHz R L Ω C L pF, OFF isolation O ISO C dB V NO V RMS f 100 kHz R L Ω C L pF, Total harmonic distortion THD C 0.27 V NO V RMS f 100 kHz Supply C 0.03 V supply current I V IN V or V µ A Full 0.05 (1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum. (2) Typical values are at T A (3) Δ r ON r ON(MAX) r ON(MIN) (4) Leakage parameters are 100% tested at maximum-rated hot operating temperature, and are ensured by correlation at (5) Specified by design, not production tested Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TS12A44513 TS12A44514 TS12A44515

0 1 2 3 4 5 6 7 8 9 10 11 12 Analog Signal, V (V)COM ON-State Resistance, r ( ) ON Ω V = 3 V+ V = 4.5 V+ V = 11.4 V+ 0 1 2 3 4 Analog Signal, V (V)COM ON-State Resistance, r ( ) ON Ω T = 25°CA T = 85°CA T = –40°CA 0 1 2 3 4 5 6 7 8 9 10 11 12 Analog Signal, V (V)COM ON-State Resistance, r ( ) ON Ω T = 25°CA T = 85°CA T = –40°CA 0 1 2 3 4 5 Analog Signal, V (V)COM ON-State Resistance, r ( ) ON Ω VDD = 5.5 V T = –40°CA T = 25°CA T = 85°CA TS12A44513 TS12A44514 TS12A44515 SCDS247 OCTOBER 2008 www.ti.com Figure r ON vs V COM A Figure r ON vs V COM Figure r ON vs V COM 4.5 Figure r ON vs V COM 11.4 Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TS12A44513 TS12A44514 TS12A44515

www.ti.com SCDS247 OCTOBER 2008 PIN

DESCRIPTION

(1) PIN NO. TS12A44513 TS12A44514 TS12A44515 NAME V Power supply 12, 12, 12, IN Digital control to connect COM to NO or NC GND Digital ground NO Normally open NC Normally closed (1) NO, NC, and COM pins are identical and interchangeable. Any may be considered as an input or an output; signals pass in both directions. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TS12A44513 TS12A44514 TS12A44515

50 Ω ∆ VOUT is□the□measured□voltage□due□to charge transfer error□Q□when□the□channel□turns□off. Q□= V OUT x□CL VIN VOUT VNO or VNC =□0 V CL 1000 pF VIN VOUT ∆ VOUT V+ V+ 0 V TS12A44515 TS12A44514 TS12A44513 TS12A44515 TS12A44513 TS12A44514 TS12A44515 SCDS247 OCTOBER 2008 www.ti.com The TS12A44513/TS12A44514/TS12A44515 construction is typical of most CMOS analog switches, except that they have only two supply pins: V and GND. V and GND drive the internal CMOS switches and set their analog voltage limits. Reverse ESD-protection diodes connected in series are internally connected between each analog-signal pin and both V and GND. If an analog signal exceeds V or GND, one of the diodes will be forward biased, but the other will be reverse biased preventing current flow. Virtually all the analog leakage current comes from the ESD diodes to V or GND. Although the ESD diodes on a given signal pin are identical and, therefore, fairly well balanced, they are reverse biased differently. Each is biased by either V or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V and GND pins constitutes the analog-signal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog-signal paths and V or GND. V and GND also power the internal logic and logic-level translators. The logic-level translators convert the logic levels to switched V and GND signals to drive the analog signal gates. The logic-level thresholds are CMOS/TTL compatible when V is As V is raised, the level threshold increases slightly. When V reaches the level threshold is about V above the TTL-specified high-level minimum of 2.8 but still compatible with CMOS outputs. CAUTION: Do not connect the TS12A44513/TS12A44514/MAS4515 V to V and then connect the logic-level pins to logic-level signals that operate from 5-V supply. Output levels can exceed V and violate the absolute maximum ratings, damaging the part and/or external circuits. In 50- Ω systems, signal response is reasonably flat up to 250 MHz (see Typical Operating Characteristics Above MHz, the on response has several minor peaks that are highly layout dependent. The problem is not in turning the switch on; it is turning it off. The OFF-state switch acts like a capacitor and passes higher frequencies with less attenuation. At MHz, OFF isolation is about dB in 50- Ω systems, decreasing (approximately dB per decade) as frequency increases. Higher circuit impedances also make OFF isolation decrease. OFF isolation is about dB above that of a bare IC socket, and is due entirely to capacitive coupling. Figure Charge Injection Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TS12A44513 TS12A44514 TS12A44515

50% tOFFtON VIN 0 V GND IN NO COM 50 Ω TS12A44514 TS12A44513 300 Ω 35□pF 90% 90% 0 V 50% tONtOFF VIN 0 V GND IN NC COM 50 Ω 300 Ω 35□pF 90% 90% 0 V TS12A44515 TS12A44513 VNOPEAK VNOPEAK VNO VOUT VIN VNO VOUT VIN VOUT VOUT Measurements□are□standardized□against□short□at□socket terminals. OFF□isolation□is□measured□between□COM□and□OFF terminals on□each□switch. ON□loss□is□measured□between COM and ON□terminals□on□each□switch. Signal□direction□through switch is□reversed; worst□values□are□recorded. VOUT GND IN NO COM VIN TS12A44513/14/15 OFF□Isolation□=□20log VOUT VIN ON□Loss□=□20log VOUT VIN 50 Ω 50 Ω 50 Ω 50 Ω MEAS REF 10□nFV+ GND IN NO COM 1-MHzAs Required Analyzer Capacitance or NC TS12A44513/14/15 TS12A44513 TS12A44514 TS12A44515 www.ti.com SCDS247 OCTOBER 2008 Figure Switching Times Figure OFF Isolation and ON Loss Figure NO, NC, and COM Capacitance Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TS12A44513 TS12A44514 TS12A44515

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TS12A44513DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS12A44513DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS12A44513PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS12A44513PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS12A44514DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS12A44514DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS12A44514PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS12A44514PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS12A44515DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS12A44515DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS12A44515PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS12A44515PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. PACKAGE OPTION ADDENDUM www.ti.com 23-Jun-2008 Addendum-Page 1

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 23-Jun-2008 Addendum-Page 2

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 30-Jul-2010 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TS12A44513DR SOIC D 14 2500 346.0 346.0 33.0 TS12A44513PWR TSSOP PW 14 2000 346.0 346.0 29.0 TS12A44514DR SOIC D 14 2500 346.0 346.0 33.0 TS12A44514PWR TSSOP PW 14 2000 346.0 346.0 29.0 TS12A44515DR SOIC D 14 2500 346.0 346.0 33.0 TS12A44515PWR TSSOP PW 14 2000 346.0 346.0 29.0 PACKAGE MATERIALS INFORMATION www.ti.com 30-Jul-2010 Pack Materials-Page 2

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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