TS1100

TS1100 TOUCHSTONE | Alldatasheet

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Technical content

© 2011 Touchstone Semiconductor, Inc. All rights reserved.

FEATURES

♦ Improved Electrical Performance over the MAX9938 and the MAX9634 ♦ Ultra-Low Supply Current: 1μA ♦ Wide Input Common Mode Range: +2V to +25V ♦ Low Input Offset Voltage: 100μV (max) ♦ Low Gain Error: <0.5%(max) ♦ Voltage Output ♦ Four Gain Options Available: TS1100-25: Gain = 25V/V TS1100-50: Gain = 50V/V TS1100-100: Gain = 100V/V TS1100-200: Gain = 200V/V ♦ 5-Pin SOT23 Packaging

APPLICATIONS

Smart Battery Packs/Chargers

DESCRIPTION

The voltage -output TS1100 current-sense amplifiers are form -factor identical and electrical improvements to the MAX9938 and the MAX9634 current-sense amplifiers. Consuming a very low 1μA supply current, the TS1100 high-side current-sense amplifiers exhibit a 10 0-µV (max) VOS and a 0. 5% (max) gain error, both specifications optimized for any precision current measurement. For all high -side current -sensing applications, the TS1100 features a wide input common-mode voltage range from 2V to 25V. The SOT23 package makes the TS1100 an ideal choice for pcb-area-critical, low-current, high- accuracy current-sense applications in all battery- powered, remote or hand-held portable instruments. All TS1100s are specified for operation over the -40°C to +105°C extended temperature range. A 1µA, +2V to +25V SOT23 Precision Current-Sense Amplifier TYPICAL APPLICATION CIRCUIT PART GAIN OPTION TS1100-25 25 V/V TS1100-50 50 V/V TS1100-100 100 V/V TS1100-200 200 V/V The Touchstone Semiconductor logo is a registered trademark of Touchstone Semiconductor, Incorporated. PERCENT OF UNITS - % INPUT OFFSET VOLTAGE - µV 10 30 0 40 Input Offset Voltage Histogram

Continuous Power Dissipation (TA = +70°C) 5-Pin SOT23 (Derate at 3.9mW/°C above +70°C) .. 312mW Electrical and thermal stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not implied. Exposure to any absolute maximum rating conditions for extended periods may affect device reliability and lifetime. PACKAGE/ORDERING INFORMATION ORDER NUMBER PART MARKING CARRIER QUANTITY TS1100-25EG5TP TADJ Tape & Reel ----- TS1100-25EG5T Tape & Reel 3000 TS1100-50EG5TP TADK Tape & Reel ----- TS1100-50EG5T Tape & Reel 3000 TS1100-100EG5TP TADL Tape & Reel ----- TS1100-100EG5T Tape & Reel 3000 TS1100-200EG5TP TADM Tape & Reel ----- TS1100-200EG5T Tape & Reel 3000 Lead-free Program: Touchstone Semiconductor supplies only lead-free packaging. Consult Touchstone Semiconductor for products specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

VRS+ = VRS- = 3.6V; VSENSE = (VRS+ - VRS-) = 0V; COUT = 47nF; TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C. See Note 1 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Current (Note 2) ICC TA = +25°C 0.68 0.85 μA 1.0 VRS+ = 25V TA = +25°C 1.0 1.2 Common-Mode Input Range VCM Guaranteed by CMRR 2 25 V Common-Mode Rejection Ratio CMRR 2V < VRS+ < 25V 120 150 dB Input Offset Voltage (Note 3) VOS TA = +25°C ±30 ±100 μV ±200 Gain G TS1100-25 25 V/V TS1100-50 50 TS1100-100 100 TS1100-200 200 Gain Error (Note 4) GE TA = +25°C ±0.1 ±0.5 % ±0.6 Output Resistance (Note 5) ROUT TS1100-25/50/100 7.0 10 13.2 kΩ TS1100-200 14.0 20 26.4 OUT Low Voltage VOL Gain = 25 5 mV Gain = 50 10 Gain = 100 20 Gain = 200 40 OUT High Voltage (Note 6) VOH VOH = VRS- - VOUT 0.05 0.2 V Output Settling Time tS TS1100-25/50/100 1% final value, VSENSE = 50mV 2.2 ms TS1100-200 4.3 ms Note 1: All devices are 100% production tested at TA = +25°C. All temperature limits are guaranteed by product characterization. Note 2: Extrapolated to VOUT = 0. ICC is the total current into the RS+ and the RS- pins. Note 3: Input offset voltage VOS is extrapolated from VOUT with VSENSE set to 1mV. Note 4: Gain error is calculated by applying two values for VSENSE and then calculating the error of the actual slope vs. the ideal transfer characteristic: For GAIN = 25, the applied VSENSE is 20mV and 120mV. For GAIN = 50, the applied VSENSE is 10mV and 60mV. For GAIN = 100, the applied VSENSE is 5mV and 30mV. For GAIN = 200, the applied VSENSE is 2.5mV and 15mV. Note 5: The device is stable for any capacitive load at VOUT. Note 6: VOH is the voltage from VRS- to VOUT with VSENSE = 3.6V/GAIN.

Supply Current vs Common-Mode Voltage Input Offset Voltage vs Temperature Supply Current vs Temperature PERCENT OF UNITS - % INPUT OFFSET VOLTAGE - µV INPUT OFFSET VOLTAGE - µV TEMPERATURE - °C TEMPERATURE - °C SUPPLY CURENT - µA SUPPLY VOLTAGE - Volt 10 30 0 40 25V 3.6V SUPPLY CURRENT - µA TYPICAL PERFORMANCE CHARACTERISTICS VRS+ = VRS- = 3.6V; TA = +25°C, unless otherwise noted. -40 -15 10 35 85 60 0.2 0.6 0.4 0.8 -40 0.2 0.6 0.8 0.4 Input Offset Voltage Histogram 0 10 15 20 30 25 5 GAIN ERROR - % Gain Error Histogram PERCENT OF UNITS - % Input Offset Voltage vs Common-Mode Voltage INPUT OFFSET VOLTAGE - µV SUPPLY VOLTAGE - Volt 10 15 20 30 25 5 0 110 -40 -15 10 35 85 60 110 -20

Small-Signal Gain vs Frequency SMALL-SIGNAL GAIN -dB 0.001 0.1 1 10 1000 -15 -35 -25 FREQUENCY - kHz -10 -20 -30 100 TYPICAL PERFORMANCE CHARACTERISTICS VRS+ = VRS- = 3.6V; TA = +25°C, unless otherwise noted. 0.01 Gain Error vs. Temperature GAIN ERROR - % TEMPERATURE - °C 0.1 0.4 0.5 -0.1 0.2 0.3 Gain Error vs Common-Mode Voltage SUPPLY VOLTAGE - Volt 0.2 0.3 0.1 GAIN ERROR - % 0 10 15 20 30 25 5 VSENSE- mV VOUT vs VSENSE @ Supply = 3.6V 0 150 100 50 0.5 2.5 3.5 1.5 VOUT - V VOUT - V 0 100 60 20 VSENSE- mV VOUT vs VSENSE @ Supply = 2V 40 80 0.4 1.6 0.8 1.2 1.4 1.0 0.6 0.2 COMMON-MODE REJECTION - dB Common-Mode Rejection vs Frequency -40 -80 -20 -60 -100 -140 -120 FREQUENCY - kHz 0.001 0.1 1 10 1000 100 0.01 G = 25 G = 50 G = 100 1.8 G = 25 G = 50 G = 100 G = 25 G = 50 G = 100 G = 25 G = 50, 100 -40 -15 10 35 85 60 110

Input Offset Voltage Histogram TYPICAL PERFORMANCE CHARACTERISTICS VRS+ = VRS- = 3.6V; TA = +25°C, unless otherwise noted. 200µs/DIV VSENSE VOUT Small-Signal Pulse Response, Gain = 50 200µs/DIV Large-Signal Pulse Response, Gain = 50 VSENSE VOUT 200µs/DIV VSENSE VOUT Large-Signal Pulse Response, Gain = 25 200µs/DIV Small-Signal Pulse Response, Gain = 25 VSENSE VOUT 200µs/DIV Small-Signal Pulse Response, Gain = 100 VSENSE VOUT 200µs/DIV VSENSE VOUT Large-Signal Pulse Response, Gain = 100

5 RS+ External Sense Resistor Power-Side Connection

4 RS- External Sense Resistor Load-Side Connection

1, 2 GND Ground. Connect these pins to analog ground. 3 OUT Output Voltage. VOUT is proportional to VSENSE = VRS+ - VRS- BLOCK DIAGRAM DESCRIPTION OF OPERATION The internal configuration of the TS1100 – a unidirectional high -side, current -sense amplifier - is based on a commonly -used operational amplifier (op amp) circuit for measuring load currents (in one direction) in the presence of high -common-mode voltages. In the general case, a current -sense amplifier monitors the voltage caused by a load current through an external sense resistor and generates an output voltage as a function of that load current. Referring to the typical application circuit on Page 1 , the inputs of the op -amp-based circuit are connected across an external RSENSE resistor that is used to measure load current. At the non -inverting input of the TS1100 (the RS + terminal), the applied voltage is ILOAD x RSENSE. Since the RS - terminal is the non-inverting input of the internal op amp, op-amp feedback action forces the inverting input of the internal op amp to the same potential (ILOAD x RSENSE). Therefore, the voltage drop across RSENSE (VSENSE) and the voltage drop across RGAIN (at the RS+ terminal) are equal. To minimize any additional error because of op -amp input bias current mismatch, both RGAINs are the same value. Since the internal p -channel FET’s source is connected to the inverting input of the internal op amp and since the voltage drop across RGAIN is the same as the external V SENSE, op amp feedback action drives the gate of the FET such that the FET’s drain - source current is equal to: S VSENSE RGA N

Since the FET’s drain terminal is connected to R OUT, the output voltage of the TS1100 at the OUT terminal is, therefore; VOUT LOA x RSENSE x ROUT RGA N The current-sense amplifier’s gain accuracy is therefore the ratio match of R OUT to RGAIN. For each of the four gain options available, Table 1 lists the values for R OUT and RGAIN. The TS1100’s output stage is protected against input overdrive by use of an output current-limiting circuit of 3mA (typical) and a 7V internal clamp protection circuit. Table 1: Internal Gain Setting Resistors (Typical Values) GAIN (V/V) RGAIN (Ω) ROUT (Ω) Part Number 25 400 10k TS1100-25 50 200 10k TS1100-50 100 100 10k TS1100-100 200 100 20k TS1100-200 To achieve its very -low input offset voltage performance over temperature, VSENSE voltage, and power supply voltage, the design of the TS1100’s amplifier is chopper -stabilized, a commonly-used technique to reduce significantly the input offset voltage of amplifiers. This method, however, does employ the use of sampling techniques and therefore residue of the TS1100’s 10kHz internal clock is contained in the TS1100’s output voltage spectrum. APPLICATIONS INFORMATION Choosing the Sense Resistor Selecting the optimal value for the external RSENSE is based on the following criteria and for each commentary follows: 1) RSENSE Voltage Loss 2) VOUT Swing vs. Applied Input Voltage at VRS+ and Desired VSENSE 3) Total ILOAD Accuracy 4) Circuit Efficiency and Power Dissipation 5) RSENSE Kelvin Connections 6) Sense Resistor Composition 1) RSENSE Voltage Loss For lowest IR voltage loss in RSENSE, the smallest usable value for RSENSE should be selected. 2) VOUT Swing vs. Applied Input Voltage at VRS+ and Desired VSENSE As there is no separate power supply pin for the TS1100, the circuit draws its power from the applied voltage at both its RS+ and RS - terminals. Therefore, the signal voltage at the OUT terminal is bounded by the minimum supply voltage applied to the TS1100. Therefore, VOUT(max) = VRS+(min) - VSENSE(max) – VOH(max) and RSENSE VOUT max GA N LOA max where the full -scale V SENSE should be less than VOUT(MAX)/GA N at the application’s minimum RS+ terminal voltage. For best performance with a 3.6V power supply, RSENSE should be chosen to generate a VSENSE of: a) 120mV (for the 25V/V GAIN option), b) 60mV (for the 50V/V GAIN option), c) 30mV (for the 100V/V GAIN option), or d) 15mV (for the 200V/V GAIN option) at the full -scale I LOAD(MAX) current in each application. For the case where the minimum power supply voltage is higher than 3.6V, each of the four full -scale V SENSEs above can be increased. 3) Total ILOAD Accuracy In the TS1100’s linear region where VOUT < VOUT(MAX), there are two specifications related to the circuit’s accuracy: a) the TS1100’s input offset voltage (V OS = 100μV, max ) and b) its gain error (GE(max) = 0.5%).

low-pass filters in series with the current -sense amplifier’s inputs only introduces additional offset voltage and gain errors. To minimize or eliminate altogether the need for external low -pass filters and to maintain low input offset voltage and gain errors, the TS1100 incorporates a 50 -kHz (typ), 2 nd-order differential low-pass filter as shown in the TS1100’s Block Diagram. Optional Output Filter Capacitor If the TS1100 is part of a signal acquisition system where its OUT terminal is connected to the input of an ADC with an internal, switched -capacitor track - and-hold circuit, the internal track -and-hold’s sampling capacitor can cause voltage droop at V OUT. A 22nF to 100nF good-quality ceramic capacitor from t he OUT terminal to GND forms a low -pass filters with the TS1100’s ROUT and should be used to minimize voltage droop (holding V OUT constant during the sample interval. Using a capacitor on the OUT terminal will also reduce the TS1100’s small- signal bandwidth as well as band -limiting amplifier noise. PC Board Layout and Power-Supply Bypassing For optimal circuit performance, the TS1100 should be in very close proximity to the external current - sense resistor and the pcb tracks from RSENSE to the RS+ and the RS - input terminals of the TS1100 should be short and symmetric. Also recommended are a ground plane and surface mount resistors and capacitors. Using the TS1100 in Bidirectional Load Current In many battery-powered systems, it is oftentimes necessary to monitor a battery’s discharge and charge currents. To perform this function, a bidirectional current-sense amplifier is required. The circuit illustrated in Figure 2 shows how two TS1100s can be configured as a bidirectional current-sense amplifier. As shown in the figure, the RS+/RS- input pair of TS1100 #2 is wired opposite in polarity with respect to the RS+/RS- connections of TS1100 #1. Current-sense amplifier #1 therefore measures the discharge current and current-sense amplifier #2 measures the charge current. Note that both output voltages are measured with respect to GND. When the discharge current is being measured, VOUT1 is active and VOUT2 is zero; for the case where charge current is being measured, VOUT1 is zero, and VOUT2 is active. Figure 2: Using Two TS1100s for Bidirectional Load Current Detection

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+1 (408) 215 - 1220 ▪ www.touchstonesemi.com RTFDS PACKAGE OUTLINE DRAWING 5-Pin SOT23 Package Outline Drawing (N.B., Drawings are not to scale) Information furnished by Touchstone Semiconductor is believed to be accurate and reliable. However, Touchstone Semiconductor does not assume any responsibility for its use nor for any infringements of patents or other rights of third parties that may result f rom its use, and all information provided by Touchstone Semiconductor and its suppliers is provided on an AS IS basis, WITHOUT WARRANTY OF ANY KIND . Touchstone Semiconductor reserves the right to change product specifications and product descriptions at any time without any advance notice. No license is granted by implication or otherwise under any patent or patent rights of Touchstone Semiconductor. Touchstone Semiconductor assumes no liability for applications assistance or customer product design. Customers are responsible for thei r products and applications using Touchstone Semiconductor components. To minimize the risk associated with customer products and applications, customers should provide adequate design and operating safeguards. Trademarks and registered trademarks are the property of t heir respective owners. NOTES: 1. Dimensions and tolerances are as per ANSI Y14.5M, 1982. 2. Package surface to be matte finish VDI 11~13. 3. Die is facing up mold and facing down for trim/form, ie, reverse trim/form. 4. The foot length measuring is based on the gauge plane method. 5. Dimensions are exclusive of mold flash and gate burr. 6. Dimensions are exclusive of solder plating. 7. All dimensions are in mm. 8. This part is compliant with EIAJ spec. and JEDEC MO-178 AA 9. Lead span/stand off height/coplanarity are considered as special characteristic. 2.80 - 3.00 2.60 - 3.00 1.50 - 1.75 0.95 0.950 TYP 0.30 - 0.50 0.00 - 0.15 10º TYP 10º TYP 10º TYP 0.09 - 0.205 10º TYP 0º- 8º 0.30 - 0.55 0.25 Gauge Plane

1.90 Max

0.10 Max

0.09 – 1.45 0.50 – 0.70 1.50 – 1.75

0.50 Max

0.30 Min

0.20 Max

0.09 Min

0.90 - 1.30 0.60 – 0.80 TYP