TRU050 ETC | Alldatasheet
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Technical content
Vectron International's TRU-050 module is a user-configured, phase-locked loop (PLL) solution designed to simplify a wide variety of clock recovery and data retiming, frequency translation and clock smoothing applications. The device features a phase-lock loop ASIC with a quartz stabilized VCXO for superior stability and jitter performance. This highly integrated module provides unsurpassed performance, reliability and quality. The proprietary ASIC device includes a refined Phase Detector, a Loop Filter Op-Amp, a Loss of Signal Alarm with Clock Return to Nominal feature, a VCXO circuit, and an optional 2" divided output. The ASIC and quartz resonator are housed in a hermetic 16-pin DIL ceramic package with optional thru-hole or surface mount leads. The VCXO frequency (OUT1) and division factor (OUT2) are factory set in accordance with customer specifications. PLL response is optimized for each application by the selection of three external passive components. Software is available from Vectron to aid in loop filter component selection and loop response modeling. Features: Benefits: , , What is the main PLL with quartz stabilized VCXO Flexible modular solution benefit of the Output jitter less than 20 ps Reduce design time TRU-050? Loss of signal (LOS) alarm Increase circuit reliability a | It's a single drop-in Return to nominal clock upon LOS Less board space . Quartz Stabilized Input data rates from 8 kb/s to 65 Mb/s Reduces component count , PLL solution. Surface mount option In-state output F . User defined PLL loop response Whats Inside? NRZ data compatible What Does It Do? How Is It Used? , Pages 3-5 Pages 15-18 Robust hermetic ceramic package J J , , Ht? ? Single or +5.0 V supply (+3.3V option available) How Is It Built: How Is It Packaged: Pages 6-11 How Is It Ordered? Page 19 How Does It Perform? J Pages 12-14 Vectron International © 267 Lowell Road, Hudson, NH 03051 lel: 1-88-VECTRON-1 — e-mail: vectron@vectron.com 1 of 17
1 I 1 /
- For input RZ data, Manchester encoded data, Output 1 ' — OUTI ! 120 | 65.536 | MHz
- QUI2 is a binary submultiple of OUTI, or I
it may be disabled. Transition Times.
- Figure 1 defines these parameters. Figure 2 5 i i
1 Rou | | Ig
- Symmetry is the ON TIME/PERIOD jn Recovered Clock ! CLK ! 40 : 60 : %
- Alloss of signal (LOS) indicator is set to a . ! y ! !
- Accuracy at room temperature. Stability Output Logic High ! “OH 29 V
4 Period ——¥ uu ovyot SYM= 100 x Peto (4
Figure 1. = Figure 2.
Pin — Symbol Function 1 Control voltage input to internal voltage controlled crystal oscillator (VCXO). 2 ON Negative input terminal to internal operational amplifier. 3 OPOUT Output terminal of internal operational amplifier. 4 Op Positive input terminal to internal operational amplifier.
5 LOSIN With LOSIN set to a logic high, the external input to the VCXO (VC) is
disabled and the VCXO returns to it’s nominal center frequency. With LOSIN set to logic low, the external input to the VCXO is enabled. The LOSIN input has an internal pull-down resistor. 6 Output signal produced by phase detector. 7 DATAIN Input data stream to phase detector (TLL switching thresholds). 8 Circuit and cover ground. 9 CLKIN Input clock signal to phase detector (TTL switching thresholds). Wh Wo U | d
10 LOS Loss of signal indicator is set to a logic high if no transitions are y
detected at DATAIN after 256 clock cycles. As soon as a transition occurs at DATAIN, LOS is set to a logic low. 5 0 Mm e On e Db Uy 11 RCLK TTL compatible recovered clock. a T R U 0 5 0 7) 12 RDATA TTL compatible recovered data stream. : 13 OUT2 Divided version of internal VCXO output clock (TTL).
14 HIZ When set to a logic low, output pins OUT1, OUT2, RCLK, and RDATA lo SaVe ales | g if l/ Mm C,
buffers are set to high-impedance state. When set to a logic high or no connect, the device functions and output pins OUT1, OUT2, RCLK, if ‘a d U¢e CO M D 0 if] ‘a nt and RDATA are active. This input has an internal pull-up resistor. 15 OUT1 Output clock of internal VCXO (TTL). coun f conserve 16 +5.0 V +10% supply voltage (+3.3 V option available). board space, lable 2. and optimize manufacturing efficiency. Figure 3. Vectron International 267 Lowell Road, Hudson, NH 03051 lel: 1-88-VECTRON-1 — e-mail: vectron@vectron.com 3 of 17
The TRU-050 is a user-configured phase-locked loop (PLL) integrated circuit. It includes a voltage controlled crystal oscillator (VCXO), an operational amplifier, a phase detector, and additional integrated functions for use in digital synchronization applications. These applications include timing recovery and data pulse restoration for data signals, clock frequency translation and smoothing, synchronous distributed clock networks, and clock frequency synthesis. What is the output of the IRU-050 Elements phase detector? | Figure 4. [he TRU-050 phase detector output dt abe! im ae is a DC signal, under locked | Z oT : ! l conditions, and is nominally 2.5 ! u Low Fibs : OpAmp Volts. The phase error (which is a oe || | | 7 : Phase a : typically a pulse for digital phase | Detector l - _ a | detectors) is converted to a DC | n level, making it easy to design eed the loop filter. oleh iets *aleieietate ateteietetatetatetetatetatetetetetetatatetataten Prost Detcte Ouiput OC. Signd Roporiend t DetetCleck Foes Gro. LORS: LOS INC ompliment Output High efler 6 God Cycks [pin 9) wth no input Trerafions [pint } How long does the LOS Mt LOE Compliment bputHigh 6 VOCNO & Center Frequency [4-75 ppm} : Divide Circut Optional? M Oude Crountte Frequency Trembten oo FZ Oppic ions IRU-050 take to detect op Fitr Opp: Fordicive loep Fb a loss of signal? If there are no transitions on P h ase 1) Q t er t or DAIAIN for a period of 256 clock | | The phase detector is designed to accept an NRZ data stream at DATAIN (Pin 7- refer to figure 5), but may be used cycles, LOS is set to a logic 1. . ; "Ls for clock signals and other data types. The input buffers are designed to switch at a TTL switching threshold of 1.4 V. LOS is reset to logic 0 as soon as .
7 The phase detector's inputs are:
there are DATAIN transitions. + DATAIN (Pin 7) - the input clock or NRZ data signal ¢ CLKIN (Pin 9) - the clock signal feedback from the VCXO output OUT1 or OUT2 And the outputs are: © RCLK (Pin 11) - the regenerated clock signal ¢ RDATA (Pin 12) - the retimed data signal ¢ PHO (Pin 6) - the phase detector output ¢ LOS (Pin 10) - a loss of signal detector The phase relationship between the regenerated clock signal, RCLK (Pin 11), and the regenerated data signal, RDATA (Pin 12), is shown in figure 6. 4 of 17 Vectron International 267 Lowell Road, Hudson, NH 03051 lel: 1-88-VECTRON-1 — e-mail: vectron@vectron.com
(Fins) (Pinz) [(Pn3) (Pin1) LOS (Pin 10) ie oe LAW LOSIN (Pin 5) Loop Fitter WORD m- CUT! (Pin 15) DAT AIM (Pin 7) -diees Bee Op- dimp Detector . ard LOS CLEIM [Pin 9) -@ ge ere RCLK =RDATA «OP | GN py Hz Figure 3. inti) (Pni2) (Pind) (Ané) (Anis) (Pn #4) -_ . How Is it The falling edge of RCLK is coincident with 9 cumin? | TLE LILI LI LU | the center of the regenerated NRZ RDATA " manufactured pulse. Figure 6 shows a 1010 data stream | with a 100% data transition density. In = RKOPinay | FE [| | PLT Ly [he [RU-050 Is eneral, this will not be the case and input RDATA(Pin 12) g TS CRS lara 1 ! , _— a barepeed_ J |_| assembled in data will have fewer data transitions. aligmant Figure 6 However, the phase detector will still seek ge © “state of the art” to align the falling edge of the RCLK signal with the center of each RDATA pulse. | | | | class 100 and class For applications where the input clock or data signal, DATAIN, is very low in frequency (<200kHz), clock information may pass through the phase detector because of its finite low pass characteristic. In applications 10, 000 clean such as this, an additional pole may be necessary in the loop filter to attenuate these AC components prior to ing lead) the VCXO input. Please contact Vectron’s Applications Engineering staff for further detail. (OOMTIS USI Ng Cd Ing edge, high volume DATAIN ax S&S 4 automation equip- " t “pCO Relative Vv vy “pole Ga Phase (6, ment and advanced » | OV cnnnch i nnnnncncbennnnnnnnnndennnnes , | | ASIC technology. Figure /. ein <4 i2n Gain Slope = 5 Volts / 2 7 Figure 8. Phase Detector Gain Calculation The schematic diagram (figure 7) shows a simplified representation of the phase detector's basic error generation function. The actual circuit is more complex and includes circuitry to reduce the TRU-050's dependence on input data duty-cycle. In general, the TRU-050 is insensitive to duty cycle and duty cycle changes. This circuit provides a output (Vp) DC level which is proportional to the relative phase of DATAIN (Pin 7) and CLKIN (Pin 9). A plot of the output (Vp) versus relative phase is shown in figure 8. The slope of the output (Vp ) versus relative phase (0) is SV/27. The phase detector block also includes an output gain stage which should be considered when calculating the gain of the complete phase detector block. This gain stage has a gain of 2/3, and converts the differential signal to a single-ended DC output. Vectron International 267 Lowell Road, Hudson, NH 03051 _Tel: 1-88-VECTRON-1 e-mail: vectron@vectron.com 3 of 17
and D = 0.5 for 50% transition density (e.g., balanced NRZ data). frequency (+75 ppm). When LOSIN is low or has no connection, the VCXO's control voltage input is enabled (LOSIN has an internal pull-down resistor). Figure 10. RO = RS
figure 11. When designing PLLs, the VCXO gain (kV in Hz/V or rad/Vs) is an important parameter. As a rule of quality Is further thumb, the frequency deviation for the TRU-O50 VCXO is 300 ppm over the 1 V to 4 V range Vp. stress on the crystal and mass-loading of foreign material on the crystal. and results in minimal relaxation and almost negligible environmental stress transfer.
Mass-loading on the crystal generally results in a frequency decrease and is typically due to out-gassing of material within a hermetic package or from contamination by external material in a non-hermetic package. Vectron has minimized the impact of mass loading by ensuring hermetic integrity and minimizing out-gassing by limiting the number of internal components through the use of ASIC technology. Under normal operating conditions with an operating temperature of 40°C, the [RU-050 will typically exhibit 2 ppm aging in the first year of operation. The device will then exhibit 1 ppm aging the following year with a logarithmic decline each year thereafter. I'm not familiar with APR. iti Absolute Pull Range Could you explain it in more detail? Absolute pull range (APR) \\s specified by the fourth character of the product code (see figure 26). APR is the | minimum guaranteed frequency shift from fc over variations in temperature, aging, power supply and load. Both APR Is the guaranteed frequency -_ _ a | frequency and environment limit the specified APR. The total pull range for the VCXO contained in the TRU-050 error (in ppm) the VCXO can a | Is typically between 200 ppm and 400 ppm. A 50 ppm APR TRU-050 fully tracks a 50 ppm source oscillator track. This takes the guesswork . | | or any other 50 ppm reference over the operating temperature range, life of the product, power supply and out of the total pull range which | | measurement variations. drifts and is affected by temperature, aging, power supply etc. Every IRU-050 is tested for pull range over the operating Output DI vider Circuit temperature range, making it one . oo, . . | An internal 2" divided output is available at OUT2. The value of n varies from 1 to 8 and is set during of the most reliable devices on Ce ; . a, be mark manufacture. This provides divide ratios from 2 to 256. A “no output” option may also be selected to minimize the market. power usage and jitter. Divider Note: The frequency of OUT1 is the fundamental frequency of the VCXO used in the TRU-050. The What's the difference lowest frequency VCXO (OUT7) available in the TRU-050 is 12 MHz, and the highest frequency is 65.536 MHz. between OUTT and OUI2: Therefore, the frequency range of OUTT is between 12 MHz and 65.536 MHz. Since OUT2 Is a division of QUT is the direct output from the OUT1 and can vary from OUT1 = 2 to OUT1 = 256, OUT2 ranges from 46.875 kHz (12 MHz = 256) to VCXO and is limited to frequencies 32.768 MHz (65.536 MHz = 2). Lower frequency inputs may be supplied to the phase detector of the TRU- in the 12 MHz to 65 MHz range. 050, but an external divider in the feedback loop is required. With an external divider in the feedback loop, OUT2 is an optional 2” divided clock and data signals down to 8 kHz can be used as phase detector inputs. VCXO output. The divide ratio is factory set at 2, 4, 8, ...or 2", up to 256. 8 of 17 Vectron International 267 Lowell Road, Hudson, NH 03051 _Iel: 1-88-VECTRON-1 e-mail: vectron@vectron.com
] How Is it Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Vectron employs a human body model (HBM) and a Pa ck aged? charged device model (CDM) for ESD susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the mode. Although no industry-wide standard has been The TRU-050 IS d adopted for CDM, a standard HBM (resistance = 1500 2, capacitance = 100 pF) is widely used and therefore can b , fl , be used for comparison purposes. The HBM ESD threshold presented here was obtained using these circuit parameters. Very (ODUS P (Od which Is assembled MODEL ESD Threshold, Minimum Unit on an automated Charged Device y manufacturing line. ruman Body Y It is packaged in a with a seam-welded Step lid, hermetically sealed for long term reliability. Options i ™ \\ Include thru-hole —— and surface mount —— terminals and an extended temper- ature range. lape and reel packaging IS also available. Vectron International 267 Lowell Road, Hudson, NH 03051 Tel: 1-88-VECTRON-1 e-mail: vectron@vectron.com 9 of 17
A typical PLL is illustrated in figure 12. Be advised that many textbook equations describing loop dynamics, such as capture range or lockin time, are based on ideal systems. Such equations may not be accurate for real systems with nonlinearities, DC offsets and noise. A PLL is a feedback system which forces the output frequency to lockin both phase and frequency to the fundamental frequency of the input signal. When initially out of lock, the output of the phase detector is proportional to the difference in frequency between the two phase detector inputs. This beat note varies the output frequency of the VCXO, and in a properly designed phase-locked loop, the loop action forces V, to the correct value to bring the system into lock. Phase-Locked Loop Figure 17. = ; : _ OUTPUT Phase Locked Loop Black Diagram A designer's primary concern Is to select a loop filter that ensures lockin and stability, while providing adequate filtering of input signal noise or jitter. An initial design starts with a known DAIAIN signal and an output specification. An initial analysis of the open loop gain response provides insight into the response of the system. Using figure 12, the open loop gain is: G(s)= Kp kV AV(s) SN Where: Kp is the phase detector gain in V/rad (-0.53 x Data Density). kV is the VCXO gain constant in Rad/Vs. AV(s) ts the loop filter transfer function. N is the divide ratio. 1/s converts the VCXO frequency output to a phase output. The open loop gain may be plotted and varied using the SPICE model provided in figure 13. The gain, frequency, and loop filter configurations may be varied to producedesired responses. In the first-order phase-locked loop, where AV(s) and N equal 1, the gain curve has a 20 dB/decade slope with unity gain at: r_ KV-Kp where kV is in rad/Vs. 10 of 17 Vectron International 267 Lowell Road, Hudson, NH 03051 _Tel: 1-88-VECTRON-1 e-mail: vectron@vectron.com
a Open Loop Response 15°F TTT TTT OT CITI)” oD eceee 72° a TEE TE | PEN Loop PHASE! | re es * Open loop gain margin is a 50 ATTIRE ot t -3-IcetUl a -U AZ PTE oP RTE PTE, EEE, ET * ij a PTT} PETE PP DML TEE) De -ao = Closed loop jitter bandwidth aL {LLU LL WL LLU a Tt See 4 ry 32.7b8 MHz YCkKo “RA ee Bill: ° ("3 0B) as Aou0 Hz. | YY O96 MHz Feedback Loopm))) 0) A) | af -200 | TRU-OSO-GcCFA Ca PSE closed loop gain is O-11b14 cB Oe, 10 1Lo00 105 Frequency (Hz } . at a frequency of 65-000 Hz 4 J Figure 14. * Damping factor = 4.0 * RL = 13-5 k ohm Closed Loop Response * RF = 79-6 k ohm Oe TTT Tym frm oft [6 Tm) hUOTTTM = 0. Pa oP TE Ey 3c-fbd MHZ VOAO Hid CF = 0-10 JF : Ju a0 MHz Feedback Loop | * Data density = 100% — | | HH | | Hil | | mee OT We * VCXO FREQ = 32-768 MHz Ss Oooo = A PF TEHENE EE TT,TA Bg Pendent tdi be detalii eft tliemetet afd Hadad =; PH PTE EET, EE, AE TT PEE OP EAR, EET EERE, TEE, TT PAT PRR EE ET TR Ed Pn OP TEA EET, ET TTR ET PH TA ET, EE, ER ET O-] 10 1000 105 Frequency {Hz} Figure 15. 12 of 17 Vectron International 267 Lowell Road, Hudson, NH 03051 lel: 1-88-VECTRON-1 — e-mail: vectron@vectron.com
Applications
The three key applications for the TRU-050 are clock recovery of digital data, frequency translation and clock smoothing. These timing needs are required by a wide variety of markets such as telecommunications, datacommunications, digital video and audio, telemetry, test equipment and sensing. Clock Recovery and Data Retiming The TRU-050 was designed to recover a clock imbedded in an NRZ data signal, and retime it with a data pattern. In this application, the VCXO frequency is exactly the same as the NRZ data rate and the outputs are taken off Pin 11 (Recovered Clock) and Pin 12 (Recovered Data). The diagram below shows a typical circuit. Figure 17 shows the relationship between DAIAIN (Pin 7) and CLKIN (Pin 9) under locked conditions. The rising edge Is Vec if On | s) 0 of the CLKIN is centered to the DATAIN pulse. : registered? PHO OPN OPOUT Vp LOS (Fin "y Pin) (Fin) (Fin 3} (Fin 1} = (Fin 5) pW AW — Yes! Vectron s ieee 0 es #4 84 Mie DATAIN(Pin 7) F vex OUT1 (Fin 15) qua I ly SV stem was Oe Phase Loop Filer Deter Op.emp registered to ISO 31.040 MH anes ae 9001 in October 1996 RCLK (Fin 11) RDATA (Fin 12) Figure 16. Relationship of RCLK (Pin 11) and RDATA (Pin 12). The falling edge of the Recovered Clock is in the middle of the data pattern and should be used to clock the data into the next part of the circuit. There is a one and a half cycle delay (frequency of Pin 9) between DATAIN and RDATA. Therefore a 10 MHz signal would have a 150 nS delay between DATAIN and RDATA plus additional circuit delays, which are typically 9 nS. DATAIN, [Datat Lif coON | OT LL LS RDATA is clock cycles -»| Data 1 | | | ROLE ELL LL LI Figure 17. Vectron International © 267 Lowell Road, Hudson, NH 03051 _Tel: 1-88-VECTRON-1 e-mail: vectron@vectron.com 13 of 17
16.000 ns 31.0000 ns 46.0000 ns FR PAP sen eee: NO Bes li ROLK PR) trucos @ 51.84 mi CT Tela edge of Ret pnaya |_| | is contered with respect A Ch. 1 = 1.000 = Volts/div Offset = 9/6.2 mVolts Ch. 2 = 1.000 = Volts/div Offset = 951.2 mVolts , Timebase = 3.000 _ ns/div Delay = 16.0000 ns Figure 18. Timing Recovery Using OUI2 Due to the limitations in crystal size, the lowest frequency from OUT1 is 12 MHz. For applications below this frequency, the internal divide-by can be used (Note: an additional external divide-by can also be used). An application for 1.544 MHz clock recovery is shown in figure 19. PHO OPN OPOLT Ve (Fin 6) = (Pin2) (Fin 3) (Fin 1) LOS (Fin 10) LOSIN (Fin 5) alates © late © leleiatel nitaieiaiets © tek hale © siete
1.544 Mis NRZ J}: 24704 Me
DATAIN (Fin 7) 1 NERO HO OUT (Pin5) 1544 MHe 5 | 1.544 Me CLKIN (Fin 9) | ‘ S OUT? (Fin 13} ! TRUOS0 | = = = a _ fr rrr ccc ol RCLK (Fin 11) = RDATA(Pin 12) Figure 19, Frequency Translation The TRU-050 is most commonly used for frequency translation. For example, in a telecommunications application, when a 2.048 MHz reference clock is multiplied to 32.768 MHz, a very clean 32.768 MHz clock would then be output to other circuits. Generally, the [RU-050 Is specified in terms of NRZ input. Since the [RU-050's phase detector was designed for NRZ data, other inputs such as a clock signal should be considered as an equivalent 1010...NRZ pattern. 14 of 17 Vectron International = 267 Lowell Road, Hudson, NH 03051 _Tel: 1-88-VECTRON-1 e-mail: vectron@vectron.com
If the DATAIN input to the phase detector is a clock signal, the VCXO, or the divided VCXO output fed back to CLKIN, must be twice the DATAIN rate. In figure 20, the 2.048 MHz system reference clock can be treated as a 4.096 MHz NRZ data stream with a data density of 100%. Therefore, the feedback frequency in the PLL would be 4.096 MHz (the 32.768 MHz clock frequency divided by 8). PHO OPN = OPOUT Ve . LOS (Fin "t (Pin 6) (Fin) (Fin 3) (Pint) | LOSIN (Pin §j We ee ae 0768 Me DATAIN (Pin #) : ORG @— OUT (Fin 15 — Phas & Loop Fitter " Detentice On amp
4096 MHe § 4096 MHe
CLEIN (Fin 9} Divide by 8 OUT2 (Fin 13: | | Can | get ROLK Fin 1) RDATA Fn 12 Figure 20. application assistance? 208 bf 32768 ot “LOLOL OL ALLL a Absolutely! Just call The Timing diagram abowe shows a 2.046 MHe clock input being translated to 32.720 WHE clock output. 1- 89. VECTRON J Figure 21. Another example would be to translate 8.000 kHz to 51.840 Mhz. PHO OPN OPOUT Ve LOS (Pin 10). (Pin 6) (Pin 2) (Pin 3) (Pin 1) — LOSIN (Pin 5) 6 (UNO kis | eSecuesseSSeesicsicschcsSocehceuee cca cr cn tz DATAN PI J voxo “ee a Phase Loop Fitter " Detector Op-om p 3.240 WHz RCLK (Pin 11} RDATA (Pin 12) Figure 22. Vectron International + 267 Lowell Road, Hudson, NH 03051 _Tel: 1-88-VECTRON-1 e-mail: vectron@vectron.com 15 of 17
For applications where the DATAIN is very low in frequency (roughly <200 kHz), clock information may pass through the phase detector because of its finite low pass characteristics. In applications such as this, an additional pole may be necessary in the loop filter to attenuate these AC components prior to the VCXO input (note the capacitor to ground in figure 22). Please contact Vectron’s Applications Engineering staff for further detail. Clock Smoothing Example The third common application of the [RU-050 is for the Regeneration or “Smoothing” of a degraded input clock signal. In this application, the [RU-050 accepts a degraded input clock signal and regenerates the signal to square up the rising and falling edges and remove unwanted jitter. The output is then a clean quartz locked representation of the degraded input signal. Figure 23 illustrates a common example of a clock signal regeneration application. In this example, a degraded 16.384 MHz clock signal is smoothed using the TRU-050. The 16.384 MHz clock is fed into DATAIN (Pin 7). The signal is then regenerated, and a smoothed representation of the signal is available at RDATA (Pin 11). It is important to note that the signal fed back from OUT1 (Pin 15) to CLKIN (Pin 9) is twice the frequency of the degraded input signal at DATAIN (Pin 7). This is because the TRU-050 was originally designed for input NRZ data patterns. Since an NRZ data pattern has one transition per bit, and its associated clock has two transitions per bit, the TRU-050 phase detector requires twice as many transitions at CLKIN (Pin 9) when compared to DATAIN (Pin 7). In the case of an input clock signal, CLKIN (Pin 9) must be twice the frequency of DATAIN (Pin 7). For a 16.384 MHz clock smoothing application, a TRU-O50 with a 32.768 MHz OUT should be specified. PHO OPN = 60OPOUT ON, Los [Fn 10) (iné) (Pn2) (Pins) (Pini) LOSIN (Pm 5)
16.330 MHz : 1 a Tbe Me
a OUT (Pints) DATAIN (Pin 7) ——")—t pres al | $2,768 MHz a Dee ctr OPare | esDATAIN | TRU-080 , OUT# (Pin 13) iia Pye ee ee ee Ed $2.7 6% MHz 16.3% MH2 RCLK (Pin 41) AOD ATa(Pin 12)
16.384 MHz] Degraded
DATAIN [Piri ?) ee ee ee ee Input Clock RDMTA Pin iz) “Belay Output Clock Figure 23. 16 of 17 Vectron International 267 Lowell Road, Hudson, NH 03051 _Tel: 1-88-VECTRON-1 e-mail: vectron@vectron.com
How Is It Packaged? ‘ad 7 TRUOSO Ta, LO, Figure 24, | sisao 25520 be ofa vTet f 3 i Wr 3 S028 ‘faa oa ] PUS22 ] pars Nalatatalalatalen ci BUH] Reals] |] i} NB200 . psi 25 Beh ey wi ule 6020 [ ORF L hes iG _ _ Questions? MES, U ! ‘gd F | ' Lp 2 Gull ing Figure 25. TRUOS0 G4 Loa 29. . {a vie | fF 1 | 1 1 1 1 WOT 3.58 “- imaLece ikeerey 2s] a Henos] S T rf ace ——E 7 5 BLE L Mount 030 1) 10005 07=0 1 to +s Nssaos5 BAe. 13 lirao25 * E er oe Pras NS =005 Retr er [ideal 8] TH 005 005 lial B 06208] H 0 Wi | S | [ () if d Q re d vy, Standard frequencies* (MHz) Using OUTT , 12.032 12288 12624 13.824 16000 16.128 16.384 OUT 2 Frequency Version Number 51.840 65.536 19.440 40.960 og rackage Type Standard frequencies * (MHz) Using OUT2 Absolute Pull Range 1.000 1.024 1.544 2048 3.088 3240 4032 G Surface Mount H +100 ppm 6.480 6912 7.680 8000 8192 68448 8.960 ivi E Divide by 32 0 D Divide by 16 _H Divide by 256 CUE EEE EY K OUT2 Disabled 32.768 a “Other frequencies available upon request. lable 4. Vectron International + 267 Lowell Road, Hudson, NH 03051 Tel: 1-88-VECTRON-1 — e-mail: vectron@vectron.com 17of 17