TRSF3232EIDR

TRSF3232E_V02 TI | Alldatasheet

Document overview

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Technical content

TRSF3232E 3V TO 5.5V Two-Channel RS-232 1Mbit/s Line Driver and Receiver with ±15kV IEC ESD Protection in Small Package

1 Features

• Operates with 3V to 5.5V VCC supply
• Operates up to 1Mbit/s
• Low supply current: 300μA typical
• External capacitors: 4 × 0.1μF
• Accept 5V logic input with 3.3V supply
• Latch-up performance exceeds 100mA Per JESD 78, class II
• ESD protection for RS-232 pins – ±15kV Human-Body Model (HBM) – ±15kV IEC 61000-4-2 air-gap discharge – ±8kV IEC 61000-4-2 contact discharge
• Available in near chip scale QFN (3mmx3mm) package (85% smaller than SOIC-16)

2 Applications

• Industrial PCs
• Wired networking
• Data center and enterprise computing
• Battery-powered systems
• PDAs
• Notebooks
• Palmtop PCs
• Hand-held equipment

3 Description

The TRSF3232E consists of two line drivers, two line receivers, and a dual charge-pump circuit with ±15kV ESD protection pin to pin (serial-port connection pins, including GND). This device provides the electrical interface between an asynchronous communication controller and the serial-port connector. The charge pump and four small external capacitors allow operation from a single 3V to 5.5V supply. The TRSF3232E operates at data signaling rates up to 1Mbit/s and a driver output slew rate of 14V/ μs to 150V/μs.

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) TRSF3232E D (SOIC) 9.9mm x 6mm DB (SSOP) 6.2mm x 7.8mm DW (SOIC) 10.3 mm x 10.3mm PW (TSSOP) 5mm x 6.4mm RGT (VQFN) 3mm x 3mm SOT-23-THN (DYY, 16) 4.2mm × 2mm (1) For more information, see Section 11 . (2) The package size (length × width) is a nominal value and includes pins, where applicable. DIN1 5 k 5 k DIN2 ROUT1 ROUT2 DOUT1 DOUT2 RIN1 RIN2 Logic Diagram (Positive Logic) TRSF3232E SLLS825C – AUGUST 2007 – REVISED DECEMBER 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

11 Mechanical, Packaging, and Orderable

SLLS825C – AUGUST 2007 – REVISED DECEMBER 2024 www.ti.com

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4 Pin Configuration and Functions

C1− C2+ C2− DOUT2 RIN2 VCC GND DOUT1 RIN1 ROUT1 DIN1 DIN2 ROUT2 Figure 4-1. D, DB, DW, PW or DYY Package 16-Pin SSOP, TSSOP, or SOT-23-THN (Top View) Thermal Pad 6 7 8 16 15 14 13 C1- C2+ C2- DOUT1 RIN1 ROUT1 DIN1 DOUT2 RIN2 ROUT2 DIN2 C1+ V+ V CC GND Figure 4-2. RGT, VQFN Package (Top View) Table 4-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME D, DB, DW, PW or DYY RGT C1+ 1 16 - Positive lead of C1 capacitor V+ 2 15 O Positive charge pump output for storage capacitor only C1- 3 1 - Negative lead of C1 capacitor C2+ 4 2 - Positive lead of C2 capacitor C2- 5 3 - Negative lead of C2 capacitor V- 6 4 O Negative charge pump output for storage capacitor only DOUT2 7 5 O RS232 line data output (to remote RS232 system) RIN2 8 6 I RS232 line data input (from remote RS232 system) ROUT2 9 7 O Logic data output (to UART) DIN2 10 8 I Logic data input (from UART) DIN1 11 9 I Logic data input (from UART) ROUT1 12 10 O Logic data output (to UART) RIN1 13 11 I RS232 line data input (from remote RS232 system) DOUT1 14 12 O RS232 line data output (to remote RS232 system) GRD 15 13 - Ground VCC 16 14 - Supply Voltage, Connect to external 3-V to 5.5-V power supply Thermal Pad - Thermal Pad - Exposed thermal pad. Can be connected to GND or left floating. (1) Signal Types: I = Input, O = Output, I/O = Input or Output. www.ti.com TRSF3232E SLLS825C – AUGUST 2007 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TRSF3232E

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) see note (1) MIN MAX UNIT VCC Supply voltage range(2) –0.3 6 V V+ Positive-output supply voltage range(2) –0.3 7 V V– Negative-output supply voltage range(2) 0.3 –7 V V+ – V– Supply voltage difference(2) 13 V VI Input voltage range Drivers –0.3 6 V Receivers –25 25 VO Output voltage range Drivers –13.2 13.2 V Receivers –0.3 VCC + 0.3 TJ Operating virtual junction temperature 150 °C Tstg Storage temperature range –65 150 °C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are with respect to network GND.

5.2 ESD Ratings

V (ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-0011. ±3000 V Charged-device model (CDM), per JEDEC specification JESD22-C1012 ±1500

5.3 ESD Protection, Driver

PIN NAME TEST CONDITIONS TYP UNIT DOUT1, DOUT2(2) Human-body model (HBM) ±15 kVIEC 61000-4-2 Air-Gap Discharge(1) ±15 IEC 61000-4-2 Contact Discharge(1) ±8 (1) For RGT, D and PW packages only: A minimum of 1-µF capacitor is needed between VCC and GND to meet the specified IEC ESD level . (2) For optimized IEC ESD performance for DYY package, the recommendation is to have series resistor (≥ 50Ω), on all logic inputs directly connected to power or ground, to minimize the transient currents going into or out of the logic pins.

5.4 ESD Protection, Receiver

PIN NAME TEST CONDITIONS TYP UNIT RIN1, RIN2(2) HBM ±15 kVIEC 61000-4-2 Air-Gap Discharge (1) ±15 IEC 61000-4-2 Contact Discharge (1) ±8 (1) For RGT, D and PW packages only:A minimum of 1-µF capacitor is needed between VCC and GND to meet the specified IEC ESD level. (2) For optimized IEC ESD performance for DYY package, the recommendation is to have series resistor (≥ 50Ω), on all logic inputs directly connected to power or ground, to minimize the transient currents going into or out of the logic pins. TRSF3232E SLLS825C – AUGUST 2007 – REVISED DECEMBER 2024 www.ti.com

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5.5 Recommended Operating Conditions

See note (1) MIN NOM MAX UNIT Supply voltage VCC = 3.3 V 3 3.3 3.6 V VCC = 5 V 4.5 5 5.5 VIH Driver high-level input voltage DIN VCC = 3.3 V 2 V VCC = 5 V 2.4 VIL Driver low-level input voltage DIN 0.8 V VI Driver input voltage DIN 0 5.5 V Receiver input voltage –25 25 TA Operating free-air temperature TRSF3232EI –40 85 TRSF3232EC 0 70

5.6 Thermal Information

THERMAL METRIC(1) TRSF3232E UNITPW (TSSOP) D (SOIC) DW (SOIC) DB (SSOP) RGT (VQFN) DYY (SOT-23-THN)

16 Pins 16 Pins 16 Pins 16 Pins 16 Pins 16 Pins

R θJA Junction-to-ambient thermal resistance 108.2 85.9 57 46 48.8 106.2 °C/W R θJC(top) Junction-to-case (bottom) R θJB Junction-to-board thermal ψ JT Junction-to-top ψ JB Junction-to-board R θJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A N/A 9.0 N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report.

5.7 Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS(1) MIN TYP(2) MAX UNIT ICC Supply current No load, VCC = 3.3 V or 5 V 0.3 1 mA (2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C. www.ti.com TRSF3232E SLLS825C – AUGUST 2007 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TRSF3232E

5.8 Electrical Characteristics, Driver

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS(1) MIN TYP(2) MAX UNIT VOH High-level output voltage DOUT at RL = 3 kΩ to GND, DIN = GND 5 5.5 V VOL Low-level output voltage DOUT at RL = 3 kΩ to GND, DIN = VCC –5 –5.4 V IIH High-level input current VI = VCC ±0.01 ±1 μA IIL Low-level input current VI at GND ±0.01 ±1 μA IOS (3) Short-circuit output current VCC = 3.6 V, VO = 0 V ±35 ±60 mA VCC = 5.5 V, VO = 0 V RGT package only ±35 ±60 D, DB, DW, PW packages ±35 ±90 ro Output resistance VCC, V+, and V– = 0 V, VO = ±2 V 300 10M Ω (2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C. (3) Short-circuit durations should be controlled to prevent exceeding the device absolute power dissipation ratings, and not more than one output should be shorted at a time.

5.9 Electrical Characteristics, Receiver

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS(1) MIN TYP(2) MAX UNIT VOH High-level output voltage IOH = –1 mA VCC – 0.6 VCC – 0.1 V VOL Low-level output voltage IOL = 1.6 mA 0.4 V VIT+ Positive-going input threshold voltage VCC = 3.3 V 1.5 2.4 V VCC = 5 V 1.8 2.4 VIT– Negative-going input threshold voltage VCC = 3.3 V 0.6 1.2 V VCC = 5 V 0.8 1.5 Vhys Input hysteresis (VIT+ – VIT–) 0.3 V ri Input resistance VI = ±3 V to ±25 V 3 5 7 kΩ (2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C. TRSF3232E SLLS825C – AUGUST 2007 – REVISED DECEMBER 2024 www.ti.com

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5.10 Switching Characteristics, Driver

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TEST CONDITIONS(1) MIN TYP(2) MAX UNIT Maximum data rate (see Figure 6-1 ) RL = 3 kΩ, One DOUT switching CL = 250 pF,VCC = 3 V to

4.5 V 1000

CL = 1000 pF,VCC = 3.5 V to 5.5 V 1000 tsk(p) Pulse skew(3) CL = 1000 pF, RL = 3 kΩ, Vcc= 5 V (see Figure 6-2) RGT package only 70 nsCL = 150 pF to 2500 pF, RL = 3 kΩ to 7 kΩ (see Figure 6-2) D, DB, DW, PW packages 300 SR(tr) Slew rate, transition region (see Figure 6-1) RL = 3 kΩ to 7 kΩ, CL = 150 pF to 1000 pF, VCC = 3.3 V 14 150 V/μs (2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C. (3) Pulse skew is defined as |tPLH – tPHL| of each channel of the same device.

5.11 Switching Characteristics, Reveiver

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TEST CONDITIONS(1) MIN TYP(2) MAX UNIT tPLH Propagation delay time, low- to high-level output CL = 150 pF RGT package 85 ns D, DB, DW, PW packages 300 tPHL Propagation delay time, high- to low-level output CL = 150 pF RGT package 110 ns D, DB, DW, PW packages 300 tsk(p) Pulse skew(3) RGT package 25 ns D, DB, DW, PW packages 300 (2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C. (3) Pulse skew is defined as |tPLH – tPHL| of each channel of the same device. www.ti.com TRSF3232E SLLS825C – AUGUST 2007 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TRSF3232E

5.12 Typical Characteristics

D003_SLLS825.grf Vcc (V) Driver Pulse Skew (ns) 100 110 120 Corr D002 D003 Cload=150pF Cload=250pF Cload=1000pF Figure 5-1. Driver pulse skew at TA = 25°C (RGT package) D004_SLLS825.grf VCC (V) RX Pulse Skew (ns) D004 Figure 5-2. Receiver path skew at TA = 25°C (tpHL-tpLH) (RGT package) D005_SLLS825.grf Vcc (V) Receiver Path tpHL (ns) 92.5 97.5 100 102.5 105 107.5 110 112.5 115 117.5 D005 -45 qC 25 qC 85 qC Figure 5-3. Receiver path high-to-low propagation delay, CL = 150pF (RGT package) Figure 5-4. Receiver path low-to-high propagation delay, CL = 150pF (RGT package) TRSF3232E SLLS825C – AUGUST 2007 – REVISED DECEMBER 2024 www.ti.com

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6 Parameter Measurement Information

TEST CIRCUIT VOLTAGE WAVEFORMS 0 V 3 V Output Input VOL VOH tTLH Generator (see Note B) RL RS-232 Output tTHLCL (see Note A) SR(tr) 6 V tTHL or t TLH NOTES: A. C L includes probe and jig capacitance. B. The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 /c87, 50% duty cycle, tr < 10 ns, tf < 10 ns. 1.5 V 1.5 V 3 V −3 V 3 V −3 V Figure 6-1. Driver Slew Rate TEST CIRCUIT VOLTAGE WAVEFORMS 0 V 3 V Output Input VOL VOH tPLHtPHL 50% 50% NOTES: A. C L includes probe and jig capacitance. B. The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 /c87, 50% duty cycle, tr < 10 ns, tf < 10 ns. 1.5 V 1.5 V 50 /c87 Generator (see Note B) RL RS-232 Output CL (see Note A) Figure 6-2. Driver Pulse Skew TEST CIRCUIT VOLTAGE WAVEFORMS 50 /c87 50%50% −3 V 3 V 1.5 V1.5 V Output Input VOL VOH tPHL Generator (see Note B) tPLH Output CL (see Note A) NOTES: A. C L includes probe and jig capacitance. B. The pulse generator has the following characteristics: Z O = 50 /c87, 50% duty cycle, tr < 10 ns, tf < 10 ns. Figure 6-3. Receiver Propagation Delay Times www.ti.com TRSF3232E SLLS825C – AUGUST 2007 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TRSF3232E

7 Detailed Description

7.1 Overview

The TRSF3232E device consists of two line drivers, two line receivers, and a dual charge-pump circuit with ±15kV IEC ESD protection between serial-port connection terminals and GND. The device meets the requirements of TIA/EIA-232-F and provides the electrical interface between an asynchronous communication controller and the serial-port connector. The charge pump and four small external capacitors allow operation from one 3V to 5.5V supply. The device operates at data signaling rates up to 1Mbps and a maximum of 150V/μs driver output slew rate. Outputs are protected against shorts to ground.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Power

The power block increases, inverts, and regulates voltage at V+ and V– pins using a charge pump that requires four external capacitors.

7.3.2 RS232 Driver

Two drivers interface the standard logic level to RS232 levels. Both DIN inputs must be valid high or low.

7.3.3 RS232 Receiver

Two receivers interface RS232 levels to standard logic levels. An open input results in a high output on ROUT. Each RIN input includes an internal standard RS232 load. TRSF3232E SLLS825C – AUGUST 2007 – REVISED DECEMBER 2024 www.ti.com

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7.4 Device Functional Modes

Table 7-1. Each Driver INPUT DIN(1) OUTPUT DOUT L H H L (1) H = high level, L = low level Table 7-2. Each Receiver INPUT RIN(1) OUTPUT ROUT L H H L Open H (1) H = high level, L = low level, Open = input disconnected or connected driver off 7.4.1 VCC Powered by 3V to 5.5V The device is in normal operation.

7.4.2 VCC Unpowered, VCC = 0V

When the TRS3232 device is unpowered, it can be safely connected to an active remote RS232 device. www.ti.com TRSF3232E SLLS825C – AUGUST 2007 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TRSF3232E

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The TRSF3232E device is designed to convert single-ended signals into RS232-compatible signals, and vice- versa. This device can be used in any application where an RS232 line driver or receiver is required. ROUT and DIN connect to UART or general-purpose logic lines. RIN and DOUT lines connect to a RS232 connector or cable.

8.2 Typical Application

−C3 VCC C2+ C1+ GND C1− ROUT1 C2− CBYPASS = 0.1 /c109F RIN2 C4+ DOUT1 DOUT2 5 k/c87 5 k/c87 A. C3 can be connected to VCC or GND. Figure 8-1. Typical Operating Circuit and Capacitor Values Table 8-1. VCC vs Capacitor Values VCC C1 C2, C3, C4 3.3V ± 0.3V 0.1µF 0.1µF 5V ± 0.5V 0.047µF 0.33µF 3V to 5.5V 0.1µF 0.47µF TRSF3232E SLLS825C – AUGUST 2007 – REVISED DECEMBER 2024 www.ti.com

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8.2.1 Design Requirements

• Recommended VCC is 3.3V or 5V – 3V to 5.5V is also possible
• Maximum recommended bit rate is 250kbites

8.2.2 Detailed Design Procedure

All DIN inputs must be connected to valid low or high logic levels. Select capacitor values based on VCC level for best performance.

8.2.3 Application Performance Plots

VCC must be between 3 V and 5.5 V. Charge pump capacitors must be chosen using Table 8-1 Figure 8-2. 1Mbps timing waveform from driver input to receiver output loopback. DOUT to RIN trace is in purple, DIN trace is in yellow and ROUT trace is in pink

8.3 Power Supply Recommendations

The supply voltage, VCC, should be between 3V and 5.5V. Select the charge-pump capacitors using Table 8-1.

8.4 Layout

8.4.1 Layout Guidelines

Keep the external capacitor traces short, specifically on the C1 and C2 nodes that have the fastest rise and fall times. www.ti.com TRSF3232E SLLS825C – AUGUST 2007 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TRSF3232E

8.4.2 Layout Example

0.1µF C1+ C1– C2+ C2– DOUT2 RIN2 VCC GND DOUT1 RIN1 ROUT1 DIN1 DIN2 ROUT2 Figure 8-3. Layout Diagram TRSF3232E SLLS825C – AUGUST 2007 – REVISED DECEMBER 2024 www.ti.com

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9 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below.

9.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (June 2021) to Revision C (December 2024) Page Changes from Revision A (December 2020) to Revision B (June 2021) Page

• Changed the table note in the ESD Protection, Reciever table to make it applicable to D and PW packages.. 4 Changes from Revision * (August 2007) to Revision A (December 2020) Page
• Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device www.ti.com TRSF3232E SLLS825C – AUGUST 2007 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TRSF3232E

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. TRSF3232E SLLS825C – AUGUST 2007 – REVISED DECEMBER 2024 www.ti.com

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www.ti.com 25-Dec-2024 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TRSF3232ECDBR ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 RT32EC Samples TRSF3232ECDR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TRSF3232EC Samples TRSF3232ECDWR OBSOLETE SOIC DW 16 TBD Call TI Call TI 0 to 70 TRSF3232EC TRSF3232ECPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 RT32EC Samples TRSF3232EID OBSOLETE SOIC D 16 TBD Call TI Call TI -40 to 85 TRSF3232EI TRSF3232EIDBR ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 RT32EI Samples TRSF3232EIDR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TRSF3232EI Samples TRSF3232EIDW ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TRSF3232EI Samples TRSF3232EIDWR ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TRSF3232EI Samples TRSF3232EIDYYR ACTIVE SOT-23-THIN DYY 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 RT32EI Samples TRSF3232EIPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 RT32EI Samples TRSF3232EIRGTR ACTIVE VQFN RGT 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 F3232 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1

www.ti.com 25-Dec-2024 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Dec-2024 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TRSF3232EIDYYR SOT-23- THIN Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Dec-2024 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TRSF3232ECDBR SSOP DB 16 2000 356.0 356.0 35.0 TRSF3232ECDR SOIC D 16 2500 356.0 356.0 35.0 TRSF3232ECDR SOIC D 16 2500 356.0 356.0 35.0 TRSF3232ECPWR TSSOP PW 16 2000 356.0 356.0 35.0 TRSF3232EIDBR SSOP DB 16 2000 356.0 356.0 35.0 TRSF3232EIDR SOIC D 16 2500 356.0 356.0 35.0 TRSF3232EIDR SOIC D 16 2500 356.0 356.0 35.0 TRSF3232EIDWR SOIC DW 16 2000 350.0 350.0 43.0 TRSF3232EIDYYR SOT-23-THIN DYY 16 3000 336.6 336.6 31.8 TRSF3232EIPWR TSSOP PW 16 2000 356.0 356.0 35.0 TRSF3232EIPWR TSSOP PW 16 2000 356.0 356.0 35.0 TRSF3232EIRGTR VQFN RGT 16 3000 367.0 367.0 35.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Dec-2024 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) TRSF3232EIDW DW SOIC 16 40 506.98 12.7 4826 6.6 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C 16X 0.30 0.18 1.68 0.07 16X 0.5 0.3 1.0 0.8 (DIM A) TYP 0.05 0.00 12X 0.5 1.5 A 3.1 2.9 B 3.1 2.9 VQFN - 1 mm max heightRGT0016C PLASTIC QUAD FLATPACK - NO LEAD 4222419/D 04/2022 SIDE WALL METAL THICKNESS DIM A OPTION 1 OPTION 2 0.1 0.2 PIN 1 INDEX AREA 0.08 SEATING PLANE 5 8 16 13 (OPTIONAL) PIN 1 ID 0.1 C A B 0.05 EXPOSED THERMAL PAD SYMM SYMM NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 3.600

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

16X (0.24) 16X (0.6) ( 0.2) TYP VIA 12X (0.5) (2.8) (2.8) (0.58) TYP ( 1.68) (R0.05) ALL PAD CORNERS (0.58) TYP VQFN - 1 mm max heightRGT0016C PLASTIC QUAD FLATPACK - NO LEAD 4222419/D 04/2022 SYMM 5 8 1316 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METAL SOLDER MASK OPENINGSOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN 16X (0.6) 16X (0.24) 12X (0.5) (2.8) (2.8) ( 1.55) (R0.05) TYP VQFN - 1 mm max heightRGT0016C PLASTIC QUAD FLATPACK - NO LEAD 4222419/D 04/2022 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM ALL AROUND METAL SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 17: 85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:25X SYMM 5 8 1316

www.ti.com PACKAGE OUTLINE C 14X 0.65 4.55 16X 0.30 0.19 TYP6.6 6.2

1.2 MAX

0.15 0.05 0.25 GAGE PLANE -80 B NOTE 4 4.5 4.3 A NOTE 3 5.1 4.9 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/A 02/2017

0.1 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 8 9 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 8 9

www.ti.com PACKAGE OUTLINE C 14X 0.65 4.55 16X 0.38 0.22 8.2

7.4 TYP

0.25 GAGE PLANE 0 -8

2 MAX

0.25 0.09 B 5.6 5.0 NOTE 4 A 6.5 5.9 NOTE 3 0.95 0.55 SSOP - 2 mm max heightDB0016A SMALL OUTLINE PACKAGE 4220763/A 05/2022 0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-150. A 15 DETAIL A TYPICAL SCALE 1.500

www.ti.com EXAMPLE BOARD LAYOUT 16X (1.85) 16X (0.45) 14X (0.65) (7) (R0.05) TYP SSOP - 2 mm max heightDB0016A SMALL OUTLINE PACKAGE 4220763/A 05/2022 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 8 9 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 16X (1.85) 16X (0.45) 14X (0.65) (7) (R0.05) TYP SSOP - 2 mm max heightDB0016A SMALL OUTLINE PACKAGE 4220763/A 05/2022 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 8 9

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.50 per side. 5. Reference JEDEC Registration MO-345, Variation AA PACKAGE OUTLINE 4224642/D 07/2024 www.ti.com SOT-23-THIN - 1.1 mm max height PLASTIC SMALL OUTLINE DYY0016A A 0.1 C B PIN 1 INDEX AREA 4.3 4.1 NOTE 3 2.1 1.9 3.36 3.16 14X 0.5 3.5 16X 0.3 0.11

1.1 MAX

C SEATING PLANE 0.2

0.08 TYP

0.1 0.0 0.25 GAUGE PLANE 0°- 8° 0.63 0.33 DETAIL A TYP 4X 0° - 15° 4X 4° - 15°

NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. EXAMPLE BOARD LAYOUT 4224642/D 07/2024 www.ti.com SOT-23-THIN - 1.1 mm max heightDYY0016A PLASTIC SMALL OUTLINE SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X 16X (0.3) 16X (1.05) (3) 14X (0.5) (R0.05) TYP 8 9 METAL SOLDER MASK OPENING SOLDER MASK OPENING METAL UNDER SOLDER MASK NON- SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS

NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. EXAMPLE STENCIL DESIGN 4224642/D 07/2024 www.ti.com SOT-23-THIN - 1.1 mm max heightDYY0016A PLASTIC SMALL OUTLINE SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 20X SYMM SYMM 16X (0.3) 16X (1.05) (3) 14X (0.5) (R0.05) TYP 8 9

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. SOIC - 2.65 mm max heightDW 16 SMALL OUTLINE INTEGRATED CIRCUIT7.5 x 10.3, 1.27 mm pitch 4224780/A

www.ti.com PACKAGE OUTLINE C TYP10.63 9.97

2.65 MAX

14X 1.27 16X 0.51 0.31 8.89 TYP0.33 0.10 0 - 8 0.3 0.1 (1.4) 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 10.5 10.1 B NOTE 4 7.6 7.4 4220721/A 07/2016 SOIC - 2.65 mm max heightDW0016A SOIC NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side. 5. Reference JEDEC registration MS-013. 1 16

0.25 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.500

www.ti.com EXAMPLE BOARD LAYOUT (9.3) 14X (1.27) R0.05 TYP 16X (2) 16X (0.6) 4220721/A 07/2016 SOIC - 2.65 mm max heightDW0016A SOIC NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS OPENING SOLDER MASK METAL SOLDER MASK DEFINED LAND PATTERN EXAMPLE SCALE:7X SYMM 8 9 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN R0.05 TYP 16X (2) 16X (0.6) 14X (1.27) (9.3) 4220721/A 07/2016 SOIC - 2.65 mm max heightDW0016A SOIC NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:7X SYMM SYMM 8 9

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