TRSF3221ECDB

TRSF3221E_V02 TI | Alldatasheet

Document overview

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Technical content

TRSF3221E 3V to 5.5V Single-Channel RS-232 1Mbit Line Driver and Receiver With ±15kV IEC ESD Protection in Small Package

1 Features

• ESD protection for RS-232 pins – ±15kV Human-body model (HBM) – ±8kV IEC 61000-4-2 Contact discharge – ±15kV IEC 61000-4-2 Air-gap discharge
• Operates with 3V to 5.5V VCC supply
• Operates up to 1Mbit/s – Low-speed pin-compatible device (250kbit/s) – TRS3221E
• Available in near chip-scale package, 16-pin VQFN (RGT, 82% smaller than TSSOP package)
• Low standby current: 1μA typical
• External capacitors : 4 × 0.1μF
• Accepts 5V logic input with 3.3V supply
• Auto-powerdown feature automatically disables drivers for power savings

2 Applications

• Industrial PCs
• Wired networking
• Data center and enterprise computing
• Battery-powered systems
• PDAs
• Notebooks
• Laptops
• Palmtop PCs
• Hand-held equipment

3 Description

The TRSF3221E consists of one line driver, one line receiver, and a dual charge-pump circuit with ±15kV IEC ESD protection pin to pin (serial-port connection pins, including GND). The TRSF3221E provides the electrical interface between an asynchronous communication controller and the serial-port connector. The charge pump and four small external capacitors allow operation from a single 3V to 5.5V supply. The TRSF3221E operates at data signaling rates up to 1Mbit/s and a driver output slew rate of 24V/μs to 150V/μs. Flexible control options for power management are available when the serial port is inactive. The auto- powerdown feature functions when FORCEON is low and FORCEOFF is high. During this mode of operation, if the TRSF3221E does not sense a valid RS-232 signal on the receiver input, the driver output is disabled. If FORCEOFF is set low and the enable (EN) input is high, both the driver and receiver are shut off, and the supply current is reduced to 1μA. Disconnecting the serial port or turning off the peripheral drivers causes the auto-powerdown condition to occur. Auto-powerdown can be disabled when FORCEON and FORCEOFF are high. With auto-powerdown enabled, the device is activated automatically when a valid signal is applied to the receiver input. The INVALID output notifies the user if an RS-232 signal is present at the receiver input. INVALID is high (valid data) if the receiver input voltage is greater than 2.7V or less than –2.7V, or has been between –0.3V and 0.3V for less than 30 μs. INVALID is low (invalid data) if the receiver input voltage is between –0.3V and 0.3V for more than 30μs. See Figure 6-5 for receiver input levels.

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) TRSF3221E DB (SSOP) 6.2mm x 5.3mm PW (TSSOP) 5mm x 4.4mm RGT (VQFN) 3mm x 3mm SOT-23-THN (DYY, 16) 4.2mm × 2mm (1) For more information, see Section 11. (2) The package size (length × width) is a nominal value and includes pins, where applicable. DIN DOUT Auto-powerdown INV ALID RIN FORCEOFF FORCEON ROUT EN 1 1 Logic Diagram (Positive Logic) TRSF3221E SLLS822C – JULY 2007 – REVISED DECEMBER 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

11 Mechanical, Packaging, and Orderable

SLLS822C – JULY 2007 – REVISED DECEMBER 2024 www.ti.com

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4 Pin Configuration and Functions

C1− C2+ C2− EN RIN VCC FORCEOFF GND DOUT FORCEON DIN INV ALID ROUT DB or PW Package. 16 Pins (Top View) Thermal Pad 6 7 8 16 15 14 13 EN C1+ C1- FORCEON DIN INVALID ROUT C2+ C2- RIN FORCEOFF GND VCC DOUT Table 4-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME DB or PW RGT EN 1 14 -- Low input enables receiver ROUT output. High input sets ROUT to high impedance. C1+ 2 16 - Positive lead of C1 capacitor V+ 3 15 O Positive charge pump output for storage capacitor only C1- 4 1 - Negative lead of C1 capacitor C2+ 5 2 - Positive lead of C2 capacitor C2- 6 3 - Negative lead of C2 capacitor V- 7 4 O Negative charge pump output for storage capacitor only RIN 8 5 I RS232 line data input (from remote RS232 system) ROUT 9 6 O Logic data output (to UART) INVALID 10 7 Invalid output pin. Output low when RIN input is unpowered. DIN 11 8 I Logic data input (from UART) FORCEON 12 9 Automatic power-down control input DOUT 13 10 O RS232 line data output (to remote RS232 system) GRD 14 11 - Ground VCC 15 12 - Supply Voltage, Connect to external 3V to 5.5V power supply FORCEOFF 16 13 Automatic power-down control input Thermal Pad - Yes - Exposed thermal pad. Can be connected to GND or left floating. (1) Signal Types: I = Input, O = Output, I/O = Input or Output. www.ti.com TRSF3221E SLLS822C – JULY 2007 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TRSF3221E

4C1– 13 DOUT 5C2+ 12 FORCEON 6C2– 11 DIN 7V– 10 INVALID 8RIN 9 ROUT Not to scale Figure 4-1. DYY Package 16-Pin SOT-23-THN (Top View) Table 4-2. Pin Functions PIN TYPE DESCRIPTION NAME NO. EN 1 I Low input enables receiver ROUT output. High input sets ROUT to high impedance. C1+ 2 — Positive terminals of the voltage-doubler charge pump capacitors V+ 3 O 5.5V supply generated by the charge pump C1– 4 — Negative terminals of the voltage-doubler charge pump capacitors C2+ 5 Positive terminals of the voltage-doubler charge pump capacitors C2– 6 Negative terminals of the voltage-doubler charge pump capacitors V– 7 O –5.5V supply generated by the charge pump RIN 8 I RS-232 receiver input ROUT 9 O Receiver output INVALID 10 O Invalid output pin. Output low when RIN input is unpowered. DIN 11 I Driver input FORCEON 12 I Automatic power-down control input DOUT 13 O RS-232 driver output GND 14 — Ground VCC 15 — 3V to 5.5V supply voltage FORCEOFF 16 I Automatic power-down control input TRSF3221E SLLS822C – JULY 2007 – REVISED DECEMBER 2024 www.ti.com

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5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)See (1) MIN MAX UNIT VCC Supply voltage range(2) –0.3 6 V V+ Positive output supply voltage range(2) –0.3 7 V V– Negative output supply voltage range(2) 0.3 –7 V V+ – V– Supply voltage difference(2) 13 V VI Input voltage range Driver ( FORCEOFF, FORCEON, EN) –0.3 6 V Receiver –25 25 VO Output voltage range Driver –13.2 13.2 V Receiver ( INVALID) –0.3 VCC + 0.3 TJ Operating virtual junction temperature 150 °C Tstg Storage temperature range –65 150 °C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are with respect to network GND.

5.2 ESD Ratings

V (ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±3000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 ESD Ratings, IEC Specifications

PIN NAME TEST CONDITIONS VALUE UNIT RIN, DOUT(2) HBM ±15,000 VIEC 61000-4-2 Contact Discharge(1) (2) ±8,000 IEC 61000-4-2 Air-Gap Discharge(1) (2) ±15,000 (1) For the RGT and PW package only, a minimum of 1µF capacitor is required between VCC and GND to meet the specified IEC-ESD level. (2) For optimized IEC ESD performance for DYY package, the recommendation is to have series resistor (≥ 50Ω), on all logic inputs directly connected to power or ground, to minimize the transient currents going into or out of the logic pins. www.ti.com TRSF3221E SLLS822C – JULY 2007 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TRSF3221E

5.4 Recommended Operating Conditions

See Figure 8-1 and (1) MIN NOM MAX UNIT Supply voltage VCC = 3.3 V 3 3.3 3.6 V VCC = 5 V 4.5 5 5.5 VIH Driver and control high-level input voltage DIN, FORCEOFF, FORCEON, EN VCC = 3.3 V 2 V VCC = 5 V 2.4 VIL Driver and control low-level input voltage DIN, FORCEOFF, FORCEON, EN 0.8 V VI Driver and control input voltage DIN, FORCEOFF, FORCEON 0 5.5 V VI Receiver input voltage –25 25 V TA Operating free-air temperature TRSF3221EI –40 85 TRSF3221EC 0 70

5.5 Thermal Resistance Characteristics

THERMAL METRIC(1) TRSF3221E UNITDB (SSOP) PW (TSSOP) RGT (VQFN) DYY (SOT-23-THN)

16 Pins 16 Pins 16 Pins 16 Pins

R θJA Junction-to-ambient thermal resistance 82 110.9 58.8 119.8 °C/W R θJC(top) Junction-to-case (top) thermal resistance 45.7 41.7 55.8 56.5 °C/W R θJB Junction-to-board thermal resistance 44.4 57.2 23.8 51.5 °C/W ψ JT Junction-to-top characterization parameter 11.0 4.2 1.7 2.6 °C/W ψ JB Junction-to-board characterization parameter 43.8 56.6 23.7 51.1 °C/W R θJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A 9 N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report.

5.6 Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 8-1) PARAMETER TEST CONDITIONS(1) MIN TYP(2) MAX UNIT II Input leakage current FORCEOFF, FORCEON, EN ±0.01 ±1 μA ICC Supply current (TA = 25°C) Auto-powerdown disabled No load, FORCEOFF and FORCEON at VCC 0.3 1 mA Powered off No load, FORCEOFF at GND 1 10 μA Auto-powerdown enabled No load, FORCEOFF at VCC, FORCEON at GND, All RIN are open or grounded 1 10 (2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C. TRSF3221E SLLS822C – JULY 2007 – REVISED DECEMBER 2024 www.ti.com

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5.7 Electrical Characteristics, Driver

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 8-1) PARAMETER TEST CONDITIONS(1) MIN TYP(2) MAX UNIT VOH High-level output voltage DOUT at RL = 3 kΩ to GND, DIN = GND 5 5.4 V VOL Low-level output voltage DOUT at RL = 3 kΩ to GND, DIN = VCC –5 –5.4 V IIH High-level input current VI = VCC ±0.01 ±1 μA IIL Low-level input current VI at GND ±0.01 ±1 μA IOS Short-circuit output current(3) VCC = 3.6 V, VO = 0 V ±35 ±60 mA VCC = 5.5 V, VO = 0 V ±35 ±90 ro Output resistance VCC, V+, and V– = 0 V, VO = ±2 V 300 10M Ω Ioff Output leakage current FORCEOFF = GND VO = ±12 V, VCC = 3 V to 3.6 V ±25 μA VO = ±10 V, VCC = 4.5 V to 5.5 V ±25 (2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C. (3) Short-circuit durations must be controlled to prevent exceeding the device absolute power dissipation ratings, and not more than one output can be shorted at a time.

5.8 Switching Characteristics, Driver

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 8-1) PARAMETER TEST CONDITIONS(1) MIN TYP(2) MAX UNIT Maximum data rate (see Figure 6-1 ) RL = 3 kΩ CL = 1000 pF 250 kbit/sCL = 250 pF, VCC = 3 V to 4.5 V 1000 CL = 1000 pF, VCC = 4.5 V to 5.5 V 1000 tsk(p) Pulse skew(3) CL = 250 pF RL = 3 kΩFigure 6-2 RGT Package 25 ns CL = 150 pF to 2500 pF, RL = 3 kΩ to 7 kΩ, See Figure 6-2 DB or PW package 100 SR(tr) Slew rate, transition region (see Figure 6-1) VCC = 3.3 V, RL = 3 kΩ to 7 kΩ, CL = 150 pF to 1000 pF 18 150 V/μs (2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C. (3) Pulse skew is defined as |tPLH – tPHL| of each channel of the same device. www.ti.com TRSF3221E SLLS822C – JULY 2007 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TRSF3221E

5.9 Electrical Characteristics, Receiver

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 8-1) PARAMETER TEST CONDITIONS(1) MIN TYP(2) MAX UNIT VOH High-level output voltage IOH = –1 mA VCC – 0.6 V VCC – 0.1 V V VOL Low-level output voltage IOL = 1.6 mA 0.4 V VIT+ Positive-going input threshold voltage VCC = 3.3 V 1.6 2.4 V VCC = 5 V 1.9 2.4 VIT– Negative-going input threshold voltage VCC = 3.3 V 0.6 1.1 V VCC = 5 V 0.8 1.4 Vhys Input hysteresis (VIT+ – VIT–) 0.5 V Ioff Output leakage current FORCEOFF = 0 V ±0.05 ±10 μA ri Input resistance VI = ±3 V to ±25 V 3 5 7 kΩ (2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.

5.10 Switching Characteristics, Receiver

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 8-1) PARAMETER TEST CONDITIONS(1) TYP(2) UNIT tPLH Propagation delay time, low- to high-level output CL = 150 pF, See Figure 6-3 RGT package 100 ns DB or PW package 150 tPHL Propagation delay time, high- to low-level output CL = 150 pF, See Figure 6-3 RGT package 125 ns DB or PW package 150 ten Output enable time CL = 150 pF, RL = 3 kΩ, See Figure 6-4 200 ns tdis Output disable time CL = 150 pF, RL = 3 kΩ, See Figure 6-4 200 ns tsk(p) Pulse skew(3) See Figure 6-3 RGT package 25 ns DB or PW package 50 (2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C. (3) Pulse skew is defined as |tPLH – tPHL| of each channel of the same device. TRSF3221E SLLS822C – JULY 2007 – REVISED DECEMBER 2024 www.ti.com

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5.11 Electrical Characteristics, Auto-Powerdown

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 6-5) PARAMETER TEST CONDITIONS MIN MAX UNIT VT+(valid) Receiver input threshold for INVALID high-level output voltage FORCEON = GND, FORCEOFF = VCC 2.7 V VT–(valid) Receiver input threshold for INVALID high-level output voltage FORCEON = GND, FORCEOFF = VCC –2.7 V VT(invalid) Receiver input threshold for INVALID low-level output voltage FORCEON = GND, FORCEOFF = VCC –0.3 0.3 V VOH INVALID high-level output voltage IOH = –1 mA, FORCEON = GND, FORCEOFF = VCC VCC – 0.6 V VOL INVALID low-level output voltage IOL = 1.6 mA, FORCEON = GND, FORCEOFF = VCC 0.4 V

5.12 Switching Characteristics, Auto-Powerdown

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 6-5) PARAMETER TYP(1) UNIT tvalid Propagation delay time, low- to high-level output 1 μs tinvalid Propagation delay time, high- to low-level output 30 μs ten Supply enable time 100 μs (1) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.

5.13 Typical Characteristics

VCC (V) Driver Pulse Skew (ns) 100 110 120 CL = 150pF CL = 250pF CL = 1000pF Figure 5-1. Driver Pulse Skew vs Load Capacitance and Supply Voltage at TA = 25°C (RGT Package) D002_rx_tpLH.grf VCC (V) Receiver Low-to-High Propagation Delay (ns) 100 105 110 115 120 D002 -40 qC 25 qC 85 qC Figure 5-2. Receiver Path Low-to-High Propagation Delay vs TA and Supply Voltage (RGT Package) D003_rx_tpHL.grf VCC (V) Receiver High-to-Low Propagation Delay (ns) 100 105 110 115 120 125 130 135 140 145 150 D003 -40 qC 25 qC 85 qC Figure 5-3. . Receiver Path High-to-Low Propagation Delay vs TA and Supply Voltage (RGT Package) D004_rx_skew.grf VCC (V) Receiver Path Skew (| tpLH -tpHL |) (ns) D004 -40 qC 25 qC 85 qC Figure 5-4. Receiver Pulse Skew (|tpLH - tpHL|) vs TA and Supply Voltage (RGT Package) www.ti.com TRSF3221E SLLS822C – JULY 2007 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TRSF3221E

6 Parameter Measurement Information

50 Ω TEST CIRCUIT VOLTAGE WAVEFORMS −3 V−3 V

3 V3 V

(see Note B) RL 3 V FORCEOFF RS-232 Output tTHLCL (see Note A) SR(tr) /C00436 V tTHL or tTLH NOTES: A. C L includes probe and jig capacitance. B. The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr10 ns, tf ≤ 10 ns. FORCEON 3 V Figure 6-1. Driver Slew Rate 50 Ω TEST CIRCUIT VOLTAGE WAVEFORMS 0 V 3 V Output Input VOL VOH tPLH Generator (see Note B) RL 3 V FORCEOFF RS-232 Output tPHLCL (see Note A) NOTES: A. C L includes probe and jig capacitance. B. The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr10 ns, tf ≤ 10 ns. 50% 50% 1.5 V 1.5 V FORCEON 3 V Figure 6-2. Driver Pulse Skew TEST CIRCUIT VOLTAGE WAVEFORMS 50 Ω −3 V 3 V Output Input VOL VOH tPHLGenerator (see Note B) tPLH Output CL (see Note A) EN = VCC NOTES: A. C L includes probe and jig capacitance. B. The pulse generator has the following characteristics: ZO = 50 Ω , 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns. 1.5 V 1.5 V 50% 50% Figure 6-3. Receiver Propagation Delay Times TRSF3221E SLLS822C – JULY 2007 – REVISED DECEMBER 2024 www.ti.com

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TEST CIRCUIT VOLTAGE WAVEFORMS 50 ΩGenerator (see Note B)

3 V or 0 V

(S1 at GND) 3 V 0 V 0.3 V Output Input 0.3 V EN NOTES: A. C L includes probe and jig capacitance. B. The pulse generator has the following characteristics: ZO = 50 Ω , 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns. C. t PLZ and tPHZ are the same as tdis. D. t PZL and tPZH are the same as ten. 1.5 V 1.5 V 50% tPHZ (S1 at GND) tPLZ (S1 at VCC) 50% tPZL (S1 at VCC) RL VCC GND CL (see Note A) Output Figure 6-4. Receiver Enable and Disable Times www.ti.com TRSF3221E SLLS822C – JULY 2007 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TRSF3221E

50 ΩGenerator (see Note B) FORCEOFF ROUT FORCEON Auto- powerdown INVALID DOUTDIN CL = 30 pF (see Note A) ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ 2.7 V −2.7 V 0.3 V −0.3 V 0 V Valid RS-232 Level, INVALID High Indeterminate Indeterminate If Signal Remains Within This Region For More Than 30 µ s, INVALID Is Low† Valid RS-232 Level, INVALID High † Auto-powerdown disables drivers and reduces supply current to 1 µ A. NOTES: A. C L includes probe and jig capacitance. B. The pulse generator has the following characteristics: PRR = 5 kbit/s, ZO = 50 Ω , 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns. VOLTAGE WAVEFORMS 3 V2.7 V −2.7 V INVALID Output Receiver Input tvalid 0 V 0 V −3 V VCC 0 V ≈ V+ 0 V ≈ V− VCC ten 50% VCC 50% VCC 2.7 V −2.7 V 0.3 V 0.3 V tinvalid Supply Voltages EN = GND Figure 6-5. INVALID Propagation Delay Times and Driver Enabling Time TRSF3221E SLLS822C – JULY 2007 – REVISED DECEMBER 2024 www.ti.com

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7 Detailed Description

7.1 Overview

The TRSF3221E consists of one line driver, one line receiver, and a dual charge-pump circuit with ±15kV IEC ESD protection pin to pin (serial-port connection pins, including GND). The TRSF3221E provides the electrical interface between an asynchronous communication controller and the serial-port connector. The charge pump and four small external capacitors allow operation from a single 3V to 5.5V supply. The TRSF3221E operates at data signaling rates up to 1Mbit/s and a driver output slew rate of 24V/μs to 150V/μs. Flexible control options for power management are available when the serial port is inactive. The auto- powerdown feature functions when FORCEON is low and FORCEOFF is high. During this mode of operation, if the TRSF3221E does not sense a valid RS-232 signal on the receiver input, the driver output is disabled. If FORCEOFF is set low and the enable ( EN) input is high, both the driver and receiver are shut off, and the supply current is reduced to 1 μA. Disconnecting the serial port or turning off the peripheral drivers causes the auto-powerdown condition to occur. Auto-powerdown can be disabled when FORCEON and FORCEOFF are high. With auto-powerdown enabled, the device is activated automatically when a valid signal is applied to the receiver input. The INVALID output notifies the user if an RS-232 signal is present at the receiver input. INVALID is high (valid data) if the receiver input voltage is greater than 2.7V or less than –2.7V, or has been between –0.3V and 0.3V for less than 30 μs. INVALID is low (invalid data) if the receiver input voltage is between –0.3V and 0.3V for more than 30μs. Outputs are protected against shorts to ground.

7.2 Functional Block Diagram

Figure 7-1. Logic Diagram (Positive Logic)

7.3 Feature Description

The power block increases, inverts, and regulates voltage at V+ and V– pins using a charge pump that requires four external capacitors. Auto-power-down feature for driver is controlled by FORCEON and FORCEOFF inputs. Receiver is controlled by EN input. When MAX3221E is unpowered, it can be safely connected to an active remote RS-232 device. The driver interfaces the standard logic level to RS232 voltage levels. The DIN input must be valid high or low. The receiver interfaces RS-232 levels to standard logic levels. An open input results in a high output on ROUT. RIN input includes an internal standard RS-232 load. A logic high input on the EN pin shuts down the receiver output. www.ti.com TRSF3221E SLLS822C – JULY 2007 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TRSF3221E

7.4 Device Functional Modes

Functional Tables, Each Driver INPUTS(1) OUTPUT DOUT DRIVER STATUS DIN FORCEON FORCEOFF VALID RIN RS-232 LEVEL X X L X Z Powered off L H H X H Normal operation with auto-powerdown disabledH H H X L L L H Yes H Normal operation with auto-powerdown enabledH L H Yes L L L H No Z Powered off by auto-powerdown featureH L H No Z (1) H = high level, L = low level, X = irrelevant, Z = high impedance Each Receiver INPUTS(1) OUTPUT ROUTRIN EN VALID RIN RS-232 LEVEL L L X H H L X L X H X Z Open L No H (1) H = high level, L = low level, X = irrelevant, Z = high impedance (off), Open = disconnected input or connected driver off TRSF3221E SLLS822C – JULY 2007 – REVISED DECEMBER 2024 www.ti.com

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8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The TRSF3221E line driver and receiver is a specialized device for 3V to 5.5V RS-232 communication applications. This application is a generic implementation of this device with all required external components. For proper operation, add capacitors as shown in Table 8-1.

8.1.1 Typical Application

ROUT and DIN connect to UART or general purpose logic lines. FORCEON and FORCEOFFmay be connected general purpose logic lines or tied to ground or VCC. INVALID may be connected to a general purpose logic line or left unconnected. RIN and DOUT lines connect to a RS-232 connector or cable. DIN, FORCEON, and FORCEOFF inputs must not be left unconnected. CBYPASS = 0.1 /c109F Auto- powerdown FORCEOFF VCC GND C1+ C2+ C1− C2− DOUT FORCEON DIN INVALID ROUT EN RIN 5 k/c87 C3(A) A. C3 can be connected to VCC or GND. B. Resistor values shown are nominal. C. Nonpolarized ceramic capacitors are acceptable. If polarized tantalum or electrolytic capacitors are used, they must be connected as shown. Figure 8-1. Typical Operating Circuit and Capacitor Values Table 8-1. VCC vs Capacitor Values VCC C1 C2, C3, C4 3.3V ± 0.3V 0.1µF 0.1µF 5V ± 0.5V 0.047µF 0.33µF 3V to 5.5V 0.1µF 0.47µF www.ti.com TRSF3221E SLLS822C – JULY 2007 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TRSF3221E

8.1.1.1 Design Requirements

• Recommended VCC is 3.3V or 5V – 3V to 5.5V is also possible
• Maximum recommended bit rate is 1Mbps
• Use capacitors as shown in Figure 8-1 and Table 8-1

8.1.1.2 Detailed Design Procedure

For proper operation:

• DIN, FORCEOFF and FORCEON inputs must be connected to valid low or high logic levels
• Select capacitor values based on VCC level for best performance ROUT and DIN connect to UART or general purpose logic lines. FORCEON and FORCEOFF may be connected general purpose logic lines or tied to ground or VCC. INVALID may be connected to a general purpose logic line or left unconnected. RIN and DOUT lines connect to a RS232 connector or cable. DIN, FORCEON, and FORCEOFF inputs must not be left unconnected.

8.1.2 Application Performance Plot

Figure 8-2. 1 Mbps Driver to Receiver Loopback Timing Waveform, VCC = 3.3 V

8.2 Power Supply Recommendations

VCC must be between 3V and 5.5V. Charge pump capacitors must be chosen using VCC vs Capacitor Values. TRSF3221E SLLS822C – JULY 2007 – REVISED DECEMBER 2024 www.ti.com

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8.3 Layout

8.3.1 Layout Guidelines

Keep the external capacitor traces short. This is more important on C1 and C2 nodes, which have the fastest rise and fall times.

8.3.2 Layout Example

0.1 µF C1+ C1- C2+ C2- RIN VCC GND DOUT FORCEON DIN INVALID ROUT EN FORCEOFF Figure 8-3. Layout Diagram www.ti.com TRSF3221E SLLS822C – JULY 2007 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TRSF3221E

9 Device and Documentation Support

9.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (July 2021) to Revision C (December 2024) Page Changes from Revision A (May 2021) to Revision B (July 2021) Page

• Changed the table note for the ESD Ratings, IEC Specifications table to make it also applicable to Changes from Revision * (August 2007) to Revision A (May 2021) Page
• Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device TRSF3221E SLLS822C – JULY 2007 – REVISED DECEMBER 2024 www.ti.com

18 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: TRSF3221E

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TRSF3221E SLLS822C – JULY 2007 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TRSF3221E

www.ti.com 25-Dec-2024 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TRSF3221ECDB OBSOLETE SSOP DB 16 TBD Call TI Call TI 0 to 70 RT21EC TRSF3221ECDBR ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 RT21EC Samples TRSF3221ECPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 RT21EC Samples TRSF3221EIDBR ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 RT21EI Samples TRSF3221EIDYYR ACTIVE SOT-23-THIN DYY 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 RT21EI Samples TRSF3221EIPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 RT21EI Samples TRSF3221EIRGTR ACTIVE VQFN RGT 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 F3221 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1

www.ti.com 25-Dec-2024 (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Dec-2024 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TRSF3221EIDYYR SOT-23- THIN Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Dec-2024 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TRSF3221ECDBR SSOP DB 16 2000 356.0 356.0 35.0 TRSF3221ECPWR TSSOP PW 16 2000 356.0 356.0 35.0 TRSF3221EIDBR SSOP DB 16 2000 356.0 356.0 35.0 TRSF3221EIDYYR SOT-23-THIN DYY 16 3000 336.6 336.6 31.8 TRSF3221EIPWR TSSOP PW 16 2000 356.0 356.0 35.0 TRSF3221EIPWR TSSOP PW 16 2000 356.0 356.0 35.0 TRSF3221EIRGTR VQFN RGT 16 3000 367.0 367.0 35.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 14X 0.65 4.55 16X 0.30 0.19 TYP6.6 6.2

1.2 MAX

0.15 0.05 0.25 GAGE PLANE -80 B NOTE 4 4.5 4.3 A NOTE 3 5.1 4.9 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/A 02/2017

0.1 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 8 9 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 8 9

www.ti.com PACKAGE OUTLINE C 14X 0.65 4.55 16X 0.38 0.22 8.2

7.4 TYP

0.25 GAGE PLANE 0 -8

2 MAX

0.25 0.09 B 5.6 5.0 NOTE 4 A 6.5 5.9 NOTE 3 0.95 0.55 SSOP - 2 mm max heightDB0016A SMALL OUTLINE PACKAGE 4220763/A 05/2022 0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-150. A 15 DETAIL A TYPICAL SCALE 1.500

www.ti.com EXAMPLE BOARD LAYOUT 16X (1.85) 16X (0.45) 14X (0.65) (7) (R0.05) TYP SSOP - 2 mm max heightDB0016A SMALL OUTLINE PACKAGE 4220763/A 05/2022 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 8 9 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 16X (1.85) 16X (0.45) 14X (0.65) (7) (R0.05) TYP SSOP - 2 mm max heightDB0016A SMALL OUTLINE PACKAGE 4220763/A 05/2022 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 8 9

www.ti.com PACKAGE OUTLINE C 16X 0.30 0.18 1.68 0.07 16X 0.5 0.3 1.0 0.8 (DIM A) TYP 0.05 0.00 12X 0.5 1.5 A 3.1 2.9 B 3.1 2.9 VQFN - 1 mm max heightRGT0016C PLASTIC QUAD FLATPACK - NO LEAD 4222419/D 04/2022 SIDE WALL METAL THICKNESS DIM A OPTION 1 OPTION 2 0.1 0.2 PIN 1 INDEX AREA 0.08 SEATING PLANE 5 8 16 13 (OPTIONAL) PIN 1 ID 0.1 C A B 0.05 EXPOSED THERMAL PAD SYMM SYMM NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 3.600

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

16X (0.24) 16X (0.6) ( 0.2) TYP VIA 12X (0.5) (2.8) (2.8) (0.58) TYP ( 1.68) (R0.05) ALL PAD CORNERS (0.58) TYP VQFN - 1 mm max heightRGT0016C PLASTIC QUAD FLATPACK - NO LEAD 4222419/D 04/2022 SYMM 5 8 1316 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METAL SOLDER MASK OPENINGSOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN 16X (0.6) 16X (0.24) 12X (0.5) (2.8) (2.8) ( 1.55) (R0.05) TYP VQFN - 1 mm max heightRGT0016C PLASTIC QUAD FLATPACK - NO LEAD 4222419/D 04/2022 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM ALL AROUND METAL SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 17: 85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:25X SYMM 5 8 1316

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.50 per side. 5. Reference JEDEC Registration MO-345, Variation AA PACKAGE OUTLINE 4224642/D 07/2024 www.ti.com SOT-23-THIN - 1.1 mm max height PLASTIC SMALL OUTLINE DYY0016A A 0.1 C B PIN 1 INDEX AREA 4.3 4.1 NOTE 3 2.1 1.9 3.36 3.16 14X 0.5 3.5 16X 0.3 0.11

1.1 MAX

C SEATING PLANE 0.2

0.08 TYP

0.1 0.0 0.25 GAUGE PLANE 0°- 8° 0.63 0.33 DETAIL A TYP 4X 0° - 15° 4X 4° - 15°

NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. EXAMPLE BOARD LAYOUT 4224642/D 07/2024 www.ti.com SOT-23-THIN - 1.1 mm max heightDYY0016A PLASTIC SMALL OUTLINE SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X 16X (0.3) 16X (1.05) (3) 14X (0.5) (R0.05) TYP 8 9 METAL SOLDER MASK OPENING SOLDER MASK OPENING METAL UNDER SOLDER MASK NON- SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS

NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. EXAMPLE STENCIL DESIGN 4224642/D 07/2024 www.ti.com SOT-23-THIN - 1.1 mm max heightDYY0016A PLASTIC SMALL OUTLINE SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 20X SYMM SYMM 16X (0.3) 16X (1.05) (3) 14X (0.5) (R0.05) TYP 8 9

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