TRS202CDG4

TRS202 TI | Alldatasheet

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FEATURES

(TOP VIEW) 1 1 C1+ C1- C2+ C2- DOUT2 RIN2 VCC GND DOUT1 RIN1 ROUT1 DIN1 DIN2 ROUT2

APPLICATIONS

(HBM) Meets or Exceeds the Requirements of TIA/EIA-232-F and ITU v.28 Standards Operates at 5-V V CC Supply Operates up to 120 kbit/s External Capacitors 0.1 μ F Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II Battery-Powered Systems PDAs Notebooks Laptops Palmtop PCs Hand-Held Equipment The TRS202 device consists of two line drivers, two line receivers, and a dual charge-pump circuit with 15-kV ESD protection pin-to-pin (serial-port connection pins, including GND). The device meets the requirements of TIA/EIA-232-F and provides the electrical interface between an asynchronous communication controller and the serial-port connector. The charge pump and four small external capacitors allow operation from a single 5-V supply. The device operates at data signaling rates up to 120 kbit/s and a maximum of 30-V/ μ s driver output slew rate. ORDERING INFORMATION T A PACKAGE (1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP N Tube of TRS202CN PREVIEW Tube of TRS202CD SOIC D TRS202C Reel of 2500 TRS202CDR C to C Tube of TRS202CDW SOIC DW TRS202C Reel of 2000 TRS202CDWR Tube of TRS202CPW TSSOP PW RU02C Reel of 2000 TRS202CPWR PDIP N Tube of TRS202IN PREVIEW Tube of TRS202ID SOIC D TRS202I Reel of 2500 TRS202IDR C to C Tube of TRS202IDW SOIC DW TRS202I Reel of 2000 TRS202IDWR Tube of TRS202IPW TSSOP PW RU02I Reel of 2000 TRS202IPWR (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. UNLESS OTHERWISE NOTED this document contains Copyright 2007, Texas Instruments Incorporated PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com DIN1 DOUT1 RIN1ROUT1 DIN2 DOUT2 RIN2ROUT2 TRS202 5-V DUAL RS-232 LINE DRIVER/RECEIVER WITH 15-kV ESD PROTECTION SLLS808 JULY 2007 FUNCTION TABLES xxx Each Driver (1) INPUT OUTPUT DIN DOUT L H H L (1) H high level, L low level Each Receiver (1) INPUT OUTPUT RIN ROUT L H H L Open H (1) H high level, L low level, Open input disconnected or connected driver off LOGIC DIAGRAM (POSITIVE LOGIC) Submit Documentation Feedback

www.ti.com Absolute Maximum Ratings (1) Recommended Operating Conditions (1) Electrical Characteristics (1) TRS202 5-V DUAL RS-232 LINE DRIVER/RECEIVER WITH 15-kV ESD PROTECTION SLLS808 JULY 2007 over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT V CC Supply voltage range (2) 0.3 V Positive charge pump voltage range (2) V CC 0.3 V V Negative charge pump voltage range (2) 0.3 V Drivers 0.3 0.3 V I Input voltage range V Receivers Drivers V 0.3 0.3 V O Output voltage range V Receivers 0.3 V CC 0.3 DOUT Short-circuit duration DOUT Continuous D package DW package θ JA Package thermal impedance (3) (4) C/W N package PW package 108 T J Operating virtual junction temperature 150 C T stg Storage temperature range 150 C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are with respect to network GND. (3) Maximum power dissipation is a function of T J (max), θ JA and T A The maximum allowable power dissipation at any allowable ambient temperature is P D J (max) T A θ JA Operating at the absolute maximum T J of 150 C can affect reliability. (4) The package thermal impedance is calculated in accordance with JESD 51-7. See Figure MIN NOM MAX UNIT Supply voltage 4.5 5.5 V V IH Driver high-level input voltage DIN V V IL Driver low-level input voltage DIN 0.8 V Driver input voltage DIN 5.5 V I V Receiver input voltage TRS202C T A Operating free-air temperature C TRS202I (1) Test conditions are 0.1 μ F at V CC V 0.5 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure PARAMETER TEST CONDITIONS MIN TYP (2) MAX UNIT I CC Supply current No load, V CC V mA (1) Test conditions are 0.1 μ F at V CC V 0.5 (2) All typical values are at V CC and T A Submit Documentation Feedback

www.ti.com DRIVER SECTION Electrical Characteristics (1) Switching Characteristics (1) ESD Protection TRS202 5-V DUAL RS-232 LINE DRIVER/RECEIVER WITH 15-kV ESD PROTECTION SLLS808 JULY 2007 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure PARAMETER TEST CONDITIONS MIN TYP (2) MAX UNIT DOUT at R L k Ω to V OH High-level output voltage DIN GND V GND, DOUT at R L k Ω to V OL Low-level output voltage DIN V CC V GND, I IH High-level input current V I V CC 200 μ A I IL Low-level input current V I at V 200 μ A I OS (3) Short-circuit output current V CC 5.5 V O V mA r o Output resistance V CC V+, and V V O V 300 Ω (1) Test conditions are 0.1 μ F at V CC V 0.5 (2) All typical values are at V CC and T A (3) Short-circuit durations should be controlled to prevent exceeding the device absolute power dissipation ratings, and not more than one output should be shorted at a time. over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure PARAMETER TEST CONDITIONS MIN TYP (2) MAX UNIT C L to 1000 pF, R L k Ω to k Ω Maximum data rate 120 kbit/s One DOUT switching, See Figure Propagation delay time, C L 2500 pF, R L k Ω t PLH(D) μ s low- to high-level output All drivers loaded, See Figure Propagation delay time, C L 2500 pF, R L k Ω t PHL(D) μ s high- to low-level output All drivers loaded, See Figure C L 150 pF to 2500 pF, R L k Ω to k Ω t sk(p) Pulse skew (3) 300 ns See Figure Slew rate, transition region C L pF to 1000 pF, R L k Ω to k Ω SR(tr) μ s (see Figure V CC V (1) Test conditions are 0.1 μ F at V CC V 0.5 (2) All typical values are at V CC and T A (3) Pulse skew is defined as PLH t PHL of each channel of the same device. PIN TEST CONDITIONS TYP UNIT DOUT, RIN Human-Body Model (HBM) kV Submit Documentation Feedback

www.ti.com RECEIVER SECTION Electrical Characteristics (1) Switching Characteristics (1) TRS202 5-V DUAL RS-232 LINE DRIVER/RECEIVER WITH 15-kV ESD PROTECTION SLLS808 JULY 2007 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure PARAMETER TEST CONDITIONS MIN TYP (2) MAX UNIT V OH High-level output voltage I OH mA 3.5 V CC 0.4 V V OL Low-level output voltage I OL 1.6 mA 0.4 V V IT+ Positive-going input threshold voltage V CC T A C 1.7 2.4 V V IT Negative-going input threshold voltage V CC T A C 0.8 1.2 V V hys Input hysteresis IT+ V IT 0.2 0.5 V r I Input resistance V I V to V k Ω (1) Test conditions are 0.1 μ F at V CC V 0.5 (2) All typical values are at V CC V and T A over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure PARAMETER TEST CONDITIONS MIN TYP (2) MAX UNIT t PLH(R) Propagation delay time, low- to high-level output C L 150 pF 0.5 μ s t PHL(R) Propagation delay time, high- to low-level output C L 150 pF 0.5 μ s t sk(p) Pulse skew (3) 300 ns (1) Test conditions are 0.1 μ F at V CC V 0.5 (2) All typical values are at V CC V and T A (3) Pulse skew is defined as PLH t PHL of each channel of the same device. Submit Documentation Feedback

www.ti.com PARAMETER MEASUREMENT INFORMATION 50 /c87 TEST□CIRCUIT VOLTAGE□WAVEFORMS 0□V 3□V Output Input VOL VOH tPLH□(D) Generator (see□Note□B) RL RS-232 Output tPHL (D)CL (see□Note A) NOTES: A.□□□C includes□probe□and□jig□capacitance.L B. The□pulse□generator□has□the□following□characteristics:□PRR□=□120□kbit/s,□Z =□50 ,□50%□duty□cycle,□t 10□ns,□t 10□ns.O r f/c87 /c163 /c163 1.5□V 1.5□V 3□V -3□V 3□V -3□V SR(tf)□= 6V t or□tPHL(D PLH(D)) TEST□CIRCUIT VOLTAGE□WAVEFORMS 0□V 3□V Output Input VOL VOH tPLH□(D)tPHL (D) 50% 50% NOTES: A.□□□C includes□probe□and□jig□capacitance.L B. The□pulse□generator□has□the□following□characteristics:□PRR□=□120□kbit/s,□Z =□50 ,□50%□duty□cycle,□t 10□ns,□t 10□ns.O r f/c87 /c163 /c163 1.5□V 1.5□V 50 /c87 Generator (see□Note□B) RL RS-232 Output CL (see□Note A) TEST□CIRCUIT VOLTAGE□WAVEFORMS 50 /c87 50%50% -3□V 3□V 1.5□V1.5□V Output Input VOL VOH tPHL (R) Generator (see□Note□B) tPLH□(R) Output CL (see□Note A) NOTES: A.□□□C includes□probe□and□jig□capacitance.L B. The□pulse□generator□has□the□following□characteristics:□Z =□50 ,□50%□duty□cycle,□t 10□ns,□t 10□ns.O r f/c87 /c163 /c163 TRS202 5-V DUAL RS-232 LINE DRIVER/RECEIVER WITH 15-kV ESD PROTECTION SLLS808 JULY 2007 Figure Driver Slew Rate Figure Driver Pulse Skew Figure Receiver Propagation Delay Times Submit Documentation Feedback

www.ti.com APPLICATION INFORMATION ROUT2 DIN2 RIN1 DIN1 VCC C2+ C1+ GND C1- ROUT1 C2- CBYPASS =□0.1 F,/c109 RIN2 DOUT1 DOUT2 C3□can□be□connected□to□V or□GND.CC NOTES: A .□□□Resistor□values□shown□are□nominal.

0.1 F,/c109

6.3□V

0.1 F/c109

16□V 16□V 5□k/c87 5□k/c87 0.1 /c109F, 16□V B□.□□□Nonpolarized□ceramic□capacitors□are□acceptable.□If□polarized□tantalum□or□electrolytic□capacitors□are□used,□they□should□be connected□as□shown. Capacitor Selection Electrostatic Discharge (ESD) Protection TRS202 5-V DUAL RS-232 LINE DRIVER/RECEIVER WITH 15-kV ESD PROTECTION SLLS808 JULY 2007 Figure Typical Operating Circuit and Capacitor Values The capacitor type used for is not critical for proper operation. The TRS202 requires 0.1- μ F capacitors, although capacitors up to μ F can be used without harm. Ceramic dielectrics are suggested for the 0.1- μ F capacitors. When using the minimum recommended capacitor values, make sure the capacitance value does not degrade excessively as the operating temperature varies. If in doubt, use capacitors with a larger (e.g., nominal value. The capacitors' effective series resistance (ESR), which usually rises at low temperatures, influences the amount of ripple on and V Use larger capacitors (up to μ to reduce the output impedance at and V Bypass V CC to ground with at least 0.1 μ In pumps, decouple V CC to ground with a capacitor the same size as (or larger than) the charge-pump capacitors (C1 C4). TI TRS202 devices have standard ESD protection structures incorporated on the pins to protect against electrostatic discharges encountered during assembly and handling. In addition, the RS232 bus pins (driver outputs and receiver inputs) of these devices have an extra level of ESD protection. Advanced ESD structures were designed to successfully protect these bus pins against ESD discharge of kV when powered down. Submit Documentation Feedback

www.ti.com ESD Test Conditions Human-Body Model (HBM) + DUT RD 1.5□k/c87 VHBM 100□pF CS 100 150 200500 1.5 1.0 0.5 0.0 V =□2□kVHBM DUT□=□10-V,□1-/c87Zener□Diode| Time□-□ns I - ADUT Machine Model (MM) TRS202 5-V DUAL RS-232 LINE DRIVER/RECEIVER WITH 15-kV ESD PROTECTION SLLS808 JULY 2007 APPLICATION INFORMATION (continued) Stringent ESD testing is performed by TI, based on various conditions and procedures. Please contact TI for a reliability report that documents test setup, methodology, and results. The HBM of ESD testing is shown in Figure Figure shows the current waveform that is generated during a discharge into a low impedance. The model consists of a 100-pF capacitor, charged to the ESD voltage of concern, and subsequently discharged into the device under test (DUT) through a 1.5-k Ω resistor. Figure HBM ESD Test Circuit Figure Typical HBM Current Waveform The MM ESD test applies to all pins using a 200-pF capacitor with no discharge resistance. The purpose of the MM test is to simulate possible ESD conditions that can occur during the handling and assembly processes of manufacturing. In this case, ESD protection is required for all pins, not just RS-232 pins. However, after PC board assembly, the MM test no longer is as pertinent to the RS-232 pins. Submit Documentation Feedback

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TRS202CD ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202CDG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202CDR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202CDRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202CDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202CDWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202CDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202CDWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202CPW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202CPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202CPWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202CPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202ID ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202IDG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202IDR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202IDRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202IDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202IDWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202IDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202IDWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202IPW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202IPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202IPWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202IPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2007 Addendum-Page 1

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2007 Addendum-Page 2

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TRS202CDR SOIC D 16 2500 333.2 345.9 28.6 TRS202CDWR SOIC DW 16 2000 346.0 346.0 33.0 TRS202CPWR TSSOP PW 16 2000 346.0 346.0 29.0 TRS202IDR SOIC D 16 2500 333.2 345.9 28.6 TRS202IDWR SOIC DW 16 2000 346.0 346.0 33.0 TRS202IPWR TSSOP PW 16 2000 346.0 346.0 29.0 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 Pack Materials-Page 2

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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