TRF7963ARHBT

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www.ti.com SLOS758C –DECEMBER 2011–REVISED JANUARY 2013 FULLYINTEGRATED13.56-MHzRFIDREADER/WRITERIC FORISO14443A,B/NFCSTANDARDS Check forSamples: TRF7963A

1 Introduction

1.1 Features

• CompletelyIntegratedProtocolHandlingfor • Dual ReceiverArchitectureWith RSSI for ISO14443A/B,NFC Forum Device Types 1 to4, Eliminationof"Read Holes" and Adjacent and FeliCa Reader System/Ambient In-BandNoise Detection• InputVoltageRange: 2.7VDC to5.5VDC
• Programmable Power Modes forUltra-Low• Programmable Output Power: Power System Design (Power Down <0.5µA)+20 dBm (100mW) or +23 dBm (200mW)
• Parallelor SPI Interface• Programmable I/OVoltageLevels: 1.8VDC to5.5VDC • IntegratedVoltageRegulatorfor MicrocontrollerSupply• Programmable System Clock Frequency Output (RF,RF/2,RF/4) • Temperature Range: -25°C to85°C
• Programmable ModulationDepth • 32-PinQFN Package (5mm x 5 mm) (RHB)

1.2 Applications

• Secure Access Control
• DigitalDoor Lock
• ContactlessPayment Systems
• TransportTicketing
• ePassportReader Systems

1.3 Description

The TRF7963A is an integratedanalog frontend and data-framingdevice fora 13.56-MHz RFID reader/writersystem.Built-inprogramming optionsmake itsuitablefora wide range of applicationsfor proximityidentificationsystems. The readerisconfiguredby selectingthe desiredprotocolinthe controlregisters.Directaccess to all controlregistersallowsfinetuningofvariousreaderparametersas needed. Comprehensivedocumentation,referencedesigns,evaluationmodules,and TImicrocontrollers(basedon MSP430 ™ orARM ™ technology)sourcecode areavailable. The TRF7963A isa high-performance13.56-MHz HF RFID readerIC comprisingan integratedanalog frontend (AFE) and a built-indataframingengineforISO14443A/B and FeliCa.Itsupportsdataratesup to848 kbps forISO14443 withallframingand synchronizationtaskson board(inISO Mode, default).The TRF7963A alsosupportsNFC Forum Tag Types 1, 2, 3, and 4 operations(as reader/writeronly).This architectureenables the customer to builda complete and cost-effectiveyet high-performanceHF RFID/NFC reader/writerusinga low-costmicrocontroller(forexample,an MSP430). Otherstandardsand even custom protocolscan be implementedby usingtwo oftheDirectModes the deviceoffers.These DirectModes (0and 1)allowtheusertofullycontroltheanalogfrontend (AFE) and alsogainaccess to the raw subcarrierdata or the unframed,but alreadyISO formatteddata and the associated(extracted)clocksignal. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2MSP430 isa trademarkofTexas Instruments. 3ARM isa trademarkofARM Limited. PRODUCTION DATA informationiscurrentas ofpublicationdate.Productsconformto Copyright© 2011–2013,Texas InstrumentsIncorporatedspecificationsper the terms of the Texas Instrumentsstandardwarranty.Production processingdoes notnecessarilyincludetestingofallparameters.

RX_IN1 RX_IN2 Phase and Amplitude Detector Gain RSSI (AUX) Logic State Control Logic (Control Registers, Command Logic) 12-Byte FIFO MCU Interface VDD _I/O I/O_0 I/O_1 I/O_2 I/O_3 I/O_4 I/O_5 I/O_6 I/O_7 IRQ SYS_CLK DATA _CLK ISO Protocol Handling Decoder RSSI (External) Gain RSSI (Main) Filter, AGC Digitizer Bit FramingFraming Serial Conversion CRC, Parity Transmitter Analog Front EndTX_ OUT VDD_PA VSS_PA Digital Control State Machine Crystal Oscillator Timing System EN EN2 ASK/ OOK MOD OSC_IN OSC_ OUT Voltage Supply Regulator Systems (Supply Regulators, Reference Voltages) VSS_A VSS_RF VDD _RF VDD_X VSS_D VSS VIN VDD _A BAND _GAP Phase and Amplitude Detector Level Shifter TRF7963A SLOS758C –DECEMBER 2011–REVISED JANUARY 2013 www.ti.com Figure1-1.Block Diagram The receiversystem has a dual-inputreceiverarchitecture.The receiversalsoincludevariousautomatic and manual gaincontroloptions.The receivedinputbandwidthcan be selectedtocovera broadrangeof inputsubcarriersignaloptions. The receivedsignalstrengthfrom transponders,ambientsourcesor internallevelsisavailableviathe RSSI register.The receiveroutputis selectableamong a digitizedsubcarriersignaland any of the integratedsubcarrierdecoders.The selectedsubcarrierdecoderdeliversthedatabitstreamand thedata clockas outputs. The TRF7963A includesa receiverframingengine.ThisreceiverframingengineperformstheCRC and/or paritycheck,removes theEOF and SOF settings,and organizesthedatainbytesforISO14443A/B and NFC Forum protocols.Framed dataisthenaccessibletothemicrocontroller(MCU) viaa 12-byteFIFO register. A parallelor serialinterface(SPI)can be used forthe communicationbetween the MCU and the TRF7963A reader.When the built-inhardware encodersand decodersare used,transmitand receive functionsuse a 12-byteFIFO register.For directtransmitor receivefunctions,theencodersor decoders can be bypassed so the MCU can process the data in realtime.The TRF7963A supportsdata communicationlevelsfrom1.8V to5.5V fortheMCU I/Ointerface.The transmitterhas selectableoutput power levelsof100 mW (+20 dBm) or200 mW (+23 dBm) equivalentintoa 50-Ω loadwhen usinga 5-V supply.

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(MSP430/ARM) Matching VDD_X VDD_I/O TX_OUT RX_IN 1 RX_IN 2 VSS VIN Parallel or SPI Supply 2.7 V to 5.5 V VDD VDD Crystal

13.56 MHz

www.ti.com SLOS758C –DECEMBER 2011–REVISED JANUARY 2013 Figure1-2.ApplicationBlock Diagram The transmittersupportsOOK and ASK modulationwithselectablemodulationdepth.The TRF7963A includesa datatransmissionenginethatsupportsmodifiedMillerencodingforISO14443A/B and FeliCa. IncludedwiththetransmitdatacodingistheautomaticgenerationofStartOf Frame (SOF),End Of Frame (EOF),CyclicRedundancy Check (CRC), and paritybits.Severalintegratedvoltageregulatorsensurea properpower-supplynoiserejectionforthecompletereadersystem.The built-inprogrammable auxiliary voltageregulatorVDD_X (pin32)deliversup to20 mA tosupplya microcontrollerand additionalexternal circuitswithinthereadersystem. Table1-1.Supported Protocols Supported Protocols Device ISO14443A/B NFC Forum Types 1 to4106 kbps 212 kbps 424 kbps 848 kbps

1.4 OrderingInformation

Packaged Devices(1) Package Type (2) TransportMedia Quantity TRF7963ARHBT 250 RHB-32 Tape and Reel TRF7963ARHBR 3000 (1) Forthemost currentpackage and orderinginformation,see thePackage OptionAddendum attheend ofthisdocument,orsee theTI Web siteatwww.ti.com. (2) Package drawings,standardpackingquantities,thermaldata,symbolization,and PCB designguidelinesareavailableat www.ti.com/sc/package. Copyright© 2011–2013,Texas InstrumentsIncorporated Introduction 3 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

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I/O_6 I/O_5 I/O_4 I/O_3 I/O_2 I/O_1 I/O_0 I/O_7 RHB PACKAGE (TOP VIEW) VIN VDD_RF VDD_PA TX_OUT VSS_PA VSS_RX RX_IN1 VDD_A OSC_IN OSC_OUT VSS_D EN SYS_CLK DATA_CLK EN2VDD_X VSSBG ASK/OOK IRQMOD VSS_AVDD_I/ORX_IN2 9 10 11 13 1412 15 16 32 31 30 28 2729 26 25 Thermal Pad (Connect to Ground) TRF7963A www.ti.com SLOS758C –DECEMBER 2011–REVISED JANUARY 2013

2 PhysicalCharacteristics

2.1 Device Pinout

Figure2-1.TRF7963A Pin Assignment

2.2 TerminalFunctions

Table2-1.TerminalFunctions Terminal Type (1) Description Name No. VDD_A 1 OUT Internalregulatedsupply(2.7V to3.4V) foranalogcircuitry VIN 2 SUP Externalsupplyinputtochip(2.7V to5.5V) VDD_RF 3 OUT Internalregulatedsupply(2.7V to5 V);normallyconnectedtoVDD_PA (pin4) VDD_PA 4 INP SupplyforPA; normallyconnectedexternallytoVDD_RF (pin3) TX_OUT 5 OUT RF output(selectableoutputpower:100 mW or200 mW, withVDD = 5 V) VSS_PA 6 SUP NegativesupplyforPA; normallyconnectedtocircuitground VSS_RX 7 SUP Negativesupplyforreceiveinputs;normallyconnectedtocircuitground RX_IN1 8 INP Main receiveinput RX_IN2 9 INP Auxiliaryreceiveinput VSS 10 SUP Chipsubstrateground BAND_GAP 11 OUT Bandgap voltage(VBG = 1.6V);internalanalogvoltagereference Selectionbetween ASK and OOK modulation(0= ASK, 1 = OOK) forDirectMode 0 and 1.ASK/OOK 12 BID Itcan be configuredas an outputtoprovidethereceivedanalogsignaloutput. IRQ 13 OUT Interruptrequest INP ExternaldatamodulationinputforDirectMode 0 or1 MOD 14 OUT Subcarrierdigitaldataoutput(seeregister0x1A and 0x1B definitions) VSS_A 15 SUP Negativesupplyforinternalanalogcircuits;connectedtoGND VDD_I/O 16 INP SupplyforI/Ocommunications(1.8V toVIN)levelshifter.VIN shouldbe neverexceeded. (1) SUP = Supply,INP = Input,BID = Bidirectional,OUT = Output Copyright© 2011–2013,Texas InstrumentsIncorporated PhysicalCharacteristics 5 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

SLOS758C –DECEMBER 2011–REVISED JANUARY 2013 www.ti.com Table2-1.TerminalFunctions(continued) Terminal Type (1) Description Name No. I/O_0 17 BID I/Opinforparallelcommunication I/O_1 18 BID I/Opinforparallelcommunication I/O_2 19 BID I/Opinforparallelcommunication I/O_3 20 BID I/Opinforparallelcommunication I/OpinforparallelcommunicationI/O_4 21 BID SlaveselectsignalinSPI mode I/OpinforparallelcommunicationI/O_5 22 BID Data clockoutputinDirectMode 1 I/Opinforparallelcommunication I/O_6 23 BID MISO forserialcommunication(SPI) SerialbitdataoutputinDirectMode 1 orsubcarriersignalinDirectMode 0 I/Opinforparallelcommunication.I/O_7 24 BID MOSI forserialcommunication(SPI) Selectionofpower down mode. IfEN2 isconnectedtoVIN,thenVDD_X isactiveduringpowerEN2 25 INP down mode 2 (forexample,tosupplytheMCU). DATA_CLK 26 INP Data clockinputforMCU communication(paralleland serial) IfEN = 1 (EN2 = don'tcare)the system clockforthe MCU isconfiguredwithregister0x09 (off, SYS_CLK 27 OUT 3.39MHz, 6.78MHz, or13.56MHz). IfEN = 0 and EN2 = 1,thesystemclockissetto60 kHz EN 28 INP Chipenableinput(IfEN = 0,thenthechipisinsleeporpower-down mode) VSS_D 29 SUP Negativesupplyforinternaldigitalcircuits OSC_OUT 30 OUT Crystaloroscillatoroutput OSC_IN 31 INP Crystaloroscillatorinput Internallyregulatedsupply(2.7V to3.4V) fordigitalcircuitand externaldevices(forexample,anVDD_X 32 OUT MCU) PAD PAD SUP Chipsubstrateground

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3 ElectricalCharacteristics

3.1 AbsoluteMaximum Ratings (1)

overoperatingfree-airtemperaturerange(unlessotherwisenoted)(2) VIN Inputvoltagerange -0.3V to6 V IIN Maximum current 150 mA ESD Electrostaticdischargerating Human-body model (HBM) 2 kV Charged-devicemodel (CDM) 500 V Machine model (MM) 200 V TJ Maximum operatingvirtualjunctiontemperature(3) Any condition 140°C Continuousoperation,long-termreliability 125°C TSTG Storagetemperaturerange -55°C to150°C (1) Stressesbeyond thoselistedunderAbsoluteMaximum Ratingsmay cause permanentdamage tothedevice.These arestressratings onlyand functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunderOperatingConditionsarenot implied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) AllvoltagevaluesarewithrespecttosubstrategroundterminalVSS. (3) The maximum junctiontemperatureforcontinuousoperationislimitedby package constraints.Operationabove thistemperaturemay resultinreducedreliabilityand/orlifetimeofthedevice.

3.2 DissipationRatings

POWER RATING (2) PACKAGE θJC θJA (1) TA ≤ 25°C TA ≤ 85°C RHB (32) 31°C/W 36.4°C/W 2.7W 1.1W (1) Thisdatawas takenusingtheJEDEC standardhigh-KtestPCB. (2) Power ratingisdeterminedwitha junctiontemperatureof125°C. Thisisthepointwhere distortionstartstoincreasesubstantially. Thermalmanagement ofthefinalPCB shouldstrivetokeep thejunctiontemperatureatorbelow125°C forbestperformanceand long- termreliability.

3.3 Recommended OperatingConditions

overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN TYP MAX UNIT VIN Operatinginputvoltage 2.7 5 5.5 V TA Operatingambienttemperature -25 25 85 °C TJ Operatingvirtualjunctiontemperature -25 25 125 °C Copyright© 2011–2013,Texas InstrumentsIncorporated ElectricalCharacteristics 7 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

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3.4 ElectricalCharacteristics

TYP operatingconditionsareTA = 25°C, VIN = 5 V,full-powermode (unlessotherwisenoted) MIN and MAX operatingconditionsareoverrecommended rangesofsupplyvoltageand operatingfree-airtemperature (unlessotherwisenoted) PARAMETER CONDITIONS MIN TYP MAX UNIT Allbuildingblocksdisabled,includingsupply- IPD1 SupplycurrentinPower Down Mode 1 voltageregulators;measured after500-ms <0.5 5 µA settlingtime(EN = 0,EN2 = 0) The SYS_CLK generatorand VDD_X remainSupplycurrentinPower Down Mode 2IPD2 activetosupportexternalcircuitry,measured 120 200 µA(SleepMode) after100-ms settlingtime(EN = 0,EN2 = 1) Oscillatorrunning,supply-voltageregulatorsinISTBY Supplycurrentinstand-bymode 1.9 3.5 mAlow-consumptionmode (EN = 1,EN2 = x) Supplycurrentwithoutantennadriver Oscillator,regulators,RX, and AGC areactive,ION1 10.5 14 mAcurrent TX isoff Oscillator,regulators,RX, AGC, and TXION2 Supplycurrent– TX (halfpower) 70 78 mAactive,POUT = 100 mW Oscillator,regulators,RX, AGC, and TXION3 Supplycurrent– TX (fullpower) 130 170 mAactive,POUT = 200 mW VPOR Power-onresetvoltage InputvoltageatVIN 1.4 2 2.6 V VBG Bandgap voltage(pin11) Internalanalogreferencevoltage 1.5 1.6 1.7 V RegulatedoutputvoltageforanalogVDD_A VIN = 5 V 3.1 3.5 3.8 Vcircuitry(pin1) VDD_X RegulatedsupplyforexternalcircuitryOutputvoltagepin32,VIN = 5 V 3.1 3.4 3.8 V IVDD_Xmax Maximum outputcurrentofVDD_X Outputcurrentpin32,VIN = 5 V 20 mA Halfpower mode, VIN = 2.7V to5.5V 8 12 Ω R RFOUT Antennadriveroutputresistance(1) Fullpower mode, VIN = 2.7V to5.5V 4 6 Ω R RFIN RX_IN1 and RX_IN2 inputresistance 4 10 20 kΩ Maximum RF inputvoltageatRX_IN1,VRF_INmax VRF_INmax shouldnotexceed VIN 3.5 VppRX_IN2 Minimum RF inputvoltageatRX_IN1,VRF_INmin fSUBCARRIER = 424 kHz 1.4 2.5 mV ppRX_IN2 (inputsensitivity)(2) fSUBCARRIER = 848 kHz 2.1 3 mV pp fSYS_CLK SYS_CLK frequency Inpower mode 2,EN = 0,EN2 = 1 25 60 120 kHz fC Carrierfrequency Definedby externalcrystal 13.56 MHz Time untiloscillatorstablebitisset(registertCRYSTAL Crystalrun-intime 5 ms0x0F) (3) Depends on capacitiveloadon theI/Olines,fD_CLKmax Maximum DATA_CLK frequency(4) 2 8 10 MHzrecommendationis2 MHz (4) I/Olines,IRQ,SYS_CLK, DATA_CLK, EN, 0.2×VIL Inputvoltage,logiclow VEN2 VDD_I/O I/Olines,IRQ,SYS_CLK, DATA_CLK, EN, 0.8×VIH Inputvoltagethreshold,logichigh VEN2 VDD_I/O R OUT Outputresistance,I/O_0toI/O_7 500 800 Ω R SYS_CLK OutputresistanceR SYS_CLK 200 400 Ω (1) Antennadriveroutputresistance (2) Measured withsubcarriersignalatRX_IN1/2 and measured thedigitaloutputatMOD pinwithregister0x1A bit6 = 1 (3) Dependingon thecrystalparametersand components (4) Recommended DATA_CLK speed is2 MHz; higherdataclockdepends on thecapacitiveload.Maximum SPI clockspeed shouldnot exceed 10 MHz. Thisclockspeed isacceptableonlywhen externalcapacitiveloadislessthan30 pF.MISO driverhas a typicaloutput resistanceof400 Ω (12-nstimeconstantwhen 30-pFloadisused).

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3.5 SwitchingCharacteristics

overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER CONDITIONS MIN TYP MAX UNIT DATA_CLK time,highorlow(onehalftLO/HI Depends on capacitiveloadon theI/Olines(1) 50 62.5 250 nsofDATA_CLK at50% dutycycle) Slaveselectleadtime,slaveselecttSTE,LEAD 200 nslowtoclock Slaveselectlagtime,lastclocktotSTE,LAG 200 nsslaveselecthigh tSU,SI MOSI inputdatasetuptime 15 ns tHD,SI MOSI inputdataholdtime 15 ns tSU,SO MISO inputdatasetuptime 15 ns tHD,SO MISO inputdataholdtime 15 ns tVALID,SO MISO outputdatavalidtime DATA_CLK edge toMISO valid,C L = <30 pF 30 50 75 ns (1) Recommended DATA_CLK speed is2 MHz; higherdataclockdepends on thecapacitiveload.Maximum SPI clockspeed shouldnot exceed 10 MHz. Thisclockspeed isacceptableonlywhen externalcapacitiveloadislessthan30 pF.MISO driverhas a typicaloutput resistanceof400 Ω (12-nstimeconstantwhen 30-pFloadisused). Copyright© 2011–2013,Texas InstrumentsIncorporated ElectricalCharacteristics 9 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

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4 ApplicationSchematic and Layout Considerations

4.1 TRF7963A Reader System Using ParallelMicrocontrollerInterface

4.1.1 GeneralApplicationConsiderations

Figure4-1 shows the most flexibleTRF7963A application.Due to the low clockfrequencyon the DATA_CLK line,theparallelinterfaceisthemost robustway toconnecttheTRF7963A withtheMCU. This schematicshows matchingto a 50-Ω port,which allowsconnectionto a properlymatched 50-Ω antennacircuitorRF measurement equipment(forexample,a spectrumanalyzerorpower meter).

4.1.2 Schematic

Figure4-1shows a sample applicationschematicwitha parallelinterfacetotheMCU. Figure4-1.ApplicationSchematic,ParallelMCU Interface The MSP430F2370 (32kB flash,2kB RAM) isshown inFigure4-1.Minimum MCU requirementsdepend on applicationrequirementsand codingstyle.Ifonlyone ISO protocoland/ora limitedcommand setofa protocolmust be supported,MCU flashand RAM requirementscan be significantlyreduced.For example, currentreferencefirmwareforISO14443A/B (withhostinterface)isapproximately8kB, using1kB RAM . An MCU thatiscapableofrunninga GPIO at13.56MHz isrequiredforDirectMode 0 operationswith nonstandardtransponders.

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4.2 TRF7963A Reader System Using SPI With SS Mode

4.2.1 GeneralApplicationConsiderations

Figure4-2 shows the TRF7963A applicationschematicusingthe SerialPortInterface(SPI).ShortSPI lines,proper isolationto radiofrequencylines,and a proper ground area are essentialto avoid interference.The recommended clockfrequencyon theDATA_CLK lineis2 MHz. This schematicshows matchingto a 50-Ω port,which allowsconnectionto a properlymatched 50-Ω antennacircuitorRF measurement equipment(forexample,a spectrumanalyzerorpower meter).

4.2.2 Schematic

Figure4-2shows a sample applicationschematicwitha serialinterfacetotheMCU. Figure4-2.ApplicationSchematic,SPI With SS Mode MCU Interface The MSP430F2370 (32kB flash,2kB RAM) isshown inFigure4-2.Minimum MCU requirementsdepend on applicationrequirementsand codingstyle.Ifonlyone ISO protocoland/ora limitedcommand setofa protocolmust be supported,MCU flashand RAM requirementscan be significantlyreduced.For example, currentreferencefirmwareforISO14443A/B (withhostinterface)isapproximately8kB, using1kB RAM . An MCU thatiscapableofrunninga GPIO at13.56MHz isrequiredforDirectMode 0 operationswith nonstandardtransponders. Copyright© 2011–2013,Texas InstrumentsIncorporated ApplicationSchematicand LayoutConsiderations 11 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

RX_IN1 RX_IN2 Phase and Amplitude Detector Gain RSSI (AUX) Logic State Control Logic (Control Registers, Command Logic) 12-Byte FIFO MCU Interface VDD _I/O I/O_0 I/O_1 I/O_2 I/O_3 I/O_4 I/O_5 I/O_6 I/O_7 IRQ SYS_CLK DATA _CLK ISO Protocol Handling Decoder RSSI (External) Gain RSSI (Main) Filter, AGC Digitizer Bit FramingFraming Serial Conversion CRC, Parity Transmitter Analog Front EndTX_ OUT VDD_PA VSS_PA Digital Control State Machine Crystal Oscillator Timing System EN EN2 ASK/ OOK MOD OSC_IN OSC_ OUT Voltage Supply Regulator Systems (Supply Regulators, Reference Voltages) VSS_A VSS_RF VDD _RF VDD_X VSS_D VSS VIN VDD _A BAND _GAP Phase and Amplitude Detector Level Shifter TRF7963A SLOS758C –DECEMBER 2011–REVISED JANUARY 2013 www.ti.com

5 DetailedSystem Description

5.1 System Block Diagram

Figure5-1.System Block Diagram

5.2 Power Supplies

The TRF7963A positivesupplyinputVIN (pin2) sourcesthreeinternalregulatorswithoutputvoltages VDD_RF, VDD_A, and VDD_X. Allregulatorsrequireexternalbypass capacitorsforsupplynoisefiltering and must be connectedas indicatedin referenceschematics.These regulatorsprovidea high power supplyrejectratio(PSRR) as requiredforRFID readersystems.AllregulatorsaresuppliedviaVIN (pin2). The regulatorsare not independentand have common controlbitsinregister0x0B foroutputvoltage setting.The regulatorscan be configuredtooperateineitherautomaticormanual mode (register0x0B,bit 7).The automaticregulatorsettingmode ensuresan optimalcompromise between PSRR and thehighest possiblesupplyvoltageforRF output(toensuremaximum RF power output).The manual mode allows theusertomanuallyconfiguretheregulatorsettings.

5.3 Supply Arrangements

RegulatorSupply Input:VIN The positivesupplyatVIN (pin2) has an inputvoltagerange of2.7V to5.5V. VIN providesthesupply inputsources forthreeinternalregulatorswith the outputvoltagesVDD_RF, VDD_A, and VDD_X. Externalbypasscapacitorsforsupplynoisefilteringmust be used (perreferenceschematics). NOTE VIN must be thehighestvoltagesuppliedtotheTRF7963A.

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www.ti.com SLOS758C –DECEMBER 2011–REVISED JANUARY 2013 RF Power AmplifierRegulator:VDD_RF The VDD_RF (pin3) regulatorissupplyingtheRF power amplifier.The voltageregulatorcan be setfor either5V or 3V operation.Externalbypass capacitorsforsupplynoise filteringmust be used (per referenceschematics).When configuredfor5V manual-operation,theVDD_RF outputvoltagecan be set from4.3V to5 V in100-mV steps.In3-V manual operation,theoutputcan be programmed from2.7V to 3.4V in100-mV steps(seeTable5-2).The maximum outputcurrentcapabilityfor5-V operationis150 mA and for3-V operationis100 mA. Analog Supply Regulator:VDD_A RegulatorVDD_A (pin1)suppliestheanalogcircuitsofthedevice.The outputvoltagesettingdepends on theinputvoltageand can be setfor5-V and 3-V operation.When configuredfor5-V manual operation, theoutputvoltageisfixedat3.4V. Externalbypass capacitorsforsupplynoisefilteringmust be used (per referenceschematics).When configuredfor3-V manual operation,theVDD_A outputcan be setfrom2.7 V to3.4V in100-mV steps(seeTable5-2). NOTE The configurationof VDD_A and VDD_X regulatorsare not independentfrom each other. The VDD_A outputcurrentshouldnotexceed 20 mA. DigitalSupply Regulator:VDD_X The DigitalSupply RegulatorVDD_X (pin32) providesthe power forthe internaldigitalbuildingblocks and can alsobe used tosupplyexternalelectronicswithinthereadersystem.When configuredfor3-V operation,theoutputvoltagecan be setfrom2.7to3.4V in100-mV steps.Externalbypass capacitorsfor supplynoisefilteringmust be used (perreferenceschematics). NOTE The configurationoftheVDD_A and VDD_X regulatorsarenotindependentfromeach other. The VDD_X outputcurrentshouldnotexceed 20 mA. The RF power amplifierregulator(VDD_RF), analog supply regulator(VDD_A), and digitalsupply regulator(VDD_X) can be configuredtooperateineitherautomaticormanual mode describedinTable5- 1.The automaticregulatorsettingmode ensuresan optimalcompromise between PSRR and thehighest possiblesupplyvoltagetoensuremaximum RF power output. By default,the regulatorsare setinautomaticregulatorsettingmode. In thismode, the regulatorsare automaticallyseteverytimethesystem isactivatedby settingEN inputHigh or each timetheautomatic regulatorsettingbit,B7 inregister0x0B issettoa 1.The actionisstartedon the0 to1 transition.This means that,iftheuserwants tore-runtheautomaticsettingfroma stateinwhichtheautomaticsettingbit isalreadyhigh,theautomaticsettingbit(B7 inregister0x0B)shouldbe changed:1-0-1. By default,theregulatorsettingalgorithmsetstheregulatoroutputstoa "DeltaVoltage"of250 mV below VIN, but not higherthan 5 V forVDD_RF and 3.4 V forVDD_A and VDD_A. The "DeltaVoltage"in automaticregulatormode can be increasedup to400 mV (formore details,see bitsB0 toB2 inregister 0x0B). Power AmplifierSupply:VDD_PA The power amplifieroftheTRF7963A issuppliedthroughVDD_PA (pin4).The positivesupplypinforthe RF power amplifierisexternallyconnectedtotheregulatoroutputVDD_RF (pin3). Copyright© 2011–2013,Texas InstrumentsIncorporated DetailedSystem Description 13 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

SLOS758C –DECEMBER 2011–REVISED JANUARY 2013 www.ti.com I/OLevelShifterSupply:VDD_I/O The TRF7963A has a separatesupplyinputVDD_I/O (pin16) forthe buildin I/O levelshifter.The supportedinputvoltagerangesfrom1.8V toVIN,however notexceeding5.5V. Pin16 isused tosupply the I/O interfacepins(I/O_0to I/O_7),IRQ, SYS_CLK, and DATA_CLK pinsof the reader.In typical applications,VDD_I/O isdirectlyconnectedtoVDD_X whileVDD_X alsosuppliestheMCU. Thisensures thattheI/OsignallevelsoftheMCU match withthelogiclevelsoftheTRF7963A. NegativeSupply Connections:VSS, VSS_RX, VSS_A, VSS_PA The negativesupplyconnectionsVSS_X ofeach functionalblockareallexternallyconnectedtoGND. The substrateconnectionis VSS (pin10),the analog negativesupplyis VSS_A (pin15),the logic negativesupplyisVSS_D (pin29),the RF outputstage negativesupplyisVSS_PA (pin6),and the negativesupplyfortheRF receiverVSS_RX (pin7).

5.4 Supply RegulatorSettings

The inputsupplyvoltagemode ofthereadermust be selected.Thisisdone intheChip StatusControl register(0x00).Bit0 in register0x00 selectsbetween 5-V or 3-V inputsupplyvoltage.The default configurationis5 V, which reflectsan operatingsupplyvoltagerange of 4.3 V to 5.5 V. Ifthe supply voltageisbelow4.3V,the3-V configurationshouldbe used. The variousregulatorscan be configuredtooperateinautomaticormanual mode. Thisisdone inthe Regulatorand I/OControlregister(0x0B)as shown inTable5-1. Table5-1.Supply RegulatorSetting:5-V System Option BitsSettinginRegulatorControlRegister(1) Register CommentsAddress B7 B6 B5 B4 B3 B2 B1 B0 Automatic Mode (default) 0B 1 x x x x x 1 1 Automaticregulatorsetting250-mV difference 0B 1 x x x x x 1 0 Automaticregulatorsetting350-mV difference 0B 1 x x x x x 0 0 Automaticregulatorsetting400-mV difference Manual Mode 0B 0 x x x x 1 1 1 VDD_RF = 5 V,VDD_A = 3.4V,VDD_X = 3.4V 0B 0 x x x x 1 1 0 VDD_RF = 4.9V,VDD_A = 3.4V,VDD_X = 3.4V 0B 0 x x x x 1 0 1 VDD_RF = 4.8V,VDD_A = 3.4V,VDD_X = 3.4V 0B 0 x x x x 1 0 0 VDD_RF = 4.7V,VDD_A = 3.4V,VDD_X = 3.4V 0B 0 x x x x 0 1 1 VDD_RF = 4.6V,VDD_A = 3.4V,VDD_X = 3.4V 0B 0 x x x x 0 1 0 VDD_RF = 4.5V,VDD_A = 3.4V,VDD_X = 3.4V 0B 0 x x x x 0 0 1 VDD_RF = 4.4V,VDD_A = 3.4V,VDD_X = 3.4V 0B 0 x x x x 0 0 0 VDD_RF = 4.3V,VDD_A = 3.4V,VDD_X = 3.4V (1) x = don'tcare

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www.ti.com SLOS758C –DECEMBER 2011–REVISED JANUARY 2013 Table5-2.Supply RegulatorSetting:3-V System Option BitsSettinginRegulatorControlRegister(1) Register CommentsAddress B7 B6 B5 B4 B3 B2 B1 B0 Automatic Mode (default) 0B 1 x x x x x 1 1 Automaticregulatorsetting250-mV difference 0B 1 x x x x x 1 0 Automaticregulatorsetting350-mV difference 0B 1 x x x x x 0 0 Automaticregulatorsetting400-mV difference Manual Mode 0B 0 x x x x 1 1 1 VDD_RF = 3.4V,VDD_A = 3.4V,VDD_X = 3.4V 0B 0 x x x x 1 1 0 VDD_RF = 3.3V,VDD_A = 3.3V,VDD_X = 3.3V 0B 0 x x x x 1 0 1 VDD_RF = 3.2V,VDD_A = 3.2V,VDD_X = 3.2V 0B 0 x x x x 1 0 0 VDD_RF = 3.1V,VDD_A = 3.1V,VDD_X = 3.1V 0B 0 x x x x 0 1 1 VDD_RF = 3.0V,VDD_A = 3.0V,VDD_X = 3.0V 0B 0 x x x x 0 1 0 VDD_RF = 2.9V,VDD_A = 2.9V,VDD_X = 2.9V 0B 0 x x x x 0 0 1 VDD_RF = 2.8V,VDD_A = 2.8V,VDD_X = 2.8V 0B 0 x x x x 0 0 0 VDD_RF = 2.7V,VDD_A = 2.7V,VDD_X = 2.7V (1) x = don'tcare The regulatorconfigurationfunctionadjuststheregulatoroutputsby defaultto250 mV below VIN level, but not higherthan 5 V forVDD_RF, 3.4 V forVDD_A and VDD_X. Thisensuresthe highestpossible supplyvoltageforthe RF outputstage whilemaintainingan adequate PSRR (power supplyrejection ratio). To furtherimprovethePSRR, itispossibletoincreasethetargetvoltagedifferenceacrossVDD_X and VDD_A from itsdefaultto 350 mV or even 400 mV (fordetails,see Regulatorand I/OControlregister 0x0B definitionand Table5-2.)

5.5 Power Modes

The chiphas severalpower states,whicharecontrolledby two inputpins(EN and EN2) and severalbits intheChipStatusControlregister(0x00). Table5-3isa consolidatedtableshowingtheconfigurationforthedifferentpower modes when usinga 5- V or3-V system supply.The main readerenablesignalispinEN. When EN issethigh,allofthereader regulatorsare enabled,the13.56-MHz oscillatorisrunningand theSYS_CLK (outputclockforexternal microcontroller)isalsoavailable. The RegulatorControlregistersettingsshown are foroptimizedpower out.The automaticsetting (normally0x87)isoptimizedforbestPSRR and noisereduction. Table5-3.Power Modes (1) Chip Regulator Typical TimeStatus SYS_CLK TypicalControl Trans- SYS_CLK Power (FromMode EN2 EN Control Receiver (13.56 VDD_X CurrentRegister mitter (60kHz) Out PreviousRegister MHz) (mA)(0x0B) (dBm) State)(0x00) Mode 4 (FullPower) x 1 21 07 On On On x On 130 23 ~20-25µs

5 VDC

(FullPower) x 1 20 07 On On On x On 67 18 3.3VDC Mode 3 (HalfPower) x 1 31 07 On On On x On 70 20 ~20-25µs (HalfPower) x 1 30 07 On On On x On 53 15 3.3VDC (1) x = don'tcare Copyright© 2011–2013,Texas InstrumentsIncorporated DetailedSystem Description 15 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

SLOS758C –DECEMBER 2011–REVISED JANUARY 2013 www.ti.com Table5-3.Power Modes (1) (continued) Chip Regulator Typical TimeStatus SYS_CLK TypicalControl Trans- SYS_CLK Power (FromMode EN2 EN Control Receiver (13.56 VDD_X CurrentRegister mitter (60kHz) Out PreviousRegister MHz) (mA)(0x0B) (dBm) State)(0x00) Mode 2 x 1 03 07 Off On On x On 10.5 — ~20-25µs5 VDC Mode 2 x 1 02 00 Off On On x On 9 —3.3VDC Mode 1 x 1 01 07 Off Off On x On 5 — ~20-25µs5 VDC Mode 1 x 1 00 00 Off Off On x On 33.3VDC StandbyMode x 1 81 07 Off Off On x On 3 — 4.8ms5 VDC StandbyMode x 1 80 00 Off Off On x On 2 —3.3VDC SleepMode 1 0 x x Off Off Off On On 0.120 — 1.5ms Power Down 0 0 x x Off Off Off Off Off <0.001 — Start The inputpinEN2 has two functions:

• A directconnectionfromEN2 toVIN toensuretheavailabilityoftheregulatedsupplyVDD_X and an auxiliaryclocksignal(60 kHz, SYS_CLK) foran externalMCU. This mode (EN = 0, EN2 = 1) is intendedforsystemsinwhichtheMCU isalsobeingsuppliedby thereadersupplyregulator(VDD_X) and theMCU clockissuppliedby theSYS_CLK outputofthereader.ThisallowstheMCU supplyand clocktobe availableduringsleepmode.
• EN2 enablesthestart-upofthereadersystem fromcompletepower down (EN = 0,EN2 = 0).Inthis case,the EN inputisbeingcontrolledby the MCU (orothersystem device)thatiswithoutsupply voltageduringcompletepower down (thusunabletocontroltheEN input).A risingedge appliedtothe EN2 input(whichhas an approximately1-V thresholdlevel)startsthereadersupplysystemand 13.56- MHz oscillator(identicaltoconditionEN = 1). When userMCU iscontrollingEN and EN2, a delayof5 ms between EN and EN2 must be used.Incases where MCU is only controllingEN, EN2 is recommended to be connected to eitherVIN or GND, dependingon theapplicationMCU requirements/needsforVDD_X and SYS_CLK. NOTE UsingEN=1 and EN2=1 inparallelatstartup shouldnotbe done as itmay cause incorrect operation. Thisstart-upmode lastsuntilalloftheregulatorshave settledand the13.56-MHz oscillatorhas stabilized. IftheEN inputissethigh(EN = 1)by theMCU (orothersystemdevice),thereaderstaysactive.IftheEN inputisnotsethigh(EN = 0)within100 µs aftertheSYS_CLK outputisswitchedfromauxiliaryclock(60 kHz) tohigh-frequencyclock(derivedfrom thecrystaloscillator),thereadersystem returnstocomplete Power-Down Mode 1. Thisoptioncan be used to wake the readersystem from completePower Down (PD Mode 1)by usinga pushbuttonswitchorby sendinga singlepulse. AfterthereaderEN lineishigh,theotherpower modes areselectedby controlbitswithintheChip Status Controlregister(0x00).The power mode optionsand statesarelistedinTable5-3. When EN issethigh(oron risingedge ofEN2 and thenconfirmedby EN = 1)thesupplyregulatorsare activatedand the13.56-MHz oscillatorstarted.When thesuppliesaresettledand theoscillatorfrequency isstable,the SYS_CLK outputisswitchedfrom the auxiliaryfrequencyof 60 kHz to the 13.56-MHz frequencyderivedfromthecrystaloscillator.At thistime,thereaderisreadytocommunicate and perform the requiredtasks.The MCU can then program the Chip StatusControlregister0x00 and selectthe operationmode by programmingtheadditionalregisters.

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• Stand-byMode (bit7 = 1 of register0x00),the readeriscapableof recoveringto fulloperationin 100 µs.
• Mode 1 (activemode withRF outputdisabled,bit5 = 0 and bit1 = 0 ofregister0x00)isa low-power mode thatallowsthereadertorecovertofulloperationwithin25 µs.
• Mode 2 (activemode withonlythe RF receiveractive,bit1 = 1 of register0x00) can be used to measure the externalRF field(as describedin RSSI measurements paragraph)ifreader-to-reader anticollisionisimplemented.
• Mode 3 and Mode 4 (activemodes withtheentireRF sectionactive,bit5 = 1 ofregister0x00)arethe normalmodes used fornormaltransmitand receiveoperations.

5.6 Receiver-Analog Section

5.6.1 Main and AuxiliaryReceiver

The TRF7963A has two receiverinputs:RX_IN1 (pin8) and RX_IN2 (pin9).Each of the inputsis connectedto an externalcapacitivevoltagedividerto ensure thatthe modulatedsignalfrom the tag is availableon atleastone ofthetwo inputs.Thisarchitectureeliminatesany possiblecommunicationholes thatmay occurfromthetagtothereader. The two RX inputs(RX_IN1 and RX_IN2) are multiplexedintotwo receivers–themain receiverand the auxiliaryreceiver.Only the main receiverisused forreception;the auxiliaryreceiverisused forsignal qualitymonitoring.Receiverinputmultiplexingiscontrolledby bitB3 intheChip StatusControlregister (address0x00). Afterstartup,RX_IN1 ismultiplexedtothemain receiverwhichiscomposed ofan RF envelopedetection, firstgainand band-passfilteringstage,second gainand filteringstagewithAGC. Only themain receiver isconnectedtothedigitizingstagewhich outputisconnectedtothedigitalprocessingblock.The main receiveralsohas an RSSI measuring stage,which measures the strengthof the demodulated signal (subcarriersignal). The primaryfunctionoftheauxiliaryreceiveristomonitortheRX signalqualityby measuringtheRSSI of the demodulatedsubcarriersignal(internalRSSI).Afterstartup,RX_IN2 ismultiplexedto the auxiliary receiver.The auxiliaryreceiverhas an RF envelopedetectionstage,firstgainand filteringwithAGC stage and finallytheauxiliaryRSSI block. The defaultMUX settingisRX_IN1 connectedtothemain receiverand RX_IN2 connectedtotheauxiliary receiver.To determinethesignalquality,theresponsefromthetagisdetectedby the"main"(pinRX_IN1) and "auxiliary"(pinRX_IN2) RSSI. Both valuesmeasured and storedintheRSSI levelregister(address 0x0F).The MCU can readtheRSSI valuesfromtheTRF7963A RSSI registerand decideifswappingthe inputsignalsispreferableor not.SettingB3 in the Chip StatusControlregister(address0x00) to 1 connects RX_IN1 (pin8) to the auxiliaryreceiverand RX_IN2 (pin9) to the main receiver.This mechanism must be used toavoidreadingholes. The main and auxiliaryreceiverinputstagesareRF envelopedetectors.The RF amplitudeatRX_IN1 and RX_IN2 shouldbe approximately3 VPP fora VIN supplylevelgreaterthan3.3V. IftheVIN levelislower, theRF inputpeak-to-peakvoltagelevelshouldnotexceed theVIN level.

5.6.2 ReceiverGain and FilterStages

The firstgainand filteringstagehas a nominalgainof 15 dB withan adjustableband-passfilter.The band-passfilterhas programmable 3-dB cornerfrequenciesbetween 110 kHz to 450 kHz forthe high- pass filterand between 570 kHz to 1500 kHz forthe low-passfilter.Afterthe band-passfilter,thereis anothergain-and-filteringstagewitha nominalgainof8 dB and withfrequencycharacteristicsidenticalto thefirstband-passstage. The internalfiltersareconfiguredautomaticallydependingon theselectedISO communicationstandardin theISO Controlregister(address0x01).Ifrequired,additionalfinetuningcan be done by writingdirectly totheRX specialsettingregisters(address0x0A). Copyright© 2011–2013,Texas InstrumentsIncorporated DetailedSystem Description 17 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

SLOS758C –DECEMBER 2011–REVISED JANUARY 2013 www.ti.com The main receiveralsohas a second receivergainand digitizerstagewhichisincludedintheAGC loop. The AGC loopisactivatedby settingthebitB2 = 1 intheChip StatusControlregister(address0x00). When activated,the AGC continuouslymonitorsthe inputsignallevel.Ifthe signallevelissignificantly higherthanan internalthresholdlevel,gainreductionisactivated. By default,theAGC isfrozenafterthefirstfourpulsesofthesubcarriersignal.ThispreventstheAGC frominterferingwiththereceptionoftheremainingdatapacket.Incertainsituations,this"AGC freeze"is notoptimal,so itcan be removed by settingB0 = 1 intheRX SpecialSettingregister(address0x0A). Table5-4shows thevarioussettingsforthereceiveranalogsection.ItisimportanttonotethatsettingB4, B5, B6, and B7 to0 resultsina band-passcharacteristicof240 kHz to1.4MHz, whichisappropriatefor ISO14443B 106 kbps,ISO14443A/B data-ratesof212 kbps and 424 kbps,and FeliCa424 kbps. Table5-4.RX SpecialSettingRegister(0x0A) Bit Function Comments B7 Bandpass from110 kHz to570 kHz Appropriateforany 212-kHzsubcarriersystemslikeFeliCa B6 Bandpass from200 kHz to900 kHz AppropriateforManchester-coded106-kbps848-kHzsubcarriersystems(forB5 Bandpass from450 kHz to1.5MHz example,used inISO14443A). Appropriateforhighestbitrate(848kbps)used inhigh-bit-rateISO14443B. GainB4 Bandpass from100 kHz to1.5MHz isreducedby 7 dB. B3 00 = no gainreduction 01 = gainreductionfor5 dB SetstheRX digitalgainreduction(changingthewindow ofthedigitizing 10 = gainreductionfor10 dB comparator).B2 11 = gainreductionfor15 dB AGC activationlevelchange.From fivetimeshighertotheminimum RX digitizing0 = 5 timesminimum digitizinglevelB1 leveltothreetimestheminimum digitizinglevel.The minimum RX digitizinglevel1 = 3 timesminimum digitizinglevel can be adjustedby B2 and B3 (gainreduction). AGC actionisnotlimitedintimeortothestartofreceive.AGC actioncan be done 0 = AGC freezeafter16 subcarrieredges any timeduringreceiveprocess.The AGC can onlyincreaseand,hence,clipsonB0 1 = AGC alwayson duringreceive thepeak RX levelduringtheenableperiod.AGC levelisresetautomaticallyatthe beginningofeach receivestartframe.

5.7 Receiver-DigitalSection

The outputoftheTRF7963A analogreceiverblockisa digitizedsubcarriersignaland istheinputtothe digitalreceiverblock.Thisblockincludesa ProtocolBitDecoder sectionand theFramingLogicsection. The protocolbitdecodersconvertthesubcarriercoded signalintoa serialbitstreamand a dataclock. The decoder logicis designed formaximum errortolerance.This enables the decoder sectionto successfullydecode even partlycorruptedsubcarriersignalsthatotherwisewould be lostdue tonoiseor interference. Intheframinglogicsection,theserialbitstreamdataisformattedinbytes.Specialsignalssuch as the startof frame (SOF), end of frame (EOF), startof communication,and end of communicationare automaticallyremoved.The paritybitsand CRC bytesarealsocheckedand removed.This"clean"datais then sent to the 12-byteFIFO registerwhere itcan be read by the externalmicrocontrollersystem. Providingthedatathisway, inconjunctionwiththetimingregistersettingsoftheTRF7963A, means the firmwaredeveloperhas toknow aboutmuch lessofthefinerdetailsoftheISO protocolstocreatea very robustapplication,especiallyin low-costplatformswhere code space is at a premium and high performanceisstillrequired. The startofthereceiveoperation(successfullyreceivedSOF) setstheIRQ flagsintheIRQ and Status register(0x0C).The end ofthereceiveoperationissignaledtotheexternalsystem MCU by settingpin13 (IRQ) high.Ifthe receivedata packetislongerthan 8 bytes,an interruptissent to the MCU as the receiveddata occupies75% of the FIFO capacity.The data shouldbe immediatelyremoved from the FIFO.

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www.ti.com SLOS758C –DECEMBER 2011–REVISED JANUARY 2013 Any errorinthedataformat,parity,orCRC isdetectedand notifiedtotheexternalsystem by an interrupt requestpulse.The sourceconditionoftheinterruptrequestpulseisavailableintheIRQ Statusregister (0x0C).The main registercontrollingthedigitalpartofthereceiveristheISO Controlregister(0x01).By writingtothisregister,theuserselectstheprotocoltobe used.With each new writeinthisregister,the defaultpresetsare reloadedin allrelatedregisters,so no furtheradjustmentsin otherregistersare needed forproperoperation. NOTE Ifregistersettingchanges are needed forfinetuningthe system,theymust be done after settingtheISO Controlregister(0x01). The framingsectionalsosupportsthebit-collisiondetectionas specifiedinISO14443A (0x01).When a bit collisionisdetected,an interruptrequestissentand a flagissetintheIRQ and Statusregister(0x0C). The positionofthebitcollisioniswrittenintwo registers:CollisionPositionregister(0x0E)and partlyin CollisionPositionand InterruptMask register(0x0D)(bitsB6 and B7). The collisionpositionispresentedas sequentialbitnumber,where thecountstartsimmediatelyafterthe startbit.This means a collisionin the firstbitof a UID would givethe value00 0001 0000 in these registerswhen theircontentsare combined afterbeingread.(thecountstartswith0 and thefirst16 bits arethecommand code and theNumber ofValidBits(NVB) byte) The receivesectionalsoincludestwo timers.The RX waittimetimeriscontrolledby thevalueintheRX Wait Time register(0x08).Thistimerdefinesthetimeintervalaftertheend ofthetransmitoperationin which the receivedecodersare not active(heldinresetstate).Thispreventsfalsedetectionsresulting fromtransientsfollowingthetransmitoperation.The valueoftheRX WaitTime register(0x08)definesthe time in incrementsof 9.44 µs. This registeris presetat every writeto ISO Controlregister(0x01) accordingtotheminimum tagresponsetimedefinedby each standard. The RX no responsetimeriscontrolledby the RX No Response Wait Time register(0x07).Thistimer measures thetimefromthestartofslotintheanticollisionsequence untilthestartoftagresponse.Ifthere isno tag responseinthe definedtime,an interruptrequestissentand a flagissetinthe IRQ Status register(0x0C).Thisenablestheexternalcontrollertobe relievedofthetaskofdetectingempty slots.The waittimeisstoredintheregisterinincrementsof37.76µs.Thisregisterisalsoautomaticallypresetfor everynew protocolselection.

5.7.1 Received SignalStrengthIndicator(RSSI)

The TRF7963A incorporatesintotalthreeindependentRSSI buildingblocks:InternalMain RSSI, Internal AuxiliaryRSSI, and ExternalRSSI. The internalRSSI blocksare measuring the amplitudeof the subcarriersignal,and the externalRSSI blockmeasures the amplitudeof the RF carriersignalat the receiverinput.

5.7.1.1 InternalRSSI – Main and AuxiliaryReceivers

Each receiverpath has itsown RSSI blockto measure the envelopeof the demodulated RF signal (subcarrier).InternalMain RSSI and InternalAuxiliaryRSSI areidenticalexceptthattheyareconnectedto differentRF inputpins.The InternalRSSI isintendedfordiagnosticpurposestosetthecorrectRX path conditions. The InternalRSSI valuescan be used toadjusttheRX gainsettingsand/ordecidewhichRX path(main or auxiliary)providesthe greateramplitudeand, hence, to decide ifthe MUX may need to be reprogrammed toswap theRX inputsignal.The measuringsystem latchesthepeak value,so theRSSI levelcan be read afterthe end of each receivepacket.The RSSI registervaluesare resetwithevery transmission(TX) by the reader.This guaranteesan updated RSSI measurement foreach new tag response. Copyright© 2011–2013,Texas InstrumentsIncorporated DetailedSystem Description 19 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

Input RF Carrier Level (V )PP RSSI Levels and Oscillator Status Register Value (0x0F) TRF7963A SLOS758C –DECEMBER 2011–REVISED JANUARY 2013 www.ti.com The InternalRSSI has 7 steps(3 bit)witha typicalincrementof about 4 dB. The operatingrange is between 600 mVp and 4.2Vpp witha typicalstepsizeofabout600 mV. Both RSSI values"InternalMain" and "InternalAux" RSSI arestoredintheRSSI Levelsand OscillatorStatusregister(0x0F). The nominalrelationshipbetween theinputRF peak leveland theRSSI valueisshown inFigure5-2. Figure5-2.DigitalInternalRSSI (Mainand Auxiliary)Value vs RF InputLevel ThisRSSI measurement isdone duringthecommunicationtotheTag;thismeans theTX must be on.Bit 1 intheChip StatusControlregister(0x00)definesifinternalRSSI ortheexternalRSSI valueisstoredin theRSSI Levelsand OscillatorStatusregister0x0F.Directcommand 0x18 isused totriggeran internal RSSI measurement.

5.7.1.2 ExternalRSSI

The externalRSSI ismainlyused fortestand diagnosticinordertosense theamplitudeofany 13.56- MHz signalat the receiversRX_IN1 input.The externalRSSI measurement istypicallydone inactive mode when the receiverison but transmitteroutputisoff.The levelof the RF signalreceivedat the antennaismeasured and storedintheRSSI Levelsand OscillatorStatusRegister0x0F. The relationshipbetween thevoltageattheRX_IN1 inputand the3-bitcode isshown inFigure5-3.

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0 25 50 75 100 125 150 175 200 225 250 275 300 325 RF Input Voltage Level at Pin RF_IN1 (mV )PP RSSI Levels and Oscillator Status Register Value (0x0F) TRF7963A www.ti.com SLOS758C –DECEMBER 2011–REVISED JANUARY 2013 Figure5-3.DigitalExternalRSSI Value vs RF InputLevel The relationbetween the3-bitcode and theexternalRF fieldstrength(A/m)sensed by theantennamust be determinedby calculationor by experimentsforeach antenna design.The antenna Q-factorand connectiontotheRF inputinfluencetheresult.Directcommand 0x19 isused totriggeran internalRSSI measurement. To checktheinternalorexternalRSSI valueindependentofany otheroperation,theusermust: 1. Settransmittertodesiredstate(onoroff)usingBit5 ofChipStatusControlregister(0x00) 2. Setthereceiverusingdirectcommand 0x17. 3. Check internalorexternalRSSI usingdirectcommands 0x18 or0x19,respectively. Thisactionlatches/placesRSSI valueinRSSI register 4. Read RSSI registerusingdirectcommand 0x0F,valuesrangefrom0x40 to0x7F. 5. Repeat steps1-4as desired,as registerisresetafterread.

5.8 OscillatorSection

The 13.56-MHz oscillatoriscontrolledviathe Chip StatusControlregister(0x00)and the EN and EN2 signals.The oscillatorgeneratestheRF frequencyfortheRF outputstageand theclocksourceforthe digitalsection.The bufferedclocksignalisavailableatpin27 (SYS_CLK) forexternalcircuits.B4 and B5 insidetheModulationand SYS_CLK register(0x09)can be used todividetheexternalSYS_CLK signalat pin27 by 1,2,or4. Typicalstart-uptimefromcompletepower down isintherangeof3.5ms. DuringPower Down Mode 2 (EN = 0,EN2 = 1)thefrequencyofSYS_CLK isswitchedto60 kHz (typical). The 13.56-MHz crystalmust be connectedbetween pin31 and pin32. The externalshuntcapacitors valuesforC 1 and C 2 must be calculatedbased on the specifiedloadcapacitanceof the crystalbeing used.The externalshuntcapacitorsare calculatedas two identicalcapacitorsinseriesplusthe stray capacitanceoftheTRF7963A and parasiticPCB capacitanceinparalleltothecrystal. The parasiticcapacitance(CS , strayand parasiticPCB capacitance)can be estimatedat 4 to 5 pF (typical). Copyright© 2011–2013,Texas InstrumentsIncorporated DetailedSystem Description 21 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

SLOS758C –DECEMBER 2011–REVISED JANUARY 2013 www.ti.com As an example,usinga crystalwitha requiredloadcapacitance(CL)of18 pF,thecalculationisas follows (seeFigure5-4): C 1= C 2 = 2 × (CL – C S)= 2 × (18pF – 4.5pF)= 27 pF A 27-pFcapacitormust be placedon pins30 and 31 toensurepropercrystaloscillatoroperation. Figure5-4.CrystalBlock Diagram Table5-5shows theminimum characteristicsrequiredforany crystalused withTRF7963A. Table5-5.TRF7963A Minimum CrystalRequirements Parameter Specification Frequency 13.56MHz Mode ofoperation Fundamental Type ofresonance Parallel Frequencytolerance ± 20 ppm Aging <5 ppm/year Operationtemperaturerange -40°C to85°C Equivalentseriesresistance 50 Ω As an alternative,an externalclockoscillatorsourcecan be connectedtopin31 toprovidethesystem clock,and pin32 can be leftopen.

5.9 Transmitter-Analog Section

The 13.56-MHz oscillatorgeneratesthe RF signalforthe PA stage.The power amplifierconsistsof a driverwithselectableoutputresistanceof4 Ω or 8 Ω (typical).The transmitpower levelsare selectable between 100 mW (halfpower) or 200 mW (fullpower) when configuredfor5-V automaticoperation. Selectionof the transmitpower levelissetby bitB4 inthe Chip StatusControlregister(0x00).When configuredfor3-V automaticoperation,thetransmitpower levelistypicallyintherange of33 mW (half power)or70 mW (fullpower). The ASK modulationdepthiscontrolledby bitsB0, B1, and B2 intheModulatorand SYS_CLK Control register(0x09).The ASK modulationdepthrangecan be adjustedbetween 7% to30% or100% (OOK). Externalcontrolofthetransmitmodulationdepthispossibleby settingtheISO Controlregister(0x01)to DirectMode. WhileoperatingtheTRF7963A inDirectMode, thetransmitmodulationismade possibleby selectingthe modulationtypeASK or OOK at pin12. Externalcontrolof the modulationtypeismade possibleonlyifenabledby settingB6 intheModulatorand SYS_CLK Controlregister(0x09)to1. Innormaloperationmode, thelengthofthemodulationpulseisdefinedby theprotocolselectedinthe ISO Controlregister(0x01).Incase ofa high-Qantenna,themodulationpulseistypicallyprolonged,and the tag detectsa longerpulsethan intended.For such cases,the modulationpulselengthmust be correctedby usingtheTX PulseLengthregister(0x06). Iftheregistercontainsallzeros,thenthepulselengthisgovernedby theprotocolselection.Iftheregister containsa valueotherthan 0x00, the pulselengthisequal to the valueof the registermultipliedby

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5.10 Transmitter-DigitalSection

The digitalpartof the transmitterisa mirrorof the receiver.The settingscontrolledthe ISO Control register(0x01)are appliedtothetransmitterjustlikethereceiver.IntheTRF7963A defaultmode (ISO Mode), the TRF7963A automaticallyadds allthe specialsignalslikestartof communication,end of communication,SOF, EOF, paritybitsand CRC bytes. The dataisthencoded tomodulationpulselevelsand senttotheRF outputstagemodulationcontrolunit. Justlikewiththereceiver,thismeans thattheexternalsystem MCU onlyhas toloadtheFIFO withdata and allthemicro-codingisdone automatically,againsavingthefirmwaredevelopercode space and time. Additionally,allthe registersused fortransmitparametercontrolare automaticallypresetto optimum valueswhen a new selectionisenteredintotheISO Controlregister(0x01). NOTE The FIFO must be resetbeforestartingany transmissionwithDirectCommand 0x0F. Therearetwo ways tostartthetransmitoperation:

• Itcan be startedby loadingthenumber ofbytestobe sent(address0x1D and 0x1E) and datatobe loadedinthe FIFO (address0x1F) followedby a transmitcommand (describedindirectcommands section).Inthiscase,thetransmissionthenstartsexactlyon thetransmitcommand.
• Itis also possibleto send the transmitcommand and informationon the number of bytes to be transmittedfirstand thenstarttosend thedatatoFIFO.Inthiscase,thetransmissionstartswhen first databyteiswrittenintotheFIFO. NOTE Ifthe data lengthislongerthan the FIFO, the externalsystem MCU iswarned when the majorityofdatafromtheFIFO was alreadytransmittedby sendingand interruptrequestwith flaginIRQ registertoindicatea FIFO low/highstatus.The externalsystem shouldrespond by loadingnextdatapacketintotheFIFO. At theend ofa transmitoperation,theexternalsystem MCU isnotifiedby interruptrequest(IRQ)witha flaginIRQ register(0x0C)indicatingTX iscomplete(examplevalue= 0x80). The TX Lengthregistersalsosupportincompletebytetransmission.The hightwo nibblesinregister0x1D and thenibblecomposed ofbitsB4 throughB7 inregister0x1E storethenumber ofcompletebytestobe transmitted.BitB0 inregister0x1E isa flagindicatingthattherearealsoadditionalbitstobe transmitted whichdo notforma completebyte.The number ofbitsisstoredinbitsB1 throughB3 ofthesame register (0x1E). Some protocolshave optionsso thereare two sub-levelconfigurationregisterstoselecttheTX protocol options.
• ISO14443B TX Optionsregister(0x02).ItcontrolstheSOF and EOF selectionand EGT selectionfor theISO14443B protocol.
• ISO14443A High-Bit-Rateand ParityOptionsregister(0x03).Thisregisterenablestheuse ofdifferent bitratesforRX and TX operationsinISO14443 highbitrateprotocol.Besidesthat,italsoselectsthe paritymethod incase ofISO14443A highbitrate.

5.11 Transmitter– ExternalPower Amplifier/Subcarrierdetector

The TRF7963A can be used inconjunctionwithan externalTX power amplifierand/orexternalsubcarrier detectorforthereceiverpath.Ifthisisthecase,certainregistersmust be programmed as shown here:

• BitB6 oftheRegulatorand I/OControlregister(0x0B)must be setto1. This settinghas two functions:First,to providea modulated signalforthe transmitter,ifneeded. Second,toconfiguretheTRF7963A receiverinputsforan externaldemodulatedsubcarrierinput.
• BitB3 oftheModulationand SYS_CLK Controlregister(0x09)to1 (seeSection6.1.2.6). Copyright© 2011–2013,Texas InstrumentsIncorporated DetailedSystem Description 23 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

SLOS758C –DECEMBER 2011–REVISED JANUARY 2013 www.ti.com ThisfunctionconfigurestheASK/OOK pinforeithera digitaloranalogoutput(B3 = 0 enablesa digital output,and B3 = 1 enablesan analogoutput).The designof an externalpower amplifierrequires detailedRF knowledge.There are alsoreadilydesignedand certifiedhigh-powerHF readermodules on themarket.

5.12 TRF7963A Communication Interface

5.12.1 GeneralIntroduction

The communicationinterfaceto the readercan be configuredin two ways: witha eightlineparallel interface(D0:D7)plusDATA_CLK, or witha threeor fourwireSerialPeripheralInterface(SPI).The SPI interfaceuses traditionalMasterOut/SlaveIn(MOSI),MasterIn,SlaveOut (MISO),IRQ, and DATA_CLK lines.The SPI can be operatedwithorwithoutusingtheSlaveSelectline. These communicationmodes are mutuallyexclusive;meaning,onlyone mode can be used ata timein theapplication. When theSPI interfaceisselected,theunused I/O_2,I/O_1,and I/O_0pinsmust be hard-wiredaccording toTable5-6.At power up,theTRF7963A IC samples thestatusofthesethreepins.Iftheyare notthe same (allHighorallLow) itentersone ofthepossibleSPI modes. The TRF7963A always behaves as the slave,whilethe microcontroller(MCU) behaves as the master device.The MCU initiatesallcommunicationswiththe TRF7963A. The TRF7963A makes use of the InterruptRequest(IRQ)pininbothparalleland SPI modes toprompttheMCU forservicingattention. Table5-6.Pin Assignment inParalleland SerialInterfaceConnection or DirectMode Pin Parallel ParallelDirect SPI With SS SPI WithoutSS DATA_ CLK DATA_CLK DATA_CLK DATA_CLK frommaster DATA_CLK frommaster I/O_7 A/D[7] MOSI (1)= datain(readerin) MOSI (1)= datain(readerin) Directmode, dataoutI/O_6 A/D[6] MISO (2)= dataout(MCU out) MISO (2)= dataout(MCU out)(subcarrierorbitstream) I/O_5(3) A/D[5] Directmode, strobe(bitclockout) See (3) See (3) I/O_4 A/D[4] SS (slaveselect)(4) – I/O_3 A/D[3] – – – I/O_2 A/D[2] – AtVDD AtVDD I/O_1 A/D[1] – AtVDD AtVSS I/O_0 A/D[0] – AtVSS AtVSS IRQ IRQ interruptIRQ interrupt IRQ interrupt IRQ interrupt (1) MOSI = MasterOut,SlaveIn (2) MISO = MasterIn,SlaveOut (3) The I/O_5pinisused onlyforinformationwhen dataisputoutofthechip(forexample,reading1 bytefromthechip).Itisnecessary firsttowriteintheaddressoftheregister(8clocks)and thentogenerateanother8 clocksforreadingoutthedata.The I/O_5pingoes highduringthesecond 8 clocks.ButfornormalSPI operationsI/O_5pinisnotused. (4) The slaveselectpinisactivelow. Communication is initializedby a startcondition,which is expected to be followedby an Address/Command word (Adr/Cmd).The Adr/Cmd word is8 bitslong,and itsformatisshown inTable5-

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www.ti.com SLOS758C –DECEMBER 2011–REVISED JANUARY 2013 Table5-7.Address/Command Word BitDistribution Bit Description BitFunction Address Command 0 = addressB7 Command controlbit 0 11 = command 1 = readB6 Read/Write R/W 00 = write B5 Continuousaddressmode 1 = continuousmode R/W 0 B4 Address/command bit4 Adr 4 Cmd 4 B3 Address/command bit3 Adr 3 Cmd 3 B2 Address/command bit2 Adr 2 Cmd 2 B1 Address/command bit1 Adr 1 Cmd 1 B0 Address/command bit0 Adr 0 Cmd 0 The MSB (bit7) determinesifthe word isto be used as a command or as an address.The lasttwo columns ofTable5-7show thefunctionoftheseparatebitsifeitheraddressorcommand iswritten.Data isexpectedonce theaddressword issent.Incontinuousaddressmode (continuousmode = 1),thefirst datathatfollowstheaddressiswritten(orread)to(from)thegivenaddress.For each additionaldata,the addressisincrementedby one.Continuousmode can be used towritetoa blockofcontrolregistersina singlestream withoutchanging the address;forexample, setup of the predefinedstandardcontrol registersfrom the MCU non-volatilememory to the reader.In non-continuousaddress mode (simple addressedmode),onlyone dataword isexpectedaftertheaddress. AddressMode isused towriteorreadtheconfigurationregistersortheFIFO.When writingmore than12 bytestotheFIFO,theContinuousAddressMode shouldbe setto1. The Command Mode is used to entera command resultingin readeraction(forexample, initialize transmission,enablereader,and turnreaderon/off). Examples ofexpectedcommunicationsbetween an MCU and theTRF7963A areshown. Table5-8.Continuous Address Mode Start Adr x Data(x) Data(x+1) Data(x+2) Data(x+3) Data(x+4) ... Data(x+n) StopCont Figure5-5.Continuous Address RegisterWriteExample StartingWith Register0x00 (UsingSPI With SS Mode) Copyright© 2011–2013,Texas InstrumentsIncorporated DetailedSystem Description 25 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

SLOS758C –DECEMBER 2011–REVISED JANUARY 2013 www.ti.com Figure5-6.Continuous Address RegisterRead Example StartingWith Register0x00 (UsingSPI With SS Mode) Table5-9.Non-Continuous Address Mode (SingleAddress Mode) Start Adr x Data(x) Adr y Data(y) ... Adr z Data(z) StopSgl Figure5-7.SingleAddress RegisterWriteExample ofRegister0x00 (UsingSPI With SS Mode)

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www.ti.com SLOS758C –DECEMBER 2011–REVISED JANUARY 2013 Figure5-8.SingleAddress RegisterRead Example ofRegister0x00 (UsingSPI With SS Mode) Table5-10.DirectCommand Mode Start Cmd x (Optionaldataorcommand) Stop Figure5-9.DirectCommand Example ofSending 0x0F (Reset)(UsingSPI With SS Mode) The otherDirectCommand Codes fromMCU toTRF7963A aredescribedinSection5.13.

5.12.2 FIFO Operation

The FIFO isa 12-byteregisterataddress0x1F withbytestoragelocations0 to11.FIFO dataisloadedin a cyclicalmanner and can be clearedby a resetcommand (0x0F,see graphicabove showingthisDirect Command). Copyright© 2011–2013,Texas InstrumentsIncorporated DetailedSystem Description 27 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

SLOS758C –DECEMBER 2011–REVISED JANUARY 2013 www.ti.com AssociatedwiththeFIFO are two countersand threeFIFO statusflags.The firstcounterisa 4-bitFIFO bytecounter(bitsB0 toB3 inregister0x1C) thatkeeps trackofthenumber ofbytesloadedintotheFIFO. Ifthenumber ofbytesintheFIFO isn,theregistervalueisn – 1 (number ofbytesinFIFO register).If8 bytesareintheFIFO,theFIFO counter(bitsB0 toB3 inregister0x1C) has thevalue7. A second counter(12 bitswide)indicatesthe number of bytesbeing transmitted(registers0x1D and 0x1E) ina dataframe.An extensiontothetransmission-bytecounterisa 4-bitbroken-bytecounteralso providedinregister0x1E (bitsB0 to B3).Togetherthesecountersmake up the TX lengthvaluethat determineswhen thereadergeneratestheEOF byte. FIFO statusflagsareas follows: 1. FIFO overflow(bitB4 ofregister0x1C):IndicatesthattheFIFO was loadedtoosoon 2. FIFO leveltoo low (bitB5 ofregister0x1C):Indicatesthatonlythreebytesarelefttobe transmitted (Can be used duringtransmission.) 3. FIFO levelhigh (bitB6 ofregister0x1C):IndicatesthatninebytesarealreadyloadedintotheFIFO (Can be used duringreceptiontogeneratea FIFO receptionIRQ.ThisistonotifytheMCU toservice thereaderintimetoensurea continuousdatastream.) Duringtransmission,the FIFO ischecked foran almost-emptycondition,and duringreceptionforan almost-fullcondition.The maximum number of bytes thatcan be loaded intothe FIFO in a single sequence is12 bytes. NOTE The number ofbytesina frame,transmittedorreceived,can be greaterthan12 bytes. Duringtransmission,the MCU loadsthe TRF7963A FIFO (or,duringreception,the MCU removes data fromtheFIFO),and theFIFO countercountsthenumber ofbytesbeingloadedintotheFIFO.Meanwhile, thebytecounterkeeps trackofthenumber ofbytesbeingtransmitted.An interruptrequestisgeneratedif the number of bytesinthe FIFO islessthan 3 or greaterthan 9, so thatMCU can send new data or remove thedataas necessary.The MCU alsochecks thenumber ofdatabytestobe sent,so as tonot surpassthevaluedefinedinTX lengthbytes.The MCU alsosignalsthetransmitlogicwhen thelastbyte ofdataissentorwas removed fromtheFIFO duringreception.Transmissionstartsautomaticallyafterthe firstbyteiswrittenintoFIFO. Figure5-10.Checking theFIFO StatusRegister(UsingSPI With SS Mode)

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www.ti.com SLOS758C –DECEMBER 2011–REVISED JANUARY 2013

5.12.3 ParallelInterfaceMode

Inparallelmode, thestartconditionisgeneratedon therisingedge oftheI/O_7pinwhiletheCLK ishigh. Thisisused toresettheinterfacelogic.Figure5-11shows thesequence ofthedata,withan 8-bitaddress word first,followedby data. Communicationisended by:

• The StopSmpl condition,where a fallingedge on theI/O_7pinisexpectedwhileCLK ishigh
• The StopContcondition,where theI/O_7pinmust have a successiverisingand fallingedge whileCLK islowinordertoresettheparallelinterfaceand be readyforthenew communicationsequence
• The StopSmpl conditionisalsoused toterminatetheDirectMode. Figure5-11.ParallelInterfaceCommunication With Simple Stop Condition(StopSmpl) Figure5-12.ParallelInterfaceCommunication With Continuous Stop Condition(StopCont) Figure5-13.ParallelInterfaceCommunication With Continuous Stop Condition Copyright© 2011–2013,Texas InstrumentsIncorporated DetailedSystem Description 29 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

SLOS758C –DECEMBER 2011–REVISED JANUARY 2013 www.ti.com 5.12.3.1ReceptionofAirInterfaceData At the startof a receiveoperation(when SOF issuccessfullydetected),B6 isset in the IRQ Status register.An interruptrequestissenttotheMCU attheend ofthereceiveoperationifthereceivedata stringwas shorterthan or equal to 8 bytes.The MCU receivesthe interruptrequest,then checks to determinethereasonfortheinterruptby readingtheIRQ Statusregister(address0x0C),afterwhichthe MCU readsthedatafromtheFIFO. Ifthereceivedpacketislongerthan8 bytes,theinterruptissentbeforetheend ofthereceiveoperation when theninthbyteisloadedintotheFIFO (75% full).The MCU shouldagainreadthecontentoftheIRQ Statusregistertodeterminethecause oftheinterruptrequest.IftheFIFO is75% full(asmarked withflag B5 inIRQ Statusregisterand by readingtheFIFO Statusregister),theMCU shouldrespondby reading thedatafromFIFO tomake room fornew incomingreceivedata.When thereceiveoperationisfinished, the interruptissentand the MCU must check how many words are stillpresentinthe FIFO beforeit finishesreading. Ifthereaderdetectsa receiveerror,thecorrespondingerrorflagisset(framingerror,CRC error)inthe IRQ Statusregister,indicatingtotheMCU thatreceptionwas notcompletedcorrectly. 5.12.3.2Data TransmissiontoMCU Beforebeginningdata transmission,the FIFO shouldalways be clearedwitha resetcommand (0x0F). Data transmissionisinitiatedwitha selectedcommand (seeSection5.13).The MCU thencommands the readertodo a continuouswritecommand (0x3D)(seeTable5-7)startingfromregister0x1D. Data written intoregister0x1D istheTX lengthbyte1 (upperand middlenibbles),whilethefollowingbyteinregister 0x1E is the TX lengthbyte 2 (lowernibbleand broken byte length).Note thatthe TX byte length determineswhen the readersends the EOF byte.Afterthe TX lengthbytesare written,FIFO data is loadedinregister0x1F withbytestoragelocations0 to11.Data transmissionbeginsautomaticallyafter thefirstbyteiswrittenintotheFIFO. The loadingofTX lengthbytesand theFIFO can be done witha continuouswritecommand, as theaddressesaresequential. At thestartoftransmission,theflagB7 (IRQ_TX) issetintheIRQ Statusregister.Ifthetransmitdatais shorterthan or equalto 4 bytes,the interruptissentonlyat the end of the transmitoperation.Ifthe number ofbytestobe transmittedishigherorequalto5,thentheinterruptisgenerated.Thisoccursalso when the number of bytesinthe FIFO reaches3. The MCU shouldcheck the IRQ Statusregisterand FIFO Statusregisterand then loadadditionaldata to the FIFO, ifneeded. At the end of the transmit operation,an interruptissenttoinformtheMCU thatthetaskiscomplete.

5.12.4 SerialInterfaceCommunication (SPI)

When an SPI interfaceisutilized,I/Opins,I/O_2,I/O_1,and I/O_0,must be hard wiredaccordingto Table5-7.On power up,theTRF7963A looksforthestatusofthesepins;iftheyarenotthesame (notall high,ornotalllow),thereaderentersintoone oftwo possibleSPI modes:

• SPI withslaveselect or
• SPI withoutslaveselect The choiceofone ofthesemodes overtheothershouldbe made based on theavailableGPIOs and the desiredcontrolofthesystem. The serialcommunicationswork inthesame manner as theparallelcommunicationswithrespecttothe FIFO, except forthe followingcondition.On receivingan IRQ from the reader,the MCU reads the TRF7963A IRQ Statusregistertodeterminehow toservicethereader.Afterthis,theMCU must todo a dummy readtoclearthereader'sIRQ Statusregister.The dummy readisrequiredinSPI mode, because thereader'sIRQ Statusregisterneeds an additionalclockcycletocleartheregister.Thisisnotrequired inparallelmode, because theadditionalclockcycleisincludedintheStopcondition.

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IRQ Status Register Dummy ReadWrite Address Byte (0x6C) No Data Transitions (All High/Low) Don't Care Ignore 0 1 1 0 1 1 0 0 B7 B6 B5 B4 B3 B2 B1 B0 SLAVE SELECT MISO MOSI DATA_CLK No Data Transitions (All High/Low) TRF7963A www.ti.com SLOS758C –DECEMBER 2011–REVISED JANUARY 2013 A procedurefora dummy readisas follows: 1. Startingthedummy read (a) When usingslaveselect(SS):setSS bitlow (b) When notusingSS: startconditioniswhen SCLK ishigh 2. Send addressword toIRQ Statusregister(0x0C)withreadand continuousaddressmode bitssetto1 3. Read 1 byte(8bits)fromIRQ Statusregister(0x0C) 4. Dummy-read 1 bytefromregister0Dh (collisionpositionand interruptmask) 5. Stoppingthedummy read (a) When usingslaveselect(SS):setSS bithigh (b) When notusingSS: stopconditionwhen SCLK ishigh Figure5-14.Procedure forDummy Read Figure5-15.Dummy Read Using SPI With SS 5.12.4.1SerialInterfaceMode WithoutSlaveSelect(SS) The serialinterfacewithoutthe slaveselectpin must use delimitersforthe startand stop conditions. Between thesedelimiters,theaddress,data,and command words can be transferred.Allwords must be 8 bitslongwithMSB transmittedfirst(seeFigure5-16). Copyright© 2011–2013,Texas InstrumentsIncorporated DetailedSystem Description 31 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

CKPH = 1, CKPL = 0 Data Transition is on Data Clock Falling Edge MOSI Valid on Data Clock Rising Edge tSTE,LEAD tSTE,LAG tLO/HI tLO/HI b6 to b1 b0 tSU,SI tHD,SI 1/fUCxCLK No Data Transitions (All High/Low) Switch DATA_CLK Polarity Read Mode CKPH = 0, CKPL = 0 Data Transition is on Data Clock Rising Edge MOSI Valid on Data Clock Falling Edge tSTE,LAG tSU,SO tHD,SO tVALID,SO tSTE,DIS 50 ns Start Condition Stop Condition b7 b6 b5 b4 b3 b2 b1 b0 Data Clock Data In Data Out TRF7963A SLOS758C –DECEMBER 2011–REVISED JANUARY 2013 www.ti.com Figure5-16.SPI WithoutSlaveSelectTiming Inthismode, a risingedge on datain(I/O_7,pin24) whileSCLK ishighresetstheserialinterfaceand preparesittoreceivedata.Data incan change onlywhen SCLK islow,and itisreadby thereaderon the SCLK risingedge.Communicationisterminatedby thestopconditionwhen thedatainfallingedge occurs duringa highSCLK period. 5.12.4.2SerialInterfaceMode With SlaveSelect(SS) The serialinterfaceisinresetwhiletheSlaveSelectsignalishigh.Serialdatain(MOSI) changes on the fallingedge,and isvalidatedinthereaderon therisingedge,as shown inFigure5-17.Communicationis terminatedwhen theSlaveSelectsignalgoes high. Allwords must be 8 bitslongwiththeMSB transmittedfirst. Figure5-17.SPI With SlaveSelectTiming The read command issentout on the MOSI pin,MSB first,inthe firsteightclockcycles.MOSI data changes on thefallingedge,and isvalidatedinthereaderon therisingedge,as shown inFigure5-17. Duringthe writecycle,the serialdata out (MISO) isnot valid.Afterthe lastread command bit(B0)is validatedattheeighthrisingedge ofSCLK, afterhalfa clockcycle,validdatacan be readon theMISO pinatthefallingedge ofSCLK. Ittakeseightclockedges toreadoutthefullbyte(MSB first). When usingthehardwareSPI (forexample,an MSP430 hardwareSPI)toimplementthisfeature,care must be takentoswitchtheSCLK polarityafterwritephase forproperreadoperation.The example clock polarityforthe MSP430-specificenvironmentis shown in the write-modeand read-mode boxes of Figure5-17.See theUSART-SPI chapterforany specificmicrocontrollerfamilyforfurtherinformationon the settingthe appropriateclockpolarity.This clockpolarityswitchmust be done forallread (single, continuous)operations.The MOSI (serialdata out)shouldnot have any transitions(allhighor alllow) duringthereadcycle.The SlaveSelectshouldbe lowduringthewholewriteand readoperation. See Section3.5,SwitchingCharacteristics,forthetimingvaluesshown inFigure5-17. The continuousreadoperationisshown inFigure5-18.

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(All High/Low) Don't Care B7 B6 B5 B4 B3 B2 B1 B0 SLAVE SELECT MISO MOSI DATA_CLK No Data Transitions (All High/Low)B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 TRF7963A www.ti.com SLOS758C –DECEMBER 2011–REVISED JANUARY 2013 Figure5-18.Continuous Read OperationUsing SPI With SlaveSelect Figure5-19.Continuous Read ofRegisters0x00 Through 0x05 Using SPI With SS

5.12.5 DirectMode

Directmode allowsthereadertobe configuredinone oftwo ways. DirectMode 0 (bit6 = 0,as definedinISO Controlregister)allowstheapplicationtouse onlythefront- end functionsof the reader,bypassingthe protocolimplementationin the reader.For transmit functions,theapplicationhas directaccesstothetransmitmodulatorthroughtheMOD pin(pin14).On the receiveside,the applicationhas directaccess to the subcarriersignal(digitizedRF envelope signal)on I/O_6(pin23). DirectMode 1 (bit6 = 1,as definedinISO Controlregister)uses thesubcarriersignaldecoderofthe selectedprotocol(as definedinISO Controlregister).Thismeans thatthe receiveoutputisnot the subcarriersignalbutthedecoded serialbitstreamand bitclocksignals.The serialdataisavailableon I/O_6 (pin23),and the bitclockisavailableon I/O_5 (pin22).The transmitsideisidentical;the applicationhas directcontrolovertheRF modulationthroughtheMOD input.Thismode isprovidedso thatthe applicationcan implementa protocolthathas the same bitcodingas one of the protocols implementedinthereader,butneeds a differentframingformat. Copyright© 2011–2013,Texas InstrumentsIncorporated DetailedSystem Description 33 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

Analog Front End (AFE) 14443A ISO Encoders/Decoders 14443B FeliCa Packetization/Framing Microcontroller Direct Mode 0: Raw RF Sub-Carrier Data Stream Direct Mode 1: Raw Digital ISO Coded Data Without Protocol Frame ISO Mode: Full ISO Framing and Error Checking (Typical Mode) TRF7963A SLOS758C –DECEMBER 2011–REVISED JANUARY 2013 www.ti.com To selectDirectMode, firstchoose which DirectMode toenterby writingB6 intheISO Controlregister. Thisbitdeterminesifthereceiveoutputisthedirectsubcarriersignal(B6 = 0) or theserialdataofthe selecteddecoder.IfB6 = 1,thentheapplicationmust alsodefinewhich protocolshouldbe used forbit decodingby writingtheappropriatesettingintheISO Controlregister. The readeractuallyenterstheDirectMode when B6 (direct)issetto1 intheChip StatusControlregister. Directmode startsimmediately.The writecommand shouldnotbe terminatedwitha stopcondition(see communicationprotocol),because thestopconditionterminatestheDirectMode and clearsB6. Thisis necessaryas theDirectMode uses one ortwo I/Opins(I/O_6and I/O_5).Normal parallelcommunication isnotpossibleinDirectMode. Sendinga stopconditionterminatesDirectMode. Figure5-20shows thedifferentconfigurationsavailableinDirectMode.

• Inmode 0,thereaderisused as an AFE only,and protocolhandlingisbypassed.
• In mode 1, framingisnot done, but SOF and EOF are present.This allowsfora user-selectable framinglevelbased on an existingISO standard.
• In mode 2, data is ISO standardformatted.SOF, EOF, and errorcheckingare removed, so the microprocessorreceivesonlybytesofraw dataviaa 12-byteFIFO. Figure5-20.User-ConfigurableModes

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www.ti.com SLOS758C –DECEMBER 2011–REVISED JANUARY 2013 The stepstoenterDirectMode are listedbelow,usingSPI withSS communicationmethod onlyas one example,as DirectMode(s)arealsopossiblewithparalleland SPI withoutSS. The applicationmust enter DirectMode 0 toaccommodate non-ISO standardcompliantcardtypecommunications.DirectMode can be enteredatany time,so thatifa cardtypestartedwithISO standardcommunications,thendeviated from thestandardafterbeingidentifiedand selected,theabilitytogo intoDirectMode 0 becomes very useful. Step 1:ConfigurepinsI/O_0toI/O_2forSPI withSS Step 2:Setpin12 oftheTRF7963A (ASK/OOK pin)to0 forASK or1 forOOK Step 3:Program theTRF7963A registers The followingregistersneed tobe explicitlysetbeforegoingintoDirectMode. 1. ISO Controlregister(0x01)totheappropriatestandard: – 0x08 forISO14443A (106kbps) – 0x1A forFeliCa212 kbps – 0x1B forFeliCa424 kbps 2. Modulatorand SYS_CLK Register(0x09)totheappropriateclockspeed and modulation: – 0x21 for6.78-MHz clockand OOK (100%) modulation – 0x20 for6.78-MHz clockand ASK 10% modulation – 0x22 for6.78-MHz clockand ASK 7% modulation – 0x23 for6.78-MHz clockand ASK 8.5% modulation – 0x24 for6.78-MHz clockand ASK 13% modulation – 0x25 for6.78-MHz clockand ASK 16% modulation See register0x09 definitionforallotherpossiblevalues. Example registersettingforISO14443A at106 kbps: – ISO Controlregister(0x01)to0x08 – RX No Response WaitTime register(0x07)to0x0E – RX WaitTime register(0x08)to0x07 – ModulatorControlregister(0x09)to0x21 (orany custom modulation) – RX SpecialSettingsregister(0x0A)to0x20 Step 4:EnterDirectMode The followingregistersmust be reprogrammed toenterDirectMode: a. SetbitB6 oftheModulatorand SYS_CLK Controlregister(0x09)to1. b. SetbitB6 oftheISO Controlregister(0x01)to0 forDirectMode 0 (defaultits0) c. SetbitB6 oftheChipStatusControlregister(0x00)to1 toenterDirectMode (donotsend a Stop conditionafterthiscommand) NOTE – Itisimportantthatthe lastwritebe NOT terminatedwithStop condition.For SPI,this means thatSlaveSelect(I/O_4)continuestostaylow. – Sendinga Stop conditionterminatestheDirectMode and clearsbitB6 intheChip Status Controlregister(0x00). NOTE Access toregisters,FIFO,and IRQ isnotavailableduringDirectMode 0. Remember thatthereaderentersDirectMode 0 when bit6 oftheChip StatusControlregister(0x00)is settoa 1,and itstaysinDirectMode 0 untila Stopconditionissentfromthemicrocontroller. Copyright© 2011–2013,Texas InstrumentsIncorporated DetailedSystem Description 35 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

according to the data-coding specified by the standard Decode the subcarrier information according to the standard MOD (Pin 14) IO6 (Pin 23) TRF7963A SLOS758C –DECEMBER 2011–REVISED JANUARY 2013 www.ti.com NOTE The writecommand shouldnot be terminatedwitha Stop condition(forexample,in SPI mode thisisdone by bringingthe SS linehighafterthe registerwrite),because the Stop conditionterminatesthe DirectMode and clearsbit6 of the Chip StatusControlregister (0x00),making ita 0. Figure5-21.EnteringDirectMode 0 Step 5:TransmitdatausingDirectMode The usernow has directcontrolovertheRF modulationthroughtheMOD input. Figure5-22.ControlofRF ModulationUsing MOD The microcontrollerisresponsibleforgeneratingdataaccordingtothecodingspecifiedby theparticular standard.The microcontrollermust generateSOF, EOF, data,and CRC. InDirectMode, theFIFO isnot used and no IRQs are generated.See the applicableISO standardto understandbitand frame definitions. Step 6:ReceivedatausingDirectMode AftertheTX operationiscomplete,thetagrespondstotherequestand thesubcarrierdataisavailableon pinI/O_6.The microcontrollermust decode thesubcarriersignalaccordingtothestandard.Thisincludes decodingtheSOF, databits,CRC, and EOF. The CRC thenmust be checked toverifydataintegrity.The receivedatabytesmust be bufferedlocally. As an example ofthereceivedatabitsand framinglevelaccordingtotheISO14443A standardisshown inFigure5-23(takenfromISO14443 specificationand TRF7963A airinterface).

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/c63 /c63 /c63 128/fc = 9.435 µs = t (106-kbps data rate) 64/fc = 4.719 µs = t time 32/fc = 2.359 µs = t time b x t = 9.44b µs t = 4.72 x µs t = 2.48 1 µs Sequence Y = Carrier for 9.44 µs Sequence Z = Pause for 2 Carrier for Remainder of 9.44 to 3 µs, µs TRF7963A www.ti.com SLOS758C –DECEMBER 2011–REVISED JANUARY 2013 Figure5-23.Receive Data Bitsand Framing Level(ISO14443A) Step 7:ExitDirectMode 0 When an EOF isreceived,datatransmissionisover,and DirectMode 0 can be terminatedby sendinga Stopcondition(theSS signalgoes high).The TRF7963A returnstoISO Mode (normalmode). Copyright© 2011–2013,Texas InstrumentsIncorporated DetailedSystem Description 37 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

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5.13 DirectCommands from MCU toReader

5.13.1 Command Codes

Table5-11liststhevalidcommands thattheMCU can send tothereader. Table5-11.Command Codes Command Command CommentsCode 0x00 Idle 0x03 SoftwareInitialization Same as power on reset 0x0F Reset 0x10 TransmissionwithoutCRC 0x11 TransmissionwithCRC 0x16 BlockReceiver 0x17 EnableReceiver 0x18 TestexternalRF (RSSI atRX inputwithTX on) 0x19 TestinternalRF (RSSI atRX inputwithTX off) 0x1A ReceiverGain Adjust The command code valuesfrom Table 5-11 are substitutedinTable 5-12, Bits0 through4. Also,the most-significantbit(MSB) inTable5-12must be setto1. Table5-12.Address/Command Word BitDistribution Bit Description BitFunction Address Command 0 = addressB7 Command controlbit 0 11 = command 0 = writeB6 Read/Write R/W 01 = read ContinuousB5 Continuousaddressmode Not usedmode B4 Address/Command bit4 Adr 4 Cmd 4 B3 Address/Command bit3 Adr 3 Cmd 3 B2 Address/Command bit2 Adr 2 Cmd 2 B1 Address/Command bit1 Adr 1 Cmd 1 B0 Address/Command bit0 Adr 0 Cmd 0 The MSB determinesifthe word isto be used as a command or address.The lasttwo columns of Table 5-12 show the functionof separatebitsdepending on whether address or command iswritten. Command mode is used to enter a command resultingin reader action(forexample, initialize transmission,enablereader,orturnthereaderon oroff).

5.13.2 Reset (0x0F)

The resetcommand clearstheFIFO contentsand FIFO Statusregister(0x1C).Italsoclearstheregister storingthecollisionerrorlocation(0x0E).

5.13.3 TransmissionWith CRC (0x11)

The transmissioncommand must be sentfirst,followedby transmissionlengthbytes,and FIFO data.The readerstartstransmittingafterthe firstbyteisloadedintothe FIFO. The CRC byteisincludedinthe transmittedsequence.

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5.13.4 TransmissionWithoutCRC (0x10)

The transmissioncommand must be sentfirst,followedby transmissionlengthbytes,and FIFO data.The readerstartstransmittingafterthe firstbyteisloadedintothe FIFO. Thisisthe same as the previous section(Section5.13.3),exceptthattheCRC isnotincluded.

5.13.5 Block Receiver(0x16)

The blockreceivercommand putsthedigitalpartofreceiver(bitdecoderand framer)inresetmode. This isusefulin an extremelynoisyenvironment,where the noiselevelcouldotherwisecause a constant switchingofthesubcarrierinputofthedigitalpartofthereceiver.The receiver(ifnotinreset)would tryto catcha SOF signal,and ifthenoisepatternmatched theSOF pattern,an interruptwould be generated, falselysignalingthestartofan receiveoperation.A constantflowofinterruptrequestscan be a problem fortheexternalsystem (MCU), so theexternalsystem can stopthisby puttingthereceivedecodersin resetmode. The resetmode can be terminatedintwo ways: The externalsystemcan send theenablereceivercommand (seeSection5.13.6). The resetmode isautomaticallyterminatedattheend ofa transmitoperation. The receivercan stayinresetafterend oftransmitiftheRX WaitTime register(0x08)isset.Inthiscase, thereceiverisenabledattheend ofthewaittimefollowingthetransmitoperation.

5.13.6 Enable Receiver(0x17)

Thiscommand clearstheresetmode inthedigitalpartofthereceiveriftheresetmode was enteredby theblockreceivercommand.

5.13.7 TestInternalRF (RSSI atRX InputWith TX On) (0x18)

The leveloftheRF carrieratRF_IN1 and RF_IN2 inputsismeasured.Operatingrangebetween 300 mV P and 2.1VP (stepsizeis300 mV). The two valuesare reportedintheRSSI Levelsregister(0x0F).The command isintendedfordiagnosticpurposesto setcorrectRF_IN levels.Optimum RFIN inputlevelis approximately1.6VP orcode 5 to6.The nominalrelationshipbetween theRF peak leveland RSSI code isdescribedinTable5-13and inSection5.7.1.1. NOTE Ifthecommand isexecutedimmediatelyafterpower-upand beforeany communicationwith tag was performed,the command must be preceded by the Enable RX command. The Check RF commands requirefulloperation,so the receivermust be activatedby enable receiveorby a normaltagcommunicationfortheCheck RF command towork properly. Table5-13.TestInternalRF RF_IN1 (mV P): 300 600 900 1200 1500 1800 2100 Decimal Code: 1 2 3 4 5 6 7 BinaryCode: 001 010 011 001 101 011 111

5.13.8 TestExternalRF (RSSI atRX InputWith TX Off)(0x19)

Thiscommand can be used inactivemode when theRF receiverison butRF outputisoff.Thismeans bitB1 = 1 intheChip StatusControlregister.The levelofRF signalreceivedon theantennaismeasured and reportedintheRSSI Levelsregister(0x0F).The relationbetween the3-bitcode and theexternalRF fieldstrength[A/m]must be determinateby calculationorby experimentsforeach antennatype,because theantennaQ and connectiontotheRF inputinfluencetheresult.The nominalrelationbetween theRF peak topeak voltageintheRF_IN1 inputand RSSI code isshown inTable5-14and inSection5.7.1.2. Copyright© 2011–2013,Texas InstrumentsIncorporated DetailedSystem Description 39 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

SLOS758C –DECEMBER 2011–REVISED JANUARY 2013 www.ti.com NOTE Ifthecommand isexecutedimmediatelyafterpower-upand beforeany communicationwith tag was performed,the command must be preceded by the Enable RX command. The Check RF commands requirefulloperation,so thereceivermust be activatedby enableRX orby a normaltagcommunicationfortheCheck RF command towork properly. Table5-14.TestExternalRF RF_IN1 (mV P): 40 60 80 100 140 180 300 Decimal Code: 1 2 3 4 5 6 7 BinaryCode: 001 010 011 001 101 011 111

5.13.9 ReceiverGain Adjust(0x1A)

Thiscommand shouldbe executedwhen theMCU determinesthatno tagresponseisdetectedand when theRF and receiversareon.When thiscommand isreceived,thereaderobservesthedigitizedreceiver output.Ifmore thantwo edges areobservedin100 ms, thewindow comparatorvoltageisincreased.The procedureisrepeateduntilthenumber ofedges (changesoflogicalstate)ofthedigitizedreceptionsignal islessthan2 (in100 ms).The command can reducetheinputsensitivityin5-dB incrementsup to15 dB. Thiscommand ensuresbetteroperationina noisyenvironment.The gainsettingisresettomaximum gain atEN = 0,POR = 1.

5.13.10 RegisterPreset

Afterpower-upand theEN pinlow-to-hightransition,theregistersare ina defaultmode, which must be changed by writingthe desiredISO protocolsettingsto the ISO Controlregister.The low-leveloption registers(0x02to0x0B) are automaticallyconfiguredtothenew protocolparameters.Afterselectingthe protocol,itis possibleto change some low-levelregistercontentsifneeded. However, changing to anotherprotocoland then back reloadsthe defaultsettings;therefore,the custom settingsmust be reloaded. The Clo0 and Clo1 bitsin the Modulatorand SYS_CLK Controlregister(0x09),which definethe microcontrollerfrequencyavailableon the SYS_CLK pin,are the only two bitsin the configuration registersthatarenotclearedduringprotocolselection.

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6 RegisterDescription

6.1 RegisterOverview

Table 6-1 liststhe registersavailableinthe TRF7963A. These registersare describedinthe following sections. Table6-1.RegisterOverview Address Register Read/Write Section(hex) Main ControlRegisters Section0x00 ChipStatusControl R/W 6.1.1.1 Section0x01 ISO Control R/W 6.1.1.2 ProtocolSub-SettingRegisters Section0x02 ISO14443B TX Options R/W 6.1.2.1 Section0x03 ISO14443A HighBitRate Options R/W 6.1.2.2 Section0x06 TX Pulse-LengthControl R/W 6.1.2.3 Section0x07 RX No Response Wait R/W 6.1.2.4 Section0x08 RX WaitTime R/W 6.1.2.5 Section0x09 Modulatorand SYS_CLK Control R/W 6.1.2.6 Section0x0A RX SpecialSetting R/W 6.1.2.7 Section0x0B Regulatorand I/OControl R/W 6.1.2.8 StatusRegisters Section0x0C IRQ Status R 6.1.3.1 Section0x0D CollisionPositionand InterruptMask Register R/W 6.1.3.2 Section0x0E CollisionPosition R 6.1.3.2 Section0x0F RSSI Levelsand OscillatorStatus R 6.1.3.3 FIFO Registers Section0x1A Test R/W 6.1.4.1 Section0x1B Test R/W 6.1.4.2 Section0x1C FIFO Status R 6.1.5.1 Section0x1D TX LengthByte1 R/W 6.1.5.2 Section0x1E TX LengthByte2 R/W 6.1.5.2 0x1F FIFO I/ORegister R/W Copyright© 2011–2013,Texas InstrumentsIncorporated RegisterDescription 41 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

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6.1.1 Main ConfigurationRegisters

6.1.1.1 Chip StatusControlRegister(0x00)

Table6-2.Chip StatusControlRegister(0x00) Function:Controlofpower mode, RF on/off,AGC, AM/PM, DirectMode DefaultSettings:Registerdefaultis0x01.ItispresetatEN = L orPOR = H BitNo. BitName Function Description Standbymode keeps allsupplyregulatorsand the13.56-MHz SYS_CLK1 = StandbyMode oscillatorrunning(typicalstart-uptimetofulloperationis100 µs).B7 stby 0 = ActiveMode ActiveMode (default) ProvidesuserdirectaccesstoAFE (DirectMode 0)orallowsusertoadd 1 = DirectMode 0/1 theirown framing(DirectMode 1).Bit6 ofISO Controlregistermust be set by userbeforeenteringDirectMode 0 or1.B6 direct Uses SPI orparallelcommunicationwithautomaticframingand ISO0 = ISO Mode (default) decoders 1 = RF outputactive Transmitteron,receiverson B5 rf_on 0 = RF outputnotactive Transmitteroff TX_OUT (pin5)= 8-Ω outputimpedance1 = Halfoutputpower P = 100 mW (+20dBm) at5 V,P = 33 mW (+15dBm) at3.3V B4 rf_pwr TX_OUT (pin5)= 4-Ω outputimpedance0 = Fulloutputpower P = 200 mW (+23dBm) at5 V,P = 70 mW (+18dBm) at3.3V 1 = SelectsMain RX RX_IN1 inputisusedinput B3 pm_on 0 = SelectsAux RX RX_IN2 inputisusedinput 1 = AGC on EnablesAGC (AGC gaincan be setinregister0x0A) B2 agc_on 0 = AGC off AGC blockisdisabled 1 = Receiveractivated Forcesenablingofreceiverand TX oscillator.Used forexternalfieldforexternalfield measurement.B1 rec_on measurement 0 = Automaticenable Allowsenableofthereceiverviabit5 ofthisregister 1 = 5-V operation B0 vrs5_3 SelectstheVIN voltagerange 0 = 3-V operation

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6.1.1.2 ISO ControlRegister(0x01)

Table6-3.ISO ControlRegister(0x01) Function:ControlstheselectionofISO standardprotocol,DirectMode, and receiveCRC DefaultSettings:Registerdefaultis0x02 .ItisresetatEN = L orPOR = H. BitNo. BitName Function Description 1 = no RX CRC (CRC notpresentintheresponse)B7 rx_crc_n CRC receiveselection 0 = RX CRC (CRC ispresentintheresponse) Directmode type 0 = DirectMode 0B6 dir_mode selection 1 = DirectMode 1 0 = RFID modeB5 rfid RFID /Reserved 1 = Reserved(shouldbe setto0) B4 iso_4 RFID B3 iso_3 RFID See Table6-4forB0:B4 settingsbased on theISO protocolthattheB2 iso_2 RFID applicationrequires B1 iso_1 RFID B0 iso_0 RFID Table6-4.ISO ControlRegister:ISO_4 toISO_0 ISO_4 ISO_3 ISO_2 ISO_1 ISO_0 Protocol Remarks 0 1 0 0 0 ISO14443A RX bitrate,106 kbps 0 1 0 0 1 ISO14443A RX highbitrate,212 kbps RX bitrate(1) 0 1 0 1 0 ISO14443A RX highbitrate,424 kbps 0 1 0 1 1 ISO14443A RX highbitrate,848 kbps 0 1 1 0 0 ISO14443B RX bitrate,106 kbps 0 1 1 0 1 ISO14443B RX highbitrate,212 kbps RX bitrate(1) 0 1 1 1 0 ISO14443B RX highbitrate,424 kbps 0 1 1 1 1 ISO14443B RX highbitrate,848 kbps 1 1 0 1 0 FeliCa212 kbps 1 1 0 1 1 FeliCa424 kbps (1) ForISO14443A/B,when bitrateofTX isdifferentfromRX, settingscan be done inREG (0x02or0x03) Copyright© 2011–2013,Texas InstrumentsIncorporated RegisterDescription 43 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

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6.1.2 ProtocolSub-SettingRegisters

6.1.2.1 ISO14443B TX Options Register(0x02)

Table6-5.ISO14443B TX Options Register(0x02) Function:SelectstheISO subsetsforISO14443B – TX DefaultSettings:0x00 atPOR = H orEN = L BitNo. BitName Function Description B7 egt2 TX EGT timeselectMSB Threebitcode definesthenumber ofetu(0to7)thatseparatetwoB6 egt1 TX EGT timeselect characters.ISO14443B TX only. B5 egt0 TX EGT timeselectLSB 1 = EOF → 0 length11 etuB4 eof_l0 0 = EOF → 0 length10 etu 1 = SOF → 1 length03 etuB3 sof_l1 0 = SOF → 1 length02 etu ISO14443B TX only 1 = SOF → 0 length11 etuB2 sof_l0 0 = SOF → 0 length10 etu 1 = EGT aftereach byteB1 l_egt 0 = EGT afterlastbyteisomitted B0 Unused

6.1.2.2 ISO14443A High-Bit-Rateand ParityOptions Register(0x03)

Table6-6.ISO14443A High-Bit-Rateand ParityOptions Register(0x03) Function:SelectstheISO subsetsforISO14443A – TX DefaultSettings:0x00 atPOR = H orEN = L,and ateach writetoISO Controlregister BitNo. BitName Function Description TX bitratedifferentthanRX bitB7 dif_tx_br ValidforISO14443A/B highbitraterateenable B6 tx_br1 tx_br1= 0,tx_br= 0:106 kbps tx_br1= 0,tx_br= 1:212 kbpsTX bitrate B5 tx_br0 tx_br1= 1,tx_br= 0:424 kbps tx_br1= 1,tx_br= 1:848 kbps 1 = parityodd exceptlastbyte,B4 parity-2tx whichiseven forTX ForISO14443A highbitratecodingand decoding 1 = parityodd exceptlastbyte,B3 parity-2rx whichiseven forRX B2 Unused B1 Unused B0 Unused

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6.1.2.3 TX Pulse Length ControlRegister(0x06)

The lengthofthemodulationpulseisdefinedby theprotocolselectedintheISO Controlregister(0x01). With a high-Qantenna,the modulationpulseistypicallyprolonged,and the tag detectsa longerpulse thanintended.For such cases,themodulationpulselengthcan be correctedby usingtheTX pulselength register0x06.Iftheregistercontainsallzeros,thenthepulselengthisgovernedby theprotocolselection. Iftheregistercontainsa valueotherthan0x00,thepulselengthisequaltothevalueoftheregisterin Table6-7.TX Pulse Length ControlRegister(0x06) Function:ControlsthelengthofTX pulse DefaultSettings:Defaultissetto0x00 atPOR = H orEN = L and ateach writetoISO Controlregister. BitNo. BitName Function Description B7 Pul_p2 PulselengthMSB B6 Pul_p1 The pulserangeis73.7ns to18.8µs (1to255),stepsize73.7ns B5 Pul_p0 Allbitslow(00):pulselengthcontrolisdisabled B4 Pul_c4 The followingdefaulttimingsarepresetby theISO Controlregister(0x01): B3 Pul_c3 2.36µs → ISO14443A at106 kbps 1.4µs → ISO14443A at212 kbpsB2 Pul_c2 737 ns → ISO14443A at424 kbpsB1 Pul_c1 442 ns → ISO14443A at848 kbps;pulselengthcontroldisabled B0 Pul_c0 PulselengthLSB Copyright© 2011–2013,Texas InstrumentsIncorporated RegisterDescription 45 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

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6.1.2.4 RX No Response Wait Time Register(0x07)

The RX no responsetimeriscontrolledby theRX No Response WaitTime register.Thistimermeasures thetimefromthestartofslotintheanticollisionsequence untilthestartoftagresponse.Ifthereisno tag responseinthedefinedtime,an interruptrequestissentand a flagissetinIRQ StatusControlregister (0x0C).Thisenablestheexternalcontrollertobe relievedofthetaskofdetectingempty slots.The wait timeisstoredintheregisterinincrementsof37.76µs.Thisregisterisalsopreset,automatically,forevery new protocolselection. Table6-8.RX No Response Wait Time Register(0x07) Function:Definesthetimewhen "noresponse"interruptissent DefaultSettings:Defaultissetto0x0E atPOR = H orEN = L and ateach writetoISO Controlregister. BitNo. BitName Function Description B7 NoResp7 No responseMSB B6 NoResp6 B5 NoResp5 Definesthetimewhen no responseinterruptissent.Itstartsfromtheend of TX EOF. RX no responsewaitrangeis37.76µs to9628 µs (1to255).StepB4 NoResp4 sizeis37.76µs. B3 NoResp3 The followingdefaulttimingsarepresetby theISO Controlregister(0x01):B2 NoResp2 529 µs → forallprotocols B1 NoResp1 B0 NoResp0 No responseLSB

6.1.2.5 RX Wait Time Register(0x08)

The RX waittimetimeriscontrolledby thevalueintheRX WaitTime register.Thistimerdefinesthetime aftertheend ofthetransmitoperationinwhich thereceivedecodersare notactive(heldinresetstate). Thispreventsincorrectdetectionsresultingfrom transientsfollowingthetransmitoperation.The valueof theRX waittimeregisterdefinesthistimeinincrementsof9.44µs.Thisregisterispresetateverywriteto ISO Controlregisteraccordingtotheminimum tagresponsetimedefinedby each standard. Table6-9.RX Wait Time Register(0x08) Function:DefinesthetimeafterTX EOF when theRX inputisdisregarded;forexample,toblockoutelectromagneticdisturbance generatedby therespondingcard. DefaultSettings:Defaultissetto0x1F atPOR = H orEN = L and ateach writetotheISO controlregister. BitNo. BitName Function Description B7 Rxw7 B6 Rxw6 Definesthe timeafterthe TX EOF duringwhich the RX inputisignored.B5 Rxw5 Time startsfromtheend ofTX EOF. B4 Rxw4 RX waitrangeis9.44µs to2407 µs (1to255).Stepsizeis:9.44µs.RX waittime B3 Rxw3 The followingdefaulttimingsarepresetby theISO Controlregister(0x01):B2 Rxw2 9.44µs → FeliCa 66 µs → ISO14443A and BB1 Rxw1 B1 Rxw0

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6.1.2.6 Modulatorand SYS_CLK ControlRegister(0x09)

The frequencyofSYS_CLK (pin27)isprogrammableby thebitsB4 and B5 ofthisregister.The frequency of the TRF7963A system clockoscillatoris dividedby 1, 2 or 4 resultingin availableSYS_CLK frequenciesof13.56MHz or6.78MHz or3.39MHz. The ASK modulationdepthiscontrolledby bitsB0, B1 and B2. The range ofASK modulationis7% to 30% or 100% (OOK). The selectionbetween ASK and OOK (100%) modulationcan alsobe done using directinputOOK (pin12).The directcontrolofOOK/ASK usingOOK pinisonlypossibleifthefunctionis enabledby settingB6 = 1 (en_ook_p)inthisregister(0x09)and theISO Controlregister(0x01,B6 = 1). When configuredthisway,theMOD (pin14)isused as inputforthemodulationsignal. Table6-10.Modulatorand SYS_CLK ControlRegister(0x09) Function:Controlsthemodulationinputand depth,ASK /OOK controland clockoutputtoan externalsystem(anMCU) DefaultSettings:Defaultissetto0x11 atPOR = H orEN = L,and ateach writetotheISO Controlregister,exceptClo1and Clo0. BitNo. BitName Function Description B7 Unused Enable ASK/OOK pin(pin12) for"on theflychange"between any 1 = enablesexternalselectionof pre-selectedASK modulationas definedby B0 to B2 and OOK ASK orOOK modulation modulation.B6 en_ook_p 0 = defaultoperationas defined IfB6 issetto1,pin12 isconfiguredas follows: inbitsB0 toB2 ofthisregister 1 = OOK modulation 0 = Modulationas definedinB0 toB2 (0x09) Clo1 Clo0 SYS_CLK Output B5 Clo1 SYS_CLK outputfrequencyMSB 0 0 Disabled 0 1 3.39MHz 1 0 6.78MHz B4 Clo0 SYS_CLK outputfrequencyLSB 1 1 13.56MHz 1 = setspin12 (ASK/OOK) as an Fortestand measurement purpose.ASK/OOK pin12 can be used B3 en_ana analogoutput tomonitortheanalogsubcarriersignalbeforethedigitizingwithDC levelequaltoAGND.0 = default Pm2 Pm1 Pm0 ModulationType and Percentage B2 Pm2 ModulationdepthMSB 0 0 0 ASK 10% 0 0 1 OOK (100%) 0 1 0 ASK 7% B1 Pm1 Modulationdepth 0 1 1 ASK 8.5% 1 0 0 ASK 13% 1 0 1 ASK 16% B0 Pm0 ModulationdepthLSB 1 1 0 ASK 22% 1 1 1 ASK 30% Copyright© 2011–2013,Texas InstrumentsIncorporated RegisterDescription 47 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

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6.1.2.7 RX SpecialSettingRegister(0x0A)

Table6-11.RX SpecialSettingRegister(0x0A) Function:Setsthegainsand filtersdirectly DefaultSettings:Defaultissetto0x40 atPOR = H orEN = L,and ateach writetotheISO Controlregister(0x01).When bitsB7,B6,B5 and B4 areallzero,thefiltersaresetforISO14443B (240kHz to1.4MHz). BitNo. BitName Function Description B7 C212 Bandpass 110 kHz to570 kHz Appropriatefor212-kHzsubcarriersystem(FeliCa) B6 C424 Bandpass 200 kHz to900 kHz AppropriateforManchester-coded848-kHzsubcarrierused inB5 M848 Bandpass 450 kHz to1.5MHz ISO14443A Bandpass 100 kHz to1.5MHz Appropriateforhighestbitrate(848kbps)used inhigh-bit-rateB4 hbt Gain reducedfor18 dB ISO14443 B3 gd1 00 = gainreduction0 dB 01 = gainreductionfor5 dB SetstheRX gainreductionand reducessensitivity10 = gainreductionfor10 dBB2 gd2 11 = gainreductionfor15 dB AGC activationlevelchanged fromfivetimesthedigitizinglevelto threetimesthedigitizinglevel.B1 agcr AGC activationlevelchange 1 = 3x 0 = 5x AGC actioncan be done any timeduringreceiveprocess.Itisnot limitedtothestartofreceive("maxhold").B0 no-lim AGC actionisnotlimitedintime 1 = continuously,no timelimit 0 = 8 subcarrierpulses The firstfourstepsof the AGC controlare comparatoradjustment.The second threestepsare gain reductiondone automaticallyby AGC control.The AGC isturnedon afterTX. The firstgainand filteringstagefollowingtheRF envelopedetectorhas a nominalgainof15,and the3- dB band-passfrequenciesareadjustableintherangefrom100 kHz to400 kHz forhighpass and 600 kHz to 1.5 MHz forlow pass.The nextgainand filteringstagehas a nominalgainof 8, and the frequency characteristicidenticaltofirststage.The filtersettingisdone automaticallywithinternalpresetforeach new selectionofcommunicationstandardintheISO Controlregister.Additionalcorrectionscan be done by directlywritingintotheRX SpecialSettingregister. The second receivergainstageand digitizerstageare includedintheAGC loop.The AGC loopcan be activatedby settingthe bitB2 = 1 (agc-on)in the Chip StatusControlregister.Ifactivatedthe AGC monitorsthesignallevelattheinputofdigitizingstage.Ifthesignallevelissignificantlyhigherthanthe digitizingthresholdlevel,thegainreductionisactivated.The signallevel,atwhichtheactionisstarted,is by defaultfivetimesthedigitizingthresholdlevel.Itcan be reducedtothreetimesthedigitizinglevelby settingbitB1 = 1 (agcr)intheRX SpecialSettingregister. The AGC actiontypicallyfinishesafterfoursubcarrierpulses.By default,theAGC actionisblockedafter firstfew pulsesof subcarriersignalso AGC cannot interferewithsignalreceptionduringrestof data packet.Incertaincases,thisisnotoptimal,so thisblockingcan be removed by settingB0 = 1 (no_lim)in theRX SpecialSettingregister. NOTE The settingofbitsb4,b5,b6,and b7 tozeroselectsbandpass characteristicof240 kHz to 1.4 MHz. This isappropriateforISO14443B, FeliCaprotocol,and ISO14443A higherbit rates212 kbps and 424 kbps.

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6.1.2.8 Regulatorand I/OControlRegister(0x0B)

Table6-12.Regulatorand I/OControlRegister(0x0B) Function:Controlthethreevoltageregulators DefaultSettings:Defaultissetto0x87 atPOR = H orEN = L BitNo. BitName Function Description Automaticsystemsettings: VDD_RF = VIN – 250 mV 0 = Manual system VDD_A = VIN – 250 mVB7 auto_reg 1 = Automaticsystem VDD_X = VIN – 250 mV, butnothigherthan3.4V Manual systemsettings: See B2 toB0 Internalpeak detectorsaredisabled,receiverinputs(RX_IN1 and Supportforexternalpower RX_IN2) acceptexternallydemodulatedsubcarrier.AtthesameB6 en_ext_pa amplifier time,theASK/OOK pinbecomes modulationoutputforexternalTX amplifier. When B5 = 1,maintainstheoutputdrivingcapabilitiesoftheI/O1 = EnablelowperipheralB5 io_low pinsconnectedtothelevelshifterunderlow-voltageoperation.communicationvoltage Shouldbe set1 when VDD_I/O voltageisbetween 1.8V and 2.7V. B4 Unused No function Defaultis0. B3 Unused No function Defaultis0. B2 vrs2 VoltagesetMSB vrs3_5= L: B1 vrs1 VDD_RF, VDD_A, VDD_X range2.7V to3.4V. B0 vrs0 VoltagesetLSB See Table6-13throughTable6-16. Table6-13.Supply RegulatorSetting,Manual 5-V System Option BitsSettinginControlRegister Register Action B7 B6 B5 B4 B3 B2 B1 B0 00 1 5-V system 0B 0 Manual regulatorsetting 0B 0 1 1 1 VDD_RF = 5 V,VDD_A = 3.5V,VDD_X = 3.4V 0B 0 1 1 0 VDD_RF = 4.9V,VDD_A = 3.5V,VDD_X = 3.4V 0B 0 1 0 1 VDD_RF = 4.8V,VDD_A = 3.5V,VDD_X = 3.4V 0B 0 1 0 0 VDD_RF = 4.7V,VDD_A = 3.5V,VDD_X = 3.4V 0B 0 0 1 1 VDD_RF = 4.6V,VDD_A = 3.5V,VDD_X = 3.4V 0B 0 0 1 0 VDD_RF = 4.5V,VDD_A = 3.5V,VDD_X = 3.4V 0B 0 0 0 1 VDD_RF = 4.4V,VDD_A = 3.5V,VDD_X = 3.4V 0B 0 0 0 0 VDD_RF = 4.3V,VDD_A = 3.5V,VDD_X = 3.4V Copyright© 2011–2013,Texas InstrumentsIncorporated RegisterDescription 49 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

SLOS758C –DECEMBER 2011–REVISED JANUARY 2013 www.ti.com Table6-14.Supply RegulatorSetting,Manual 3-V System Option BitsSettinginControlRegister Register Action B7 B6 B5 B4 B3 B2 B1 B0 00 0 3-V system 0B 0 Manual regulatorsetting 0B 0 1 1 1 VDD_RF = 3.4V,VDD_A = 3.4V,VDD_X = 3.4V 0B 0 1 1 0 VDD_RF = 3.3V,VDD_A = 3.3V,VDD_X = 3.3V 0B 0 1 0 1 VDD_RF = 3.2V,VDD_A = 3.2V,VDD_X = 3.2V 0B 0 1 0 0 VDD_RF = 3.1V,VDD_A = 3.1V,VDD_X = 3.1V 0B 0 0 1 1 VDD_RF = 3.0V,VDD_A = 3.0V,VDD_X = 3.0V 0B 0 0 1 0 VDD_RF = 2.9V,VDD_A = 2.9V,VDD_X = 2.9V 0B 0 0 0 1 VDD_RF = 2.8V,VDD_A = 2.8V,VDD_X = 2.8V 0B 0 0 0 0 VDD_RF = 2.7V,VDD_A = 2.7V,VDD_X = 2.7V Table6-15.Supply RegulatorSetting,Automatic 5-V System Option BitsSettinginControlRegister Register Action B7 B6 B5 B4 B3 B2 (1) B1 B0 00 1 5-V system 0B 1 x 1 1 Automaticregulatorsetting250-mV difference 0B 1 x 1 0 Automaticregulatorsetting350-mV difference 0B 1 x 0 0 Automaticregulatorsetting400-mV difference (1) x = don'tcare Table6-16.Supply RegulatorSetting,Automatic 3-V System Option BitsSettinginControlRegister Register Action B7 B6 B5 B4 B3 B2 (1) B1 B0 00 0 3-V system 0B 1 x 1 1 Automaticregulatorsetting250-mV difference 0B 1 x 1 0 Automaticregulatorsetting350-mV difference 0B 1 x 0 0 Automaticregulatorsetting400-mV difference (1) x = don'tcare

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6.1.3 StatusRegisters

6.1.3.1 IRQ StatusRegister(0x0C)

Table6-17.IRQ StatusRegister(0x0C) Function:InformationavailableaboutTRF7963A IRQ and TX/RX status DefaultSettings:Defaultissetto0x00 atPOR = H orEN = L,and ateach writetotheISO ControlRegister0x01.Itisalsoautomatically resetattheend ofa readphase.The resetalsoremoves theIRQ flag. BitNo. BitName Function Description SignalsthatTX isinprogress.The flagissetatthestartofTX butB7 Irq_tx IRQ setdue toend ofTX theinterruptrequest(IRQ = 1)issentwhen TX isfinished. SignalsthatRX SOF was receivedand RX isinprogress.The flag B6 Irg_srx IRQ setdue toRX start issetatthestartofRX buttheinterruptrequest(IRQ = 1)issent when RX isfinished. Signalswhen theFIFO ishighorlow(morethan8 bitsduringRX orB5 Irq_fifo FIFO ishighorlow lessthan4 bitsduringTX).See Section5.12.2fordetails. IndicatesreceiveCRC erroronlyifB7 (noRX CRC) ofISO ControlB4 Irq_err1 CRC error registerissetto0. B3 Irq_err2 Parityerror IndicatesparityerrorforISO14443A B2 Irq_err3 ByteframingorEOF error Indicatesframingerror CollisionerrorforISO14443A . Bitissetifmore then 6 or 7 (as definedin register0x01) are detectedinsideone bitperiodofB1 Irq_col Collisionerror ISO14443A 106 kbit/s. Collisionerrorbitcan alsobe triggeredby externalnoise. No responsewithinthe"No-responsetime"definedinRX No-B0 Irq_noresp No-responsetimeinterrupt responseWaitTime register(0x07). To reset(clear)the register0x0C and the IRQ line,the registermust be read.Duringtransmit,the decoder is disabled,and only bitsB5 and B7 can be changed. During receive,only bitB6 can be changed,butdoes nottriggertheIRQ lineimmediately.The IRQ signalissetattheend ofthetransmitor receivephase. Copyright© 2011–2013,Texas InstrumentsIncorporated RegisterDescription 51 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

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6.1.3.2 CollisionPositionand InterruptMask Registers(0x0D and 0x0E)

Table6-18.CollisionPositionand InterruptMask Register(0x0D) DefaultSettings:Defaultissetto0x3E atPOR = H and EN = L.Collisionbitsresetautomaticallyafterreadoperation. BitNo. BitName Function Description B7 Col9 BitpositionofcollisionMSB SupportsISO14443A B6 Col8 Bitpositionofcollision B5 En_irq_fifo InterruptenableforFIFO Default= 1 B4 En_irq_err1 InterruptenableforCRC Default= 1 B3 En_irq_err2 InterruptenableforParity Default= 1 InterruptenableforFramingB2 En_irq_err3 Default= 1errororEOF B1 En_irq_col Interruptenableforcollisionerror Default= 1 B0 En_irq_noresp Enablesno-responseinterrupt Default= 0 Table6-19.CollisionPositionRegister(0x0E) Function:Displaysthebitpositionofcollisionorerror DefaultSettings:Defaultissetto0x00 atPOR = H and EN = L.Automaticallyresetafterreadoperation. BitNo. BitName Function Description B7 Col7 BitpositionofcollisionMSB B6 Col6 B5 Col5 ISO14443A mainlysupported;intheotherprotocols,thisregisterB4 Col4 shows thebitpositionoferror.Eitherframe,SOF/EOF, parity,or B3 Col3 CRC error. B2 Col2 B1 Col1 B0 Col0 BitpositionofcollisionLSB

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6.1.3.3 RSSI Levelsand OscillatorStatusRegister(0x0F)

Table6-20.RSSI Levelsand OscillatorStatusRegister(0x0F) Function:Displaysthesignalstrengthon bothreceptionchannelsand RF amplitudeduringRF-offstate.The RSSI valuesarevalidfrom receptionstartuntilthestartofthenexttransmission. BitNo. BitName Function Description B7 Unused B6 osc_ok Crystaloscillatorstableindicator13.56-MHz frequencystable(approximately200 µs) MSB RSSI valueofauxiliaryRXB5 rssi_x2 Auxiliarychannelisby defaultRX_IN2. The inputcan be swapped(RX_IN2) by B3 = 1 (ChipStateControlregister).If"swapped",theauxiliaryB4 rssi_x1 AuxiliarychannelRSSI channelisconnectedtoRX_IN1 and theauxiliaryRSSI represents MSB RSSI valueofauxiliaryRX thesignallevelatRX_IN1.B3 rssi_x0 (RX_IN2) MSB RSSI valueofMain RXB2 rssi_2 (RX_IN1) Activechannelisthedefaultand can be setwithoptionbitB3 = 0 ofB1 rssi_1 Main channelRSSI theChipStatusControlregister(0x00). LSB RSSI valueofMain RXB0 rssi_0 (RX_IN1) RSSI measurement block is measuring the demodulated envelope signal(exceptin case of direct command forRF amplitudemeasurement describedlaterindirectcommands section).The measuring system islatchingthe peak value,so the RSSI levelcan be read afterthe end of receivepacket.The RSSI valueisresetduringnext transmitactionof the reader,so the new tag response levelcan be measured. The RSSI levelscalculatedto the RF_IN1 and RF_IN2 are shown in Section5.7.1.1and modulationlevelofRF signalmeasured on one sideenvelope(positiveornegative). Copyright© 2011–2013,Texas InstrumentsIncorporated RegisterDescription 53 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

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6.1.4 TestRegisters

6.1.4.1 TestRegister(0x1A)

Table6-21.TestRegister(0x1A)(forTestor DirectUse) DefaultSettings:Defaultissetto0x00 atPOR = H and EN = L. BitNo. BitName Function Description B7 OOK_Subc_In Subcarrierinput OOK Pinbecomes decoderdigitalinput MOD_Subc_OuB6 Subcarrieroutput MOD Pinbecomes receiversubcarrieroutputt B5 MOD_Direct DirectTX modulationand RX reset MOD Pinbecomes receiversubcarrieroutput 0 = Firststage outputused foranalog out and digitizingB4 o_sel Firststageoutputselection 1 = Second stageoutputused foranalogoutand digitizing B3 low2 Second stagegain-6dB,HP cornerfrequency/2 B2 low1 Firststagegain-6dB,HP cornerfrequency/2 B1 zun Inputfollowerstest B0 Test_AGC AGC test,AGC levelisseen on rssi_210bits

6.1.4.2 TestRegister(0x1B)

Table6-22.TestRegister(0x1B)(forTestor DirectUse) DefaultSettings:Defaultissetto0x00 atPOR = H and EN = L.When a test_decortest_ioisset,IC isswitchedtotestmode. TestMode persistsuntila stopconditionarrives.Atstopconditionthetest_decand test_iobitsarecleared. BitNo. BitName Function Description B7 test_rf_levelRF leveltest B3 test_io1 I/Otest Not implemented B2 test_io0 B1 test_dec Decoder testmode B0 clock_su Coder clock13.56MHz Forfastertestofcoders

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6.1.5 FIFO ControlRegisters

6.1.5.1 FIFO StatusRegister(0x1C)

Table6-23.FIFO StatusRegister(0x1C) Function:Low nibblesofcompletebytestobe transferredthroughFIFO.Informationabouta brokenbyteand number ofbitstobe transferredfromit BitNo. BitName Function Description B7 RFU B7 = 0 Reservedforfutureuse (RFU) Indicatesthat9 bytesarealreadyintheFIFO (forRX) (alsoseeB6 Fhil FIFO levelhigh register0x0C bit5) Indicatesthatonly3 bytesareintheFIFO (forTX) (alsoseeB5 Flol FIFO levellow register0x0C bit5) B4 Fove FIFO overflowerror Too many byteswere writtentotheFIFO B3 Fb3 FIFO bytesfb[3] BitsB0:B3 indicatehow many bytesthatareloadedinFIFO wereB2 Fb2 FIFO bytesfb[2] notreadoutyet(displaysN – 1 number ofbytes).If8 bytesarein B1 Fb1 FIFO bytesfb[1] theFIFO,thisnumber is7 (alsosee register0x0C bit6). B0 Fb0 FIFO bytesfb[0]

6.1.5.2 TX Length Byte1 Register(0x1D)and TX Length Byte2 Register(0x1E)

Table6-24.TX Length Byte1 Register(0x1D) Function:Hightwo nibblesofcompleteintendedbytestobe transferredthroughFIFO DefaultSettings:Defaultissetto0x00 atPOR and EN = 0.ItisalsoautomaticallyresetatTX EOF. BitNo. BitName Function Description B7 Txl11 Number ofcompletebytebn[11] B6 Txl10 Number ofcompletebytebn[10] Highnibbleofcompleteintendedbytestobe transmitted B5 Txl9 Number ofcompletebytebn[9] B4 Txl8 Number ofcompletebytebn[8] B3 Txl7 Number ofcompletebytebn[7] B2 Txl6 Number ofcompletebytebn[6] Highnibbleofcompleteintendedbytestobe transmitted B1 Txl5 Number ofcompletebytebn[5] B0 Txl4 Number ofcompletebytebn[4] Table6-25.TX Length Byte2 Register(0x1E) Function:Low nibblesofcompletebytestobe transferredthroughFIFO.Informationabouta brokenbyteand number ofbitstobe transferredfromit. DefaultSettings:Defaultissetto0x00 atPOR and EN = 0.ItisalsoautomaticallyresetatTX EOF. BitNo. BitName Function Description B7 Txl3 Number ofcompletebytebn[3] B6 Txl2 Number ofcompletebytebn[2] Highnibbleofcompleteintendedbytestobe transmitted B5 Txl1 Number ofcompletebytebn[1] B4 Txl0 Number ofcompletebytebn[0] B3 Bb2 Brokenbytenumber ofbitsbb[2] Number ofbitsinthelastbrokenbytetobe transmitted.B2 Bb1 Brokenbytenumber ofbitsbb[1] Itistakenintoaccountonlywhen brokenbyteflagisset.B1 Bb0 Brokenbytenumber ofbitsbb[0] B0 Bbf Brokenbyteflag B0 = 1 indicatesthatlastbyteisnotcomplete8 bitswide. Copyright© 2011–2013,Texas InstrumentsIncorporated RegisterDescription 55 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

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7 System Design

7.1 Layout Considerations

Keep alldecouplingcapacitorsas close to the IC as possible,with the high-frequencydecoupling capacitors(10nF)closerthanthelow-frequencydecouplingcapacitors(2.2µF). Placegroundviasas closeas possibletothegroundsideofthecapacitorsand readerIC pinstominimize any possiblegroundloops. Itisnot recommend usingany inductorsizesbelow 0603 as the outputpower can be compromised.If smallersizedinductorsareabsolutelynecessary,thedesignermust confirmoutputperformance. Pay closeattentiontotherequiredloadcapacitanceoftheused crystaland adjustthetwo externalshunt capacitorsaccordingly.Followtherecommendationsofthecrystalmanufacturerforthosevalues. There shouldbe a common groundplaneforthedigitaland analogsections.The multiplegroundsections or"islands"shouldhave viasthattiethedifferentsectionsoftheplanestogether. Ensurethattheexposed thermalpad atthecenteroftheIC isproperlylaidout.Itshouldbe tiedtoground tohelpdissipateheatfromthepackage. Trace linelengthsshould be minimizedwhenever possible,particularlythe RF outputpath,crystal connections,and controllinesfromthereadertothemicroprocessor.ProperplacementoftheTRF7963A, microprocessor,crystal,and RF connection/connectorhelpfacilitatethis. Avoidcrossingofdigitallinesunder RF signallines.Also,avoidcrossingofdigitallineswithotherdigital lineswhenever possible.Ifthe crossingsare unavoidable,90° crossingsshouldbe used to minimize couplingofthelines. Depending on the productiontestplan,the designershouldconsiderpossibleimplementationsof test pads and/ortestviasforuse duringtesting.The necessarypads/viasshouldbe placedinaccordancewith theproposedtestplantohelpenableeasy accesstothosetestpoints. Ifthe system implementationiscomplex (forexample,ifthe RFID readermodule isa subsystem of a largersystem with other modules such as Bluetooth,WiFi, microprocessors,and clocks),special considerationsshouldbe takentoensurethatthereisno noisecouplingintothesupplylines.Ifneeded, specialfilteringor regulatorconsiderationsshould be used to minimizeor eliminatenoise in these systems. For more information/detailson layoutconsiderations,see theTRF796x HF-RFID Reader LayoutDesign Guide (SLOA139 ).

7.2 Impedance Matching TX_Out (Pin5)to50 Ω

The outputimpedance oftheTRF7963A when operatedatfullpower outsettingisnominally4 + j0(4Ω real).Thisimpedance must be matched to a resonantcircuitand TI recommends matchingcircuitfrom 4 Ω to50 Ω,as commerciallyavailabletestequipment(forexample,spectrumanalyzers,power meters, and network analyzers)are 50-Ω systems.See Figure7-1 and Figure7-2 foran impedance match referencecircuit.Thissectionexplainshow thevalueswere calculated. Startingwiththe4-Ω source,Figure7-1and Figure7-2shows theprocessofgoingfrom4 Ω to50 Ω by showing itrepresentedon a Smith Chartsimulator(availablefrom http://www.fritz.dellsperger.net/).The elementsaregroupedtogetherwhere appropriate.

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www.ti.com SLOS758C –DECEMBER 2011–REVISED JANUARY 2013 Figure7-1.Impedance Matching Circuit ThisyieldsthefollowingSmithChartSimulation: Figure7-2.Impedance Matching Smith Chart Resultingpower outcan be measured witha power meter,spectrumanalyzerwithpower meterfunction, orotherequipmentcapableofmaking a "hot"measurement.Take caretoobservemaximum power input levelson testequipmentand use attenuatorswhenever availableto avoidany possibilityof damage to expensiveequipment.Expected outputpower levelsunder variousoperatingconditionsare shown in Table5-3.

7.3 Reader Antenna Design Guidelines

ForHF antennadesignconsiderationsusingtheTRF7963A, see thefollowingdocumentation: AntennaMatchingfortheTRF7960 RFID Reader (SLOA135 ) TRF7960TB HF RFID Reader Module User'sGuide,withantennadetailsatend ofmanual (SLOU297 ) Copyright© 2011–2013,Texas InstrumentsIncorporated System Design 57 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

SLOS758C –DECEMBER 2011–REVISED JANUARY 2013 www.ti.com RevisionHistory NOTE: Page numbers forpreviousrevisionsmay differfrompage numbers inthecurrentversion. Revision Description SLOS758 ProductionData release SLOS758A Section3.2,CorrectedPower RatingforTA ≤ 25°C. SLOS758B Section3.1,CorrectedTSTG value. Section3.2,Correctedtypoon θJA. SLOS758C Section3.4,Added MIN and MAX testconditions.

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www.ti.com 27-Jul-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TRF7963ARHBR ACTIVE VQFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TRF 7963A TRF7963ARHBT ACTIVE VQFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TRF 7963A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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