TRF6903_08 TI1 | Alldatasheet
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Technical content
/C0084/C0082/C0070/C0054/C0057/C0048/C0051 /C0083/C0073/C0078/C0071/C0076/C0069/C0262/C0067/C0072/C0073/C0080 /C0077/C0085/C0076/C0084/C0073/C0066/C0065/C0078/C0068 /C0082/C0070 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 SWRS022D − MARCH 2004 − REVISED JUNE 2005 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Single-Chip RF Transceiver for 315-MHz, 433-MHz, 868-MHz, and 915-MHz Industrial, Scientific, and Medical (ISM) Bands /C00682.2-V to 3.6-V Operation /C0068Low Power Consumption /C0068FSK/OOK Operation /C0068Integer-N Synthesizer With Fully Integrated Voltage Controlled Oscillator (VCO) /C0068On-Chip Reference Oscillator and Phase-Locked Loop (PLL) /C0068Power Amplifier With 8-dBm Typical Output Power /C0068Programmable Brownout Detector /C0068Clock Recovery With Integrated Data Bit Synchronizer and Baud Rate Selection /C0068Linear Receive Strength Signal Indicator (RSSI) /C0068Flexible 3-Wire Serial Interface /C0068Minimal Number of External Components Required /C006848-Pin Low-Profile Plastic Quad Flat Package (PQFP) /C0068Programmable XTAL Trimming /C0068Lock Detect Indicator /C0068Programmable Training Sequence Recognition /C0068Pin Compatible to the TRF6901 LEARN/HOLD IF_IN1, IF_IN2 CER_DIS LPF_IN MIX_OUT 43, 44 31301513 CP_OUT VCO_TUNE LNA_IN1 DET_OUT PA_OUT RX_DATA DCLK XTAL XTAL_SW RSSI_OUT RX_FLAG CLOCK DATA STROBE STDBY MODE LOCK_DETECT TX_DATA SLC_CAP LPF_OUT LNA_IN2 TRF6903
10.7 MHz Ceramic
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the gates. Copyright 2005, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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RSSI_OUT DEM_VCC LEARN/HOLD DEM_GND 47 46 45 44 4348 42 MIX_VCC MIX_OUT MIX_GND DET_OUT IF_IN1 LOCK_DETECT RX_FLAG NC CP_OUT DVDD CLOCK STROBE DATA MODE 40 39 3841 21 22 23 24 LPF_IN IF_IN2 GND CP_GND VCO_TUNE CP_VCC PQFP PACKAGE (TOP VIEW) LNA_IN1 LNA_IN2 LNA_VCC PA_OUT PA_GND1 PA_VCC PA_GND2 VCO_GND1 VCO_VCC VCO_VCC2 VCO_BYPASS VCO_GND2 LPF_OUT CER_DIS SLC_CAP RX_DATA TX_DATA XTAL_SW XTAL XTAL_VCC DGND DCLK STDBY NC
description
The TRF6903 single-chip solution is an integrated circuit intended for use as a low-cost multiband FSK or OOK transceiver to establish a frequency-programmable, half-duplex, bidirectional RF link. The multichannel transceiver is intended for digital (FSK, OOK) modulated applications in the North American and European 315-MHz, 433-MHz, 868-MHz, and 915-MHz ISM bands. The single-chip transceiver operates down to 2.2 V and is designed for low power consumption. The synthesizer has a typical channel spacing of better than 200 kHz and features a fully-integrated VCO. Only the PLL loop filter is external to the device. Two fully-programmable operation modes, Mode0 and Mode1, allow extremely fast switching between two preprogrammed settings (for example, receive (RX)/transmit (TX); TX_frequency_0/TX_frequency_1; RX_frequency_0/RX_frequency_1; …) without reprogramming the device. ISM band standards Europe has assigned an unlicensed frequency band of 868 MHz to 870 MHz. This band is specifically defined for short range devices with duty cycles from 0.1% to 100% in several subbands. The new European frequency band, due to the duty cycle assignment, allows a reliable RF link and makes many new applications possible. The North American unlicensed ISM band covers 902 MHz to 928 MHz (center frequency of 915 MHz), and is suitable for short range RF links.
a loop filter to provide a complete PLL with a typical frequency resolution of better than 200 kHz. necessary in most applications. amplifier for optimal output power. MSP430 and the MSP430 performs baseband operations in the software. feature reduces the need for extensive oversampling and data decision in the microcontroller during receive. Figure 1. System Block Diagram for Interfacing to the MSP430 Microcontroller
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PA_OUT Ceramic Discriminator Serial Interface LNA LOCK_DETECT CLOCK DATA STROBE PA Band-gap /N Prescaler /A- Counter Loop Filter Limiter Quadrature Demodulator RX_DATA LPF Amplifier Data Slicer 10.7-MHz Ceramic or Discrete IF FIlter Brownout MODE /Div. CTRL RSSI RSSI_OUT Output Divider PFD CPs /Ref /B- RF IN Counter Lock Detector VCO DET_OUT 45 LNA_IN1, LNA_IN2 1, 2 30 31 CER_DIS LPF_IN LPF_OUT IF_IN1,2 MIX_OUT XTAL_SW LEARN / HOLD SLC_CAP XTAL 47 44, 43 35 37 36 39 34
15 CP_OUT13VCO_TUNE
2...255 Mixer 1, 2, 3 Detect Bit Synchronizer Data Clock DCLK27 TX_DATA and RX_FLAG23 STDBY OOK Switch XTAL Switch Terminal Functions TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION CER_DIS 35 Connect to external ceramic discriminator CLOCK 18 I Serial interface clock signal input CP_GND 14 Charge pump ground CP_OUT 15 O Charge pump output CP_VCC 16 Charge pump supply voltage DATA 20 I Serial interface data signal input
/C0084/C0082/C0070/C0054/C0057/C0048/C0051 /C0083/C0073/C0078/C0071/C0076/C0069/C0262/C0067/C0072/C0073/C0080 /C0077/C0085/C0076/C0084/C0073/C0066/C0065/C0078/C0068 /C0082/C0070 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 SWRS022D − MARCH 2004 − REVISED JUNE 2005 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION DCLK 27 O Data clock output DEM_GND 38 Demodulator ground DEM_VCC 40 Demodulator supply voltage DET_OUT 45 O Brownout detector output; active high DGND 28 Digital ground DVDD 17 Digital power supply GND 42 Substrate ground IF_IN1 44 I Limiter amplifier noninverting input IF_IN2 43 I Limiter amplifier inverting input LEARN/HOLD 39 I Data slicer switch. Controls data slicer reference level LNA_IN1 1 I LNA noninverting input LNA_IN2 2 I LNA inverting input LNA_VCC 3 LNA power supply LOCK_DETECT 22 O PLL lock detect signal, active high LPF_IN 37 I Low-pass filter amplifier input LPF_OUT 36 O Low-pass filter amplifier output MIX_GND 46 Mixer ground MIX_OUT 47 O Mixer output MIX_VCC 48 Mixer supply voltage MODE 21 I Mode select input NC 24, 25 No connect PA_GND1 5 Power amplifier ground PA_GND2 7 Power amplifier ground PA_OUT 4 O Power amplifier output PA_VCC 6 Power amplifier supply voltage RSSI_OUT 41 O RSSI output signal RX_DATA 33 O Demodulated digital (FSK or OOK) RX data RX_FLAG 23 O Receive data flag SLC_CAP 34 I/O External capacitor for data slicer STDBY 26 I Standby input signal; active low STROBE 19 I Serial interface strobe signal TX_DATA 32 I Buffered TX data input VCO_BYPASS 11 I VCO bypass; connect to ground through a 100-pF capacitor VCO_GND1 8 VCO ground VCO_GND2 12 VCO ground VCO_TUNE 13 I Tuning voltage for the integrated VCO VCO_VCC 9 VCO supply voltage VCO_VCC2 10 VCO core supply voltage XTAL 30 I/O Connection to an external crystal reference XTAL_SW 31 I Connecting to external capacitor, which sets the frequency deviation of the transmitted signal XTAL_VCC 29 Oscillator supply voltage
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absolute maximum ratings over operating free-air temperature (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Analog supply voltage 2.2 3.6 V Digital supply voltage 2.2 3.6 V Operating free-air temperature −40 85 °C dc electrical characteristics, VCC = 2.7 V, TA = 25°C supply current PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Standby current STDBY low 0.6 4 µA 315-MHz band 12 15 RX current, receive chain inactive. Bit synchronizer and data clock433-MHz band 11 14 mARX current, receive chain inactive. Bit synchronizer and data clock inactive. PLL, VCO, dividers, and reference active 868-MHz band 10 12 mA 915-MHz band 10 12 315-MHz band 20 26 RX current, receive chain active. PLL, VCO, dividers, and reference433-MHz band 19 25 mARX current, receive chain active. PLL, VCO, dividers, and reference active. Bit synchronizer and data clock inactive 868-MHz band 18 23 mA 915-MHz band 18 23 315-MHz band 20 26 RX current, receive chain active. PLL, VCO, dividers, and reference433-MHz band 19 25 mARX current, receive chain active. PLL, VCO, dividers, and reference active. Bit synchronizer and data clock active 868-MHz band 18 23 mA 915-MHz band 18 23
/C0084/C0082/C0070/C0054/C0057/C0048/C0051 /C0083/C0073/C0078/C0071/C0076/C0069/C0262/C0067/C0072/C0073/C0080 /C0077/C0085/C0076/C0084/C0073/C0066/C0065/C0078/C0068 /C0082/C0070 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 SWRS022D − MARCH 2004 − REVISED JUNE 2005 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 dc electrical characteristics, VCC = 2.7 V, TA = 25°C (continued) supply current (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 315-MHz band 12 15 TX current, PA disabled. PLL, VCO, dividers, and reference active 433-MHz band 11 14 mATX current, PA disabled. PLL, VCO, dividers, and reference active868-MHz band 10 12 mA 915-MHz band 10 12 0-dB attenuation 315-MHz band 37 43 10-dB attenuation 315-MHz band 30 20-dB attenuation 315-MHz band 29 0-dB attenuation 433-MHz band 36 42 10-dB attenuation 433-MHz band 29 TX current‡, PA enabled. PLL, VCO, dividers,20-dB attenuation 433-MHz band 28 mATX current‡, PA enabled. PLL, VCO, dividers, reference, and data clock active 0-dB attenuation 868-MHz band 35 40 mAreference, and data clock active 10-dB attenuation 868-MHz band 28 20-dB attenuation 868-MHz band 27 0-dB attenuation 915-MHz band 35 40 10-dB attenuation 915-MHz band 28 20-dB attenuation 915-MHz band 27 ‡ The TX current consumption is dependent upon the external PA matching circuit. The matching network is normally designed to achieve the highest output power at the 0-dB attenuation setting. Changing the external matching components to optimize the output power for other attenuation settings alters the typical current consumption from the typical values noted. digital interface PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH High-level input voltage VDD −0.4 VDD V VIL Low-level input voltage 0 0.4 V VOH High-level output voltage IOH = 0.5 mA VDD −0.4 V VOL Low-level output voltage IOL = 0.5 mA 0.4 V Digital input leakage current <0.01 µA ac electrical characteristics, VCC = 2.7 V, TA = 25°C receiver (LNA, mixer, limiter, demod, LPF amplifier, data slicer, VCO, and PLL) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RX wake-up time 1 ms BER, FSK
315 MHz, 433 MHz,
868 MHz, 915 MHz,
IF = 10.7 MHz, BW = 280 kHz FSK deviation: ±32 kHz Bit rate: 19.2 kbit/s Manchester† −103 < PRFIN (dBm) < −30 10−3 BER, OOK IF = 10.7 MHz, BW = 280 kHz ON-OFF ratio: 50 dB Bit rate: 9.6 kbit/s Manchester‡ −103 < PRFIN (dBm) < −30 10−3 † 19.2 kbit/s Manchester is equivalent to 38.4 kbit/s NRZ. ‡ 9.6 kbit/s Manchester is equivalent to 19.2 kbit/s NRZ.
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ac electrical characteristics, VCC = 2.7 V, TA = 25°C LNA/mixer, 304−316 MHz PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Frequency range 304 315 316 dB Conversion gain 21 dB SSB noise figure Includes external matching network 6.5 dB Input 1-dB compression point −31 dBm Input IP3 −21 dBm LNA/mixer, 430−450 MHz PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Frequency range 430 433 450 MHz Conversion gain 21 dB SSB noise figure Includes external matching network 6.5 dB Input 1-dB compression point −31 dBm Input IP3 −21 dBm LNA/mixer, 868−870 MHz PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Frequency range 868 869 870 MHz Conversion gain 19 dB SSB noise figure Includes external matching network 6.5 dB Input 1-dB compression point −31 dBm Input IP3 −20 dBm LNA/mixer, 902−928 MHz PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Frequency range 902 915 928 MHz Conversion gain 18 dB SSB noise figure Includes external matching network 6.5 dB Input 1-dB compression point −31 dBm Input IP3 −19 dBm IF/limiter amplifier PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Frequency 10.7 MHz Voltage gain 86 dB Noise figure IF frequency = 10.7 MHz 4 dB VCO/output divider PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Frequency range: 315-MHz band Low-side injection, A<1:0> = 11 304 315 316 MHz Frequency range: 433-MHz band High-side injection, A<1:0> = 10430 433 450 MHz Frequency range: 868-MHz band High-side injection, A<1:0> = 01868 869 870 MHz Frequency range: 915-MHz band Low-side injection, A<1:0> = 01 902 915 928 MHz Closed loop phase noise Frequency offset = 50 kHz −77 dBc/HzClosed loop phase noise Frequency offset = 200 kHz −90 dBc/Hz Tuning voltage 0.1 VCC at terminal 10 V
/C0084/C0082/C0070/C0054/C0057/C0048/C0051 /C0083/C0073/C0078/C0071/C0076/C0069/C0262/C0067/C0072/C0073/C0080 /C0077/C0085/C0076/C0084/C0073/C0066/C0065/C0078/C0068 /C0082/C0070 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 SWRS022D − MARCH 2004 − REVISED JUNE 2005 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ac electrical characteristics, VCC = 2.7 V, TA = 25°C (continued) RSSI PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Dynamic range 70 dB Rise time R L = 100 kΩ, C L = 10 pF 2 4 µs Slope 20 mV/dB RSSI output current R L = 100 kΩ, CL = 10 pF 30 µA impedances and loads PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LNA_IN See Figure 4 MIX_OUT /C0123 1400 Ω IF_IN/C0123 Differential 2600 Ω PA_OUT See Figure 10 † Does not include external matching network. transmitter (XTAL, PLL, VCO, and PA), 315-MHz band PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TX frequency range A<1:0> = 11 304 315 316 MHz 0-dB attenuation 8 10-dB attenuation −2 Output power† 20-dB attenuation −12 dBmOutput power† Disabled, B<3> = 0 −80 dBm Off‡ −80 Second harmonic −25 dBc Third harmonic −30 dBc Frequency deviation§ FSK /C000632 kHz Power ON-OFF ratio OOK, 0-dB mode 75 dB Maximum data rate (NRZ) FSK 64 kbit/sMaximum data rate (NRZ) OOK 32 kbit/s † Matched to 50 Ω using external matching network. ‡ Not selectable with PA attenuation bits A<7:6>, B<7:6>, or with B<3>. Measured while the TRF6903 device is in RX mode. § Dependent upon external circuitry.
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ac electrical characteristics, VCC = 2.7 V, TA = 25°C (continued) transmitter (XTAL, PLL, VCO, and PA), 433-MHz band PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TX frequency range A<1:0> = 10 430 433 450 MHz 0-dB attenuation 8 10-dB attenuation −2 Output power† 20-dB attenuation −12 dBmOutput power† Disabled, B<3> = 0 −80 dBm Off‡ −80 Second harmonic −25 dBc Third harmonic −30 dBc Frequency deviation§ FSK /C000632 kHz Power ON-OFF ratio OOK, 0-dB mode 75 dB Maximum data rate (NRZ) FSK 64 kbit/sMaximum data rate (NRZ) OOK 32 kbit/s † Matched to 50 Ω using external matching network. ‡ Not selectable with PA attenuation bits A<7:6>, B<7:6>, or with B<3>. Measured while the TRF6903 device is in RX mode. § Dependent upon external circuitry. transmitter (XTAL, PLL, VCO, and PA), 868-MHz band PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TX frequency range A<1:0> = 11 868 869 870 MHz 0-dB attenuation 8 10-dB attenuation −2 Output power† 20-dB attenuation −12 dBmOutput power† Disabled, B<3> = 0 −80 dBm Off‡ −80 Second harmonic −25 dBc Third harmonic −30 dBc Frequency deviation§ FSK /C000632 kHz Power ON-OFF ratio OOK, 0-dB mode 75 dB Maximum data rate (NRZ) FSK 64 kbit/sMaximum data rate (NRZ) OOK 32 kbit/s † Matched to 50 Ω using external matching network. ‡ Not selectable with PA attenuation bits A<7:6>, B<7:6>, or with B<3>. Measured while the TRF6903 device is in RX mode. § Dependent upon external circuitry.
/C0084/C0082/C0070/C0054/C0057/C0048/C0051 /C0083/C0073/C0078/C0071/C0076/C0069/C0262/C0067/C0072/C0073/C0080 /C0077/C0085/C0076/C0084/C0073/C0066/C0065/C0078/C0068 /C0082/C0070 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 SWRS022D − MARCH 2004 − REVISED JUNE 2005 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ac electrical characteristics, VCC = 2.7 V, TA = 25°C (continued) transmitter (XTAL, PLL, VCO, and PA), 915-MHz band PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TX frequency range A<1:0> = 11 902 915 928 MHz 0-dB attenuation 8 10-dB attenuation −2 Output power† 20-dB attenuation −12 dBmOutput power† Disabled, B<3> = 0 −80 dBm Off‡ −80 Second harmonic −25 dBc Third harmonic −30 dBc Frequency deviation§ FSK ±32 kHz Power ON-OFF ratio OOK, 0-dB mode 75 dB Maximum data rate (NRZ) FSK 64 kbit/sMaximum data rate (NRZ) OOK 32 kbit/s † Matched to 50 Ω using external matching network. ‡ Not selectable with PA attenuation bits A<7:6>, B<7:6>, or with B<3>. Measured while the TRF6903 device is in RX mode. § Dependent upon external circuitry. XTAL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Frequency range 9.5 20 MHz brownout detector PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Voltage threshold, Vdet Set by B<2:1> 2.2 2.8 V Voltage steps (∆V) 200 mV Number of steps 4 Output level Connected to typical input port of microcontrollerCMOS
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Note: Most significant bit (MSB) clocked in first to the synthesizer. Figure 2. Timing Data for Serial Interface
NOTE: RX_DATA is latched at the falling edge of DCLK. NOTE: TX_DATA is latched at the rising edge of DCLK. Figure 3. Timing Data for DCLK, TX_DATA, RX_FLAG, and RX_DATA
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than half the RXDATA pulse width to prevent bit errors. can then latch TXDATA on the rising edge of DCLK. For more details, see the data clock section. noise figure for the LNA/mixer is listed in the specifications. impedance of the mixer (1.4 kΩ) to the input impedance of the IF filter (typically 330 Ω). Figure 4. Typical LNA Input Impedance (S11) at Device Terminals LNA_IN1,2 at the RX_DATA terminal according to the RXM field.
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Table 1. Various Post-Detection Amplifier/Low-Pass Filter NOTE: For OOK operation, it is recommended that R2 be set to 27 kΩ and C2 is not placed. continuously in the learn mode and no training sequence is necessary before the transmission of a data string. transmission); a learning sequence before each data transmission is recommended. Where the data rate in Hz is the fundamental frequency (in Hz) of the base band waveform. Figure 7. Data Slicer and Bit Synchronizer of data whose baud rate is nonstandard.
corresponding data clock is output at terminal 27, DCLK. frequencies (MHz) and the respective settings of D1, D2, and D3. Table 2. Common Bit Rates, Corresponding Crystal Frequencies, and Values of D1, D2, and D3
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Table 2. Common Bit Rates, Corresponding Crystal Frequencies, and Values of There are several receive modes, from raw slicer output to clock recovery and training sequence recognition. the receive mode as indicated in Table 3. These modes are described in more detail below. Table 3. Clock Recovery and Receive Data Modes Selected by RXM
00 Raw data Data direct from data
01 Deglitch Deglitched data Active; clock
10 Clock recovery Deglitched data;
11 Self train Deglitched data;
RX_DATA terminal a few gate delays after the rising edge of DCLK. The RX_FLAG terminal is held low. In Clock Recovery mode, the edges of the deglitched data are used to synchronize a bit-rate clock to the data. were ∆B is the error between the transmit bit rate and the receiver bit-rate clock in ppm. observed since the last reset, then DCLK is held low until an edge is seen.
/C0084/C0082/C0070/C0054/C0057/C0048/C0051 /C0083/C0073/C0078/C0071/C0076/C0069/C0262/C0067/C0072/C0073/C0080 /C0077/C0085/C0076/C0084/C0073/C0066/C0065/C0078/C0068 /C0082/C0070 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 SWRS022D − MARCH 2004 − REVISED JUNE 2005 19POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 data clock (continued) In Self Train mode, the TRF6903 receiver not only performs clock recovery, but also looks for the end of a training sequence. The TWO, E<12>, field determines the pattern of the training sequence. If TWO is low, the training sequence is assumed to be alternating ones and zeros; if TWO is high, the training sequence is assumed to be alternating pairs of ones and zeros. RX_DATA and DCLK output are the same as in Clock Recovery mode. However, if a minimum number of training bits have been observed, then the RX_FLAG terminal is asserted high for one clock period (after which it returns low) at the first bit that is not part of the training sequence. The timing of RX_FLAG is a few gate delays after the rising edge of DCLK. The minimum number of training bits is four times the unsigned binary value of TCOUNT, E<11:7>, plus two if TWO = 0 or plus three if TWO = 1, according to the equation: TB min = (4 x TCOUNT) + TWO + 2 The clock recovery and training sequence recognition circuits are all designed to reset/clear internally with no user action required. When active, DCLK is synchronized to the received data. The rising edge of the data clock is intended to be located at the middle of the received recovered data bit, thus enhancing the synchronization ability of the microcontroller and reducing the need for extensive signal processing in the microcontroller. main divider The main divider is composed of a 5-bit A-counter and a 9-bit B-counter and a prescaler. The A-counter controls the divider ratio of the prescaler, which divides the VCO signal by either 33 or 32. The prescaler divides by 33 until the A-counter reaches its terminal count and then divides by 32 until the B-counter reaches terminal count, whereupon both counters reset and the cycle repeats. The total divide-by-N operation is related to the 32/33 prescaler by: N TOTAL = 33 x A + 32 x (B – A) where 0 ≤ A ≤ 31 and 31 ≤ B ≤ 511 or, NTOTAL = A + 32B Thus, the N-divider has a range of 992 ≤ NTOTAL ≤ 16383 PLL The phase-locked loop is the radio frequency synthesizer for the TRF6903. It is used to generate the transmit signal and as the local oscillator for the receive mixer. The signal (FX) from a reference crystal oscillator (XO) is divided by an integer factor R down to FR . The minimum frequency resolution, and thus, the minimum channel spacing, is FR . FR = FX ÷ R where 1 ≤ R ≤ 256 The phase-locked loop is an integer-N design. The voltage-controlled oscillator (VCO) signal is divided by an integer factor N to get a frequency at the phase detector input. FPD = FVCO ÷ N The phase detector compares the divided VCO signal to the divided crystal frequency and implements an error signal from two charge pumps. The error signal corrects the VCO output to the desired frequency. As is in any integer-N PLLs, the VCO output has spurs at integer multiples of the reference frequency (nFR ). In applications requiring contiguous frequency channels, the reference frequency is often chosen to be equal to the channel spacing, thus, channel spacing = F R = FX ÷ R. When the PLL is locked, the LOCK_DETECT terminal is high.
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
is toggled. The change in load capacitance pulls the crystal off-frequency by the total frequency deviation. can be used to invert the data at terminal 33, RX_DATA, when high-side injection is being used. to keep the XTAL switch closed. In this manner, the actual LO frequency injected into the mixer is ƒout1 = ƒLO . If D<19> is set low, the the receiver LO would be offset, resulting in poor receiver sensitivity.
15 External
Figure 8. TRF6903 PLL and Output Divider
three steps: 250 µA, 500 µA, and 1000 µA. Figure 9. Third-Order Loop Filter and Transfer Function Table 4. Loop Filter Component Values For Various Data Rates at a Reference Frequency of 409.6 kHz, inductors. The open-loop VCO gain is approximately 100 MHz/V. these blocks are powered down.
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
to the transmit data incident at terminal 32. Figure 10. Typical PA Output Impedance (S22) at Device Terminal PA_OUT threshold is set with the B word. Four different thresholds are available. frequency and tune the demodulator. varies from 15 bits to 22 bits. Normal (write) operation of the serial interface is to clock in 24 bits through the CLOCK and DATA terminals. value is decoded and written into the appropriate data register on the rising edge of STROBE.
/C0084/C0082/C0070/C0054/C0057/C0048/C0051 /C0083/C0073/C0078/C0071/C0076/C0069/C0262/C0067/C0072/C0073/C0080 /C0077/C0085/C0076/C0084/C0073/C0066/C0065/C0078/C0068 /C0082/C0070 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 SWRS022D − MARCH 2004 − REVISED JUNE 2005 23POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION register description /C0050/C0051/C0050/C0050/C0050/C0049/C0050/C0048/C0049/C0057/C0049/C0056/C0049/C0055/C0049/C0054/C0049/C0053/C0049/C0052/C0049/C0051/C0049/C0050/C0049/C0049/C0049/C0048/C0057/C0056/C0055/C0054 /C0053 /C0052 /C0051 /C0050/C0049 /C0048 /C0087/C0111/C0114/C0100/C0065/C0100/C0100/C0114/C0101/C0115/C0115 /C0065/C0100/C0100/C0114/C0101/C0115/C0115 /C0065/C0048/C0048 /C0077/C0097/C0105/C0110 /C0065/C0262/C0068/C0105/C0118/C0105/C0100/C0101/C0114 /C0067/C0111/C0101/C0102/C0102/C0105/C0099/C0105/C0101/C0110/C0116 /C0040/C0077/C0111/C0100/C0101 /C0048/C0041 /C0077/C0097/C0105/C0110 /C0066/C0262/C0068/C0105/C0118/C0105/C0100/C0101/C0114 /C0067/C0111/C0101/C0102/C0102/C0105/C0099/C0105/C0101/C0110/C0116 /C0040/C0077/C0111/C0100/C0101 /C0048/C0041 /C0080/C0065/C0048/C0084/C0088/C0047 /C0082/C0088/C0048/C0080/C0073/C0067/C0080 /C0065/C0099/C0099/C0046/C0066/C0078/C0068 /C0066 /C0048/C0049 /C0077/C0097/C0105/C0110 /C0065/C0262/C0068/C0105/C0118/C0105/C0100/C0101/C0114 /C0067/C0111/C0101/C0102/C0102/C0105/C0099/C0105/C0101/C0110/C0116 /C0040/C0077/C0111/C0100/C0101 /C0049/C0041 /C0077/C0097/C0105/C0110 /C0066/C0262/C0068/C0105/C0118/C0105/C0100/C0101/C0114 /C0067/C0111/C0101/C0102/C0102/C0105/C0099/C0105/C0101/C0110/C0116 /C0040/C0077/C0111/C0100/C0101 /C0049/C0041 /C0080/C0065/C0049/C0084/C0088/C0047 /C0082/C0088/C0049 /C0070/C0083/C0075/C0047 /C0079/C0079/C0075/C0080/C0065/C0082/C0088/C0069/C0068/C0068/C0101/C0116/C0101/C0099/C0116/C0111/C0114 /C0084/C0104/C0114/C0101/C0115/C0104/C0111/C0108/C0100 /C0068/C0101/C0116/C0046 /C0069/C0110/C0097/C0098/C0108/C0101 /C0067 /C0049/C0048 /C0082/C0101/C0102/C0101/C0114/C0101/C0110/C0099/C0101 /C0068/C0105/C0118/C0105/C0100/C0101/C0114 /C0067/C0111/C0101/C0102/C0102/C0105/C0099/C0105/C0101/C0110/C0116/C0082/C0101/C0115/C0101/C0114/C0118/C0101/C0100/C0114 /C0114 /C0114 /C0114 /C0114/C0048 /C0048 /C0069 /C0049/C0048 /C0066/C0082/C0065/C0066/C0082/C0066/C0066/C0082/C0067/C0082/C0088/C0077/C0084/C0088/C0077/C0084/C0087/C0079 /C0084/C0067/C0079/C0085/C0078/C0084/C0048 /C0048 /C0114 /C0114 /C0114/C0048 /C0049 /C0068 /C0049/C0049/C0114/C0114/C0082/C0088/C0083/C0088/C0084/C0065/C0076/C0095/C0084/C0117/C0110/C0101/C0080/C0070/C0068 /C0114/C0101/C0115/C0101/C0116/C0068/C0101/C0109/C0095/C0084/C0117/C0110/C0101/C0079/C0079/C0075/C0088/C0083/C0114/C0114/C0114/C0114 /C0114 /C0114 /C0114 /C0114 /C0114/C0114 /C0048 NOTE: r = reserved. All reserved bits should be set low (0) during normal operation. NOTE: All bits indicated as 1 should be set high (1) during normal operation. NOTE: All bits indicated as 0 should be set low (0) during normal operation. ADDRESS LOCATION NO. OF BITS DESCRIPTION DEFAULT VALUE 00xx 21:17 5 Main A divider coefficient (Mode 0) 00000 00xx 16:8 9 Main B divider coefficient (Mode 0) 001110000 00xx 7:6 2 Controls the PA attenuation (Mode 0) 10 00xx 5 1 Enables transmit/receive path (Mode 0) 0 00xx 4 1 Receive data polarity invert bit 0 00xx 3:2 2 Controls charge pump peak current 00 00xx 1:0 2 Output divider coefficient; band select 10 01xx 21:17 5 Main A divider coefficient (Mode 1) 00000 01xx 16:8 9 Main B divider coefficient (Mode 1) 001110000 01xx 7:6 2 Controls the PA attenuation (Mode 1) 10 01xx 5 1 Enables transmit/receive path (Mode 1) 0 01xx 4 1 Controls modulation scheme (FSK or OOK) 0 01xx 3 1 Enables or disables the power amplifier while in transmit mode or the receive chain while in receive mode 01xx 2:1 2 Sets threshold for the brownout detector 00 01xx 0 1 Enables brownout detector 0 1000 21:14 8 Reference divider coefficient 01000000 1001 21:20 2 Bit-rate divider D1 11 1001 19:17 3 Bit-rate divider D2 010 1001 16 1 Bit-rate divider D3 0 1001 15:14 2 Receive mode select 00 1001 13 1 Transmit capture mode select 0 1001 12 1 RX training sequence pattern select 0 1001 11 : 7 5 Determines the minimum number of training bits 00100 11x0 19 1 Controls the position of the XTAL switch during FSK reception0 11x0 18:16 3 Tunes the XTAL frequency by using an internal capacitor bank000 11x0 15 1 PFD reset 1 11x0 14:12 3 Tunes the resonant frequency of the external demodulation tank circuit 000 11x0 11 1 Controls the position of the XTAL switch during OOK operation0 NOTE: x = don’t care
/C0084/C0082/C0070/C0054/C0057/C0048/C0051 /C0083/C0073/C0078/C0071/C0076/C0069/C0262/C0067/C0072/C0073/C0080 /C0077/C0085/C0076/C0084/C0073/C0066/C0065/C0078/C0068 /C0082/C0070 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 SWRS022D − MARCH 2004 − REVISED JUNE 2005
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
At power on/startup, all of the TRF6903 register contents are as per the default values. Address 00XX (A-Word): Word A is a 22-bit data register comprising seven fields. The main A-divider coefficient (mode 0), A<21:17>, is the 5-bit divider ratio of the A counter when the MODE terminal is low. The main B-divider coefficient (mode 0), A<16:8>, is the 9-bit value of the B counter when the MODE terminal is low. A <21:17> and A <16:8> are unsigned binary values. PA0, A<7:6>, is the 2-bit PA attenuation setting when the MODE terminal is low. TX/RX0, A<5>, is the TX/RX switch when the MODE terminal is low. PI, A<4>, is the data polarity invert bit. When high, this bit causes the data slicer output to be inverted. CP Acc., A<3:2>, sets the charge pump current. BND, A<1:0>, sets the output divider, which in turn determines the band of operation. Terminal 21 (MODE) selects bits A<21:5> if low, or B<21:5> if high. Main divider A<21:17>: 5-bit value for divider ratio of the A counter Main divider A<16:8>: 9-bit value for divider ratio of the B counter PA attenuation A<7:6>: 2 bits for setting the PA attenuation A<7:6> PA ATTENUATION 00 0 dB 01 10 dB 10 20 dB
11 Not defined
A<5>: 1-bit TX/RX mode select A<5> TX/RX MODE
0 RX mode
1 TX mode
A<4>: 1-bit data polarity invert bit A<4> RX DATA POLARITY
0 Noninverted
1 Inverted
A<3:2>: 2 bits for setting the charge pump current A<3:2> CP CURRENT 00 0.5 mA 01 1 mA 10 0.25 mA
/C0084/C0082/C0070/C0054/C0057/C0048/C0051 /C0083/C0073/C0078/C0071/C0076/C0069/C0262/C0067/C0072/C0073/C0080 /C0077/C0085/C0076/C0084/C0073/C0066/C0065/C0078/C0068 /C0082/C0070 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 SWRS022D − MARCH 2004 − REVISED JUNE 2005 25POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION A<1:0>: 2-bit value to set the output divider and thus select the band of operation. A<1:0> OUTPUT DIVIDER RATIO, P BAND OF OPERATION 00 3 315 MHz 01 2 433 MHz 10 1 868 MHz or 915 MHz 11 1 868 MHz or 915 MHz Address 01XX (B-Word): Word B is a 22-bit data register comprising eight fields. The main A-divider coefficient (mode 1), B<21:17>, is the 5-bit divider ratio of the A counter when the MODE terminal is high. The main B-divider coefficient (mode 1), B<16:8>, is the 9-bit value of the B counter when the MODE terminal is high. B<21:17> and B<16:8> are unsigned binary values. PA1, B<7:6>, is the 2-bit PA attenuation setting when the MODE terminal is high. TX/RX1, B<5>, is the TX/RX switch when the MODE terminal is high. FSK/OOK, B<4>, sets the modulation scheme for both TX and RX. Bit B<3> enables/disables the power amplifier while in transmit mode and enables/disables the receive chain while in receive mode. The detector threshold, B<2:1>, is the 2-bit setting for the threshold voltage of the brownout detector. Det. Enable, B<0>, is the brownout detector enable flag. Terminal 21 (MODE) selects bits A<21:5> if low, or B<21:5> if high. Main divider B<21:17>: 5-bit value for divider ratio of the A-counter Main divider B<16:8>: 9-bit value for divider ratio of the B-counter PA attenuation B<7:6>: 2 bits for setting the PA attenuation B<7:6> PA ATTENUATION 00 0 dB 01 10 dB 10 20 dB B<5>: 1-bit TX/RX mode select B<5> TX/RX MODE B<4> 1-bit modulation select B<4> TX/RX MODULATION
0 OOK
1 FSK
NOTE: During OOK reception, the OOK switch is closed. During FSK reception, the OOK switch is open.
/C0084/C0082/C0070/C0054/C0057/C0048/C0051 /C0083/C0073/C0078/C0071/C0076/C0069/C0262/C0067/C0072/C0073/C0080 /C0077/C0085/C0076/C0084/C0073/C0066/C0065/C0078/C0068 /C0082/C0070 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 SWRS022D − MARCH 2004 − REVISED JUNE 2005
26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
B<3>: 1-bit PA or receive chain enable/disable B<3> PA OR RECEIVE CHAIN ENABLE/DISABLE
0 Disabled
1 Enabled
B<2:1>: 2-bit value to set the threshold voltage for the brownout detector B<2:1> THRESHOLD VOLTAGE 00 2.2 V 01 2.4 V 10 2.6 V 11 2.8 V B<0>: 1 bit to enable brownout detector B<0> BROWNOUT DETECTOR
0 Off
Address 1000 (C-Word): Word C is a 20-bit data register comprising four fields. The reference divider coefficient, C<21:14>, is the 8-bit divider ratio of the reference divider. The allowable reference divider range is 2 (C <21:14> = 00000010) through 255 (C <21:14> = 11111111). Bits C<13> through C<2> are reserved and should be set to 0. Address 1001 (E-Word): Word E is a 20-bit data register comprising eight fields. The bit rate or bit frequency, used by the clock recovery receive modes and the transmit synchronous mode is controlled by the BRA, E<21:20>, BRB, E<19:17>, and BRC, E<16>, fields. These three fields control a sequence of dividers, D1 through D3, that divide the reference (crystal) frequency, F
/C0084/C0082/C0070/C0054/C0057/C0048/C0051 /C0083/C0073/C0078/C0071/C0076/C0069/C0262/C0067/C0072/C0073/C0080 /C0077/C0085/C0076/C0084/C0073/C0066/C0065/C0078/C0068 /C0082/C0070 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 SWRS022D − MARCH 2004 − REVISED JUNE 2005 27POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION E<21:20>: 2 bits to set D1 divider setting E<21:20> D1 00 1 01 5 10 6 11 8 E<19:17>: 3 bits to set D2 divider setting E<19:17> D2 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 E<16>: 1 bit to set D3 divider setting E<16> D3 0 16 1 15 RXM, E<15:14> controls the signals that appear at the RX_DATA and DCLK terminals. The definition of RXM is contained in Table 3. TXM, E<13>, sets the transmit capture mode. If TXM is low, the TX_DATA terminal controls the transmit function asynchronously. If TXM is high, the bit-rate clock is output at DCLK and the transmit data at the TX_DATA terminal is latched on the rising edge of DCLK, where DCLK is the bit-rate clock. TWO, E<12>, sets the receive training sequence pattern. If TWO is high, the expected training sequence is assumed to be alternating pairs of ones and zeroes. If TWO is low, the expected training sequence is assumed to be alternating ones and zeroes. TCOUNT, E>11:7>, determines the minimum number of training bits. The minimum number of training bits is four times the unsigned binary value of TCOUNT, plus two if TWO = 0 or plus three if TWO = 1. Bits E<6> through E<2> are reserved and should be set to 0. Address 11X0 (D-Word): Word D is a 21-bit data register comprising three fields. XTAL_Tune, D<18:16>, is used to fine tune the crystal frequency by using an internal capacitor bank. PFD reset, D<15>, selects the source of the PFD reset signal. Dem_Tune, D<14:12>, is a 3-bit value used to tune the demodulator time constant. Bit D<11> controls the position of the XTAL switch during OOK operation. D<19>: 1-bit value to control the position of the XTAL switch during FSK reception, when B<4>=1 and either A<5> or B<5> = 0. It is recommended to set this bit to 1 (XTAL switch closed). If D<19> is set to 0 (XTAL switch open), the LO frequency injected into the mixer is f outs = fLO + designed peak-peak deviation. This results in the down-converted IF signal shifting higher (high-side injection) or lower (low-side injection) from the IF center frequency (10.7 MHz) by an amount equal to the designed peak-peak frequency deviation.
/C0084/C0082/C0070/C0054/C0057/C0048/C0051 /C0083/C0073/C0078/C0071/C0076/C0069/C0262/C0067/C0072/C0073/C0080 /C0077/C0085/C0076/C0084/C0073/C0066/C0065/C0078/C0068 /C0082/C0070 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 SWRS022D − MARCH 2004 − REVISED JUNE 2005
28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D<19> XTAL SWITCH DURING FSK RECEPTION TERMINAL 31
0 Unconnected (open) High-Z
1 Connected (closed) Shorted to ground internally
D<18:16>: 3-bit value to fine-tune the XTAL frequency by using an internal capacitor bank. D<18:16> TYPICAL LOAD CAPACITANCE 000 13.23 pF 001 22.57 pF 010 17.9 pF 011 27.24 pF 100 15.56 pF 101 24.9 pF 110 20.23 pF 111 29.57 pF D<15>: 1-bit value to select the reset signal for the PFD D<15> RESET SIGNAL
0 Derived from XTAL
1 Derived from prescaler
NOTE: The default setting for D<15> is 1. D<14:12>: 3-bit value to tune the resonant frequency of the external demodulator tank circuit. It can be used to optimize the receiver performance. The recommended default setting is 110. D<11>: 1-bit value to control position of the XTAL switch during OOK operation, when B<4> = 0. D<11> XTAL SWITCH DURING OOK OPERATION TERMINAL 31 It is recommended that D<19> and D<11> be set to 0 during FSK reception and OOK operation. Bits D<21>, D<20>, and D<10> through D<1> are reserved and should be set to 0. operating modes Controlled with terminal 26, STDBY STDBY OPERATING MODE
0 Power down of all blocks—programming mode
1 Operational mode and programming mode
Controlled with terminal 21, MODE MODE OPERATING MODE
0 Enable A-word
1 Enable B-word
/C0084/C0082/C0070/C0054/C0057/C0048/C0051 /C0083/C0073/C0078/C0071/C0076/C0069/C0262/C0067/C0072/C0073/C0080 /C0077/C0085/C0076/C0084/C0073/C0066/C0065/C0078/C0068 /C0082/C0070 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 SWRS022D − MARCH 2004 − REVISED JUNE 2005 29POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION Controlled with terminal 39, LEARN/HOLD LEARN/HOLD OPERATING MODE
0 Selects data slicer decision level to HOLD
1 Selects data slicer decision level to LEARN
The transmit/receive mode is controlled by the TX/RX0, A<5>, TX/RX1, B<5>, and PARXED, B<3>, fields and the MODE and STDBY terminals. A<5> B<5> B<3> MODE STDBY OPERATING MODE X X X X 0 Off, programming mode; SPI enabled 0 X 0 0 1 Receive mode 0, RX chain disabled. Reference, PLL, VCO and dividers enabled 0 X 1 0 1 Receive mode 0, RX chain enabled. Reference, PLL, VCO and dividers enabled 1 X 0 0 1 Transmit mode 0, PA disabled. Reference, PLL, VCO and dividers enabled 1 X 1 0 1 Transmit mode 0, PA enabled. Reference, PLL, VCO and dividers enabled X 0 0 1 1 Receive mode 1, RX chain disabled. Reference, PLL, VCO and dividers enabled X 0 1 1 1 Receive mode 1, RX chain enabled. Reference, PLL, VCO and dividers enabled X 1 0 1 1 Transmit mode 1, PA disabled. Reference, PLL, VCO and dividers enabled X 1 1 1 1 Transmit mode 1, PA enabled. Reference, PLL, VCO and dividers enabled
/C0084/C0082/C0070/C0054/C0057/C0048/C0051 /C0083/C0073/C0078/C0071/C0076/C0069/C0262/C0067/C0072/C0073/C0080 /C0077/C0085/C0076/C0084/C0073/C0066/C0065/C0078/C0068 /C0082/C0070 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 SWRS022D − MARCH 2004 − REVISED JUNE 2005
30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
LPF_IN LEARN/ RSSI_ IF_IN2 IF_IN1 DET_OUT MIX_OUT HOLD OUT 242322212019181716151413 Data Slicer LPF_OUT CER_DIS SLC_CAP RX_DATA TX_DATA XTAL_SW XTAL CP_VCC CP_OUT VCO_TUNE PA_OUT PA_VCC VCO_VCC VCO_TANK2 VCO_BYPASS TRF6903 PLL VCO RX_IN+ LNA_VCC VCO_VCC C11 PA_VCC2 TX_OUT C14 C18 100 pF C19 C21 R4C20 DVDD CLOCK STROBE DATA MODE CP_VCC XTAL1 C15 C16 DCLK XTAL_VCC TX_DATA RX_DATA C10 220 kΩ LRN/HOLD DEM_VCC RSSI DET_OUT 4.7µ H MIX_VCC 82 pF C2 100 pF BPF1 SFECF10M7 Series 120 pF 82 pF 4.7µ H 1, 2, 3 Divider VCO_VCC LOCK_DETECT Bit Synchronizer Data Clock and RX_FLAG CDSCB10M7GA119−R0 STDBY DVDD MIX_VCC LNA_VCC MuRata DIS 1
10.7 MHz
PA_VCC1 C12 017119 C23 0.1 µF R2 (See Note E) 100 Ω C22 0.1 µF C17 0.1 µF C13 0.22 µF DEM_VCC XTAL_VCC VCO_VCC CP_VCC PA_VCC2 PA_VCC1 10 µF0.1 µF C24 C25 NOTE: See Table 5 for component selection for band of operation. Figure 11. Typical TRF6903 FSK Application Schematic
/C0084/C0082/C0070/C0054/C0057/C0048/C0051 /C0083/C0073/C0078/C0071/C0076/C0069/C0262/C0067/C0072/C0073/C0080 /C0077/C0085/C0076/C0084/C0073/C0066/C0065/C0078/C0068 /C0082/C0070 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 SWRS022D − MARCH 2004 − REVISED JUNE 2005 31POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Table 5. Component Selection for Band of Operation, FSK
315 MHz 433 MHz 868 MHz 915 MHz
B. Post detection low-pass filter selected for 19.2-kbps Manchester or 38.4-kbps NRZ. D. XTAL switch capacitors selected for the frequency deviation of ±50 kHz. E. R2 = 100 Ω is optional for operation in the 868-MHz and 915-MHz bands.
/C0084/C0082/C0070/C0054/C0057/C0048/C0051 /C0083/C0073/C0078/C0071/C0076/C0069/C0262/C0067/C0072/C0073/C0080 /C0077/C0085/C0076/C0084/C0073/C0066/C0065/C0078/C0068 /C0082/C0070 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 SWRS022D − MARCH 2004 − REVISED JUNE 2005
32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
LPF_IN LEARN/ RSSI_ IF_IN2 IF_IN1 DET_OUT MIX_OUT HOLD OUT 242322212019181716151413 Data Slicer LPF_OUT CER_DIS SLC_CAP RX_DATA TX_DATA XTAL_SW XTAL CP_VCC CP_OUT VCO_TUNE PA_OUT PA_VCC VCO_VCC VCO_TANK2 VCO_BYPASS TRF6903 PLL VCO RX_IN+ LNA_VCC VCO_VCC C11 PA_VCC2 TX_OUT C14 C18 100 pF C19 C21 R4C20 DVDD CLOCK STROBE DATA MODE CP_VCC XTAL1 C15 27 pF DCLK XTAL_VCC TX_DATA RX_DATA C10 LRN/HOLD DEM_VCC RSSI DET_OUT 4.7µ H MIX_VCC 82 pF C2 100 pF BPF1 SFECF10M7 Series 120 pF 82 pF 4.7µ H 1, 2, 3 Divider VCO_VCC LOCK_DETECT Bit Synchronizer Data Clock and RX_FLAG STDBY MuRata CrystekPA_VCC1 27 kΩ DNP C12 017119 DVDD MIX_VCC LNA_VCC VCC DEM_VCC XTAL_VCC VCO_VCC CP_VCC PA_VCC2 PA_VCC1 10 µF0.1 µF C23 0.1 µF 0.22 µF C22 0.1 µF C17 0.1 µF C13 C24 C25 NOTE: See Table 6 for component selection for band of operation. Figure 12. Typical TRF6903 OOK Application Schematic With Ceramic IF Filter
/C0084/C0082/C0070/C0054/C0057/C0048/C0051 /C0083/C0073/C0078/C0071/C0076/C0069/C0262/C0067/C0072/C0073/C0080 /C0077/C0085/C0076/C0084/C0073/C0066/C0065/C0078/C0068 /C0082/C0070 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 SWRS022D − MARCH 2004 − REVISED JUNE 2005 33POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Table 6. Component Selection for Band of Operation, OOK
/C0084/C0082/C0070/C0054/C0057/C0048/C0051 /C0083/C0073/C0078/C0071/C0076/C0069/C0262/C0067/C0072/C0073/C0080 /C0077/C0085/C0076/C0084/C0073/C0066/C0065/C0078/C0068 /C0082/C0070 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 SWRS022D − MARCH 2004 − REVISED JUNE 2005
34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Revision History
DATE REV PAGE SECTION DESCRIPTION 6/2/05 D 1 — Added application drawing to front page. — C — — Information not available — B — — Information not available — A — — Information not available — * — — Information not available NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TRF6903PT NRND LQFP PT 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRF6903PTG4 NRND LQFP PT 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRF6903PTR NRND LQFP PT 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRF6903PTRG4 NRND LQFP PT 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 5-Feb-2007 Addendum-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TRF6903PTR LQFP PT 48 1000 346.0 346.0 33.0 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 Pack Materials-Page 2
MTQF003A – OCTOBER 1994 – REVISED DECEMBER 1996 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PT (S-PQFP-G48) PLASTIC QUAD FLATPACK 4040052/C 11/96 0,13 NOM 0,17 0,27 SQ 6,80 7,20 5,50 TYP 0,25 0,45 0,75 0,05 MIN SQ9,20 8,80 1,35 1,45 1,60 MAX Gage Plane Seating Plane 0,10 0°–7° 0,50 M0,08 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 D. This may also be a thermally enhanced plastic package with leads conected to the die pads.
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