TRF6900

TRF6900 TI | Alldatasheet

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SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Single-Chip RF Transceiver for 868 MHz and 915 MHz ISM Bands /C0068850 MHz to 950 MHz Operation /C0068FM/FSK Operation for Transmit and Receive /C006824-Bit Direct Digital Synthesizer (DDS) With 11-Bit DAC /C0068On-Chip VCO and PLL /C0068On-Chip Reference Oscillator /C0068Minimal External Components Required /C0068Low Power Consumption /C0068Typical Output Power of 4.5 dBm /C0068Typical Output Frequency Resolution of 230 Hz /C0068Ultrafast Lock Times From DDS Implementation /C0068Two Fully Programmable Operational Modes /C00682.2 V to 3.6 V Operation /C0068Fast Radio Strength Signal Indicator (RSSI) /C0068Flexible Serial Interface to TI MSP430 Microcontroller /C006848-Pin Low Profile Plastic Quad Flat Package (PQFP) 14 15 17 18 19 20 IF1_OUT IF_GND IF2_IN DEM_GND 47 46 45 44 4348 42 LNA_VCC LNA_OUT MIX_IN MIX_VCC MIX_OUT GND XOSC1 XOSC2 DDS_GND MODE DDS_VCC TX_DATA DIG_VCC DIG_GND 40 39 3841 21 22 23 24 VREF MIX_GND IF1_IN VCO_TANK2 VCO_TANK1 STDBY PQFP PACKAGE (TOP VIEW) LNA_GND LNA_IN LNA_GND PA_VCC PA_OUT PA_GND PLL_GND PD_SET PD_OUT2 PD_OUT1 LOCKDET PLL_VCC DEM_VCC DEM_TANK DEM_TANK RSSI_OUT AMP_IN AMP_CAP AMP_OUT S&H_CAP DATA_OUT DATA CLOCK STROBE These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Copyright  2000, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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description

The TRF6900 single-chip solution is an integrated circuit intended for use as a low cost FSK transceiver to establish a frequency-agile, half-duplex, bidirectional RF link. The device is available in a 48-lead TQFP package and is designed to provide a fully-functional multichannel FM transceiver. The chip is intended for linear (FM) or digital (FSK) modulated applications in the new 868 MHz European band and the North American 915 MHz ISM band. The single chip transceiver operates down to 2.2 V and is expressly designed for low power consumption. The synthesizer has a typical channel spacing of approximately 230 Hz to allow narrow-band as well as wide-band application. Due to the narrow channel spacing of the direct digital synthesizer (DDS), the DDS can be used to adjust the TX/RX frequency and allows the use of inexpensive reference crystals. Two fully-programmable operation modes, Mode0 and Mode1, allow extremely fast switching between two preprogrammed settings (e.g., receive(RX)/transmit(TX); TX_frequency_0/TX_frequency_1; RX_frequency_0/RX_frequency_1;… ) without reprogramming the device. Each functional block of the transceiver can be specifically enabled or disabled via the serial interface. ISM band standards Europe has assigned a new unlicensed frequency band of 868 MHz to 870 MHz. This new band is specifically defined for short range devices with duty cycles from 0.1% to 100% in several sub-bands. The existing 433 MHz band for short-range devices in Europe has the great disadvantage of very high usage. The new European frequency band, due to the duty cycle assignment, allows a reliable RF link and makes many new applications possible. The North American unlicensed ISM (industrial, scientific, and medical) band covers 902 MHz to 928 MHz (center frequency of 915 MHz), and is suitable for short range RF links. transmitter The transmitter consists of an integrated VCO, a complete fully-programmable direct digital synthesizer, and a power amplifier. The internal VCO can be used with an external tank circuit or an external VCO. The divider, prescaler, and reference oscillator require only the addition of an external crystal and a loop filter to provide a complete DDS with a typical frequency resolution of 230 Hz. The 8-bit FSK frequency deviation register determines the frequency deviation in FSK mode. The modulation itself is done in the direct digital synthesizer, hence no additional external components are necessary. Since the typical RF output power is approximately 4.5 dBm, no additional external RF power amplifier is necessary in most applications. receiver The integrated receiver is intended to be used as a single-conversion FSK receiver. It consists of a low noise amplifier, mixer, IF amplifier, limiter, FM/FSK demodulator with an external LC tank circuit, and a data slicer. The receive strength signal indicator ( RSSI ) can be used for fast carrier sense detection or as an on/off keying, or amplitude shift keying, (OOK/ASK) demodulator. In the learning mode, during a learning sequence (0,1,0,1,0,....), the initial tolerances of the LC demodulator tank circuit are compensated and an external capacitor is charged to a dc voltage that is proportional to the average demodulation dc level. This level is the zero reference for the data slicer to generate the logical levels of the data sequence that follow the learning sequence. Using the internal data switch, the demodulated OOK and FSK signals are available at the same DATA_OUT terminal. baseband interface The TRF6900 can easily be interfaced to a baseband processor such as the Texas Instruments MSP430 ultra low-power microcontroller (see Figure 1). The TRF6900 serial control registers are programmed by the MSP430 and the MSP430 performs baseband operations in software.

Figure 1. System Block Diagram for Interfacing to the MSP430 Microcontroller

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DIG_VCC DIG_GND GND STDBY VCO_TANK1 MODE DDS_VCC TX_DATA VCO Direct Digital Synthesizer and Power-Down Logic LOCKDET PD_OUT1 PD_OUT2 PD_SET PLL PA_GND PA_OUT PA_VCC LNA_GND LNA_IN LNA_GND PLL_VCC IF2_IN DEM_GND VREF MIX_IN MIX_OUT MIX_GND IF1_IN IF1_OUT IF_GND LNA_OUT LNA_VCC MIX_VCC RF Mixer 1st IF Amplifier 2nd IF Amplifier/ Limiter FM/FSK Demodulator DEM_VCC RSSI_OUT AMP_IN AMP_CAP AMP_OUT S&H_CAP DATA_OUT DATA CLOCK STROBE RSSI Data SlicerTRF6900 (TOP VIEW) DEM_TANK DEM_TANK VCO_TANK2 DDS_GND XOSC1 XOSC2 PLL_GND 12 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 45 44 43 42 41 40 39 38 3746 Serial Interface RF Buffer Amplifier LO Buffer Amplifier Power Amplifier Data Switch LPF Amplifier/ Post-Detection Amplifier LNA Buffer Amplifier Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION AMP_CAP 31 I/O Connection for LPF amplifier/post-detection amplifier capacitor/resistor used to reduce the internal low pass filter frequency and to adjust the post-detection gain AMP_IN 32 I Analog post-detection amplifier input AMP_OUT 30 O Analog post-detection amplifier output CLOCK 26 I Serial interface clock signal DATA 27 I Serial interface data signal DATA_OUT 28 O Digital output of the data slicer, active high DDS_GND 15 Direct digital synthesizer ground

SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION DDS_VCC 18 Direct digital synthesizer supply voltage DEM_GND 38 Quadrature demodulator ground DEM_TANK 34, 35 I/O Quadrature demodulator tank connection DEM_VCC 36 Quadrature demodulator supply voltage DIG_GND 21 Digital ground DIG_VCC 20 Digital supply voltage IF_GND 40 Intermediate frequency (IF) section ground IF1_IN 42 I Single-ended input for the 1st intermediate frequency (IF) amplifier IF1_OUT 41 O Single-ended output for the 1st intermediate frequency (IF) amplifier IF2_IN 39 I Single-ended input for the 2nd IF amplifier/limiter LNA_GND 1, 3 Low-noise amplifier ground LNA_IN 2 I Low-noise amplifier input LNA_OUT 47 O Low-noise amplifier output, open collector LNA_VCC 48 Low-noise amplifier supply voltage LOCKDET 11 O PLL lock detect output, active high. PLL locked when LOCKDET=1. MIX_GND 43 Mixer ground MIX_IN 46 I Single-ended RF mixer input MIX_OUT 44 O Single-ended RF mixer output MIX_VCC 45 Mixer supply voltage MODE 17 I Mode select input. The functionality of the device in Mode0 or Mode1 can be programmed via the A-, B-, C-, and D-word of the serial control interface. GND 22 Ground PA_GND 6 Power amplifier ground PA_OUT 5 O Power amplifier output, open collector PA_VCC 4 Power amplifier supply voltage PD_OUT1 10 O Charge pump output – PLL in locked condition PD_OUT2 9 O Charge pump output – PLL in unlocked condition PD_SET 8 Charge pump current setting terminal. An external resistor, RPD , is connected to this terminal to set the nominal charge pump current. PLL_GND 7 PLL ground PLL_VCC 12 PLL supply voltage RSSI_OUT 33 O Receive strength signal indicator, analog output S&H_CAP 29 I/O Connection for sample and hold capacitor for the data slicer. This capacitor determines the integration time constant of the integrator while in the learning mode. STDBY 16 I Standby control for the TRF6900, active low. While STDBY=0, the contents of the control registers are still valid and can be programmed via the serial control interface. STROBE 25 I Serial interface strobe signal TX_DATA 19 I Digital modulation input for FSK/FM modulation of the carrier, active high VCO_TANK1 13 I VCO tank circuit connection. Should be left open if an external VCO is used. VCO_TANK2 14 I VCO tank circuit connection. May also be used to input an external VCO signal. VREF 37 I Reference voltage for the quadrature demodulator XOSC1 23 O Reference crystal oscillator connection XOSC2 24 I Reference crystal oscillator connection. May be used as a single-ended clock input if an external crystal is not used.

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absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, PA_VCC, PLL_VCC, DDS_VCC, DIG_VCC, † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All GND and VCC terminals must be connected to either ground or supply, respectively, even if the function block is not used. recommended operating conditions MIN TYP MAX UNIT Supply voltage, PA_VCC, PLL_VCC, DIG_VCC, DDS_VCC, DEM_VCC, MIX_VCC, LNA_VCC 2.2 3.6 V Operating temperature –20 60 °C High-level input voltage, VIH (DATA, CLOCK, STROBE, TX_DATA, MODE, STDBY ) VCC –0.5 V Low-level input voltage, VIL (DATA, CLOCK, STROBE, TX_DATA, MODE, STDBY ) 0.5 V electrical characteristics over full range of operating conditions, (typical values are at PA_VCC, PLL_VCC, DDS_VCC, DIG_VCC, DEM_VCC, MIX_VCC, LNA_VCC = 3 V, TA = 25°C) (unless otherwise noted) supply current consumption in each mode MODE ACTIVE STAGES MIN TYP MAX UNIT Power down (standby mode) None 2 5 mA RX – FSK (narrow-band) or Carrier sense DDS, PLL, VCO, LNA (normal mode), mixer, 1st IF amplifier, limiter, (demodulator, LPF amplifier, data slicer or RSSI) 24 31 mA PA STATE 0 dB attenuation 37 50 TX 10 dB attenuation DDS, PLL, VCO, PA 26 33 mA 20 dB attenuation 21 25 PA disabled 9.5 12

SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over full range of operating conditions, (typical values are at PA_VCC, PLL_VCC, DDS_VCC, DIG_VCC, DEM_VCC, MIX_VCC, LNA_VCC = 3 V, TA = 25°C) (unless otherwise noted) (continued) LNA/RF mixer PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RF frequency range 850 950 MHz LNA gain LNA in normal mode 9 13 dB LNA gain LNA in low-gain mode 2 dB LNA noise figure LNA in normal mode 3.3 5.5 dB LNA input 1 dB compression LNA in normal mode –20 –15 dBm LNA input 1-dB compression LNA in low-gain mode –18 –13 dBm LNA input IP3 LNA in normal mode –12 –5 dBm LNA input IP3 LNA in low-gain mode –6 1 dBm LNA input impedance See Figure 3 W LNA output impedance See Figure 4 W LO frequency range 850 950 MHz IF frequency range 10 21.4 MHz Mixer conversion gain –1 4.5 dB Mixer SSB noise figure IF frequency = 10.7 MHz 26 dB Mixer input impedance See Figure 5 W Mixer input IP3 –7 1 dBm Mixer input 1-dB compression –14 –9 dBm LO level at mixer Input –30 dBm Mixer output impedance IF frequency = 10.7 MHz, See Figure 6 330 W VCO PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Frequency range 850 950 MHz Tuning range 30 MHz Phase noise 50 kHz offset –86 dBc/Hz Tuning voltage 0.5 2.2 V

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electrical characteristics over full range of operating conditions, (typical values are at PA_VCC, PLL_VCC, DDS_VCC, DIG_VCC, DEM_VCC, MIX_VCC, LNA_VCC = 3 V, TA = 25°C) (unless otherwise noted) (continued) 1st IF amplifier PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IF amplifier frequency range 10 21.4 MHz IF amplifier gain 5.5 7 dB IF amplifier noise figure 11 13 dB IF amplifier input 1-dB compression –12 –3 dBm IF amplifier input IP3 –3.5 4 dBm IF amplifier input impedance IF frequency = 10.7 MHz, See Figure 8 330 W IF amplifier output impedance IF frequency = 10.7 MHz, See Figure 9 330 W 2nd IF amplifier/limiter PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IF amplifier/limiter frequency range 10 21.4 MHz IF amplifier/limiter gain 80 dB IF amplifier/limiter noise figure 9 dB IF amplifier/limiter input impedance IF frequency = 10.7 MHz, See Figure 10 330 W RSSI PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RSSI range at limiter input –80 –10 dBm RSSI output voltage range 0.44 2.6 V Nominal slope 19 mV/dB Response time step from power off to –20 dBm at limiter input 1 5 ms low pass filter amplifier [2nd order] PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Internal low pass filter frequency 0.75 MHz demodulator PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Demodulation output bandwidth IF frequency = 10.7 MHz 0.3 MHz Acquisition range IF frequency = 10.7 MHz 300 kHz Slew rate† 2 V/ms † Dependent upon external LC tank circuit. data slicer PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Output current R (load) = 3.3 kW , C(load) = 10 pF 1 mA Rise time R (load) = 3.3 kW , C(load) = 10 pF 0.1 ms

SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over full range of operating conditions, (typical values are at PA_VCC, PLL_VCC, DDS_VCC, DIG_VCC, DEM_VCC, MIX_VCC, LNA_VCC = 3 V, TA = 25 °C) (unless otherwise noted) (continued) direct digital synthesizer (DDS) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Reference oscillator input frequencyƒ f as oscillator 15 26 MHzReference oscillator input frequency, ƒref as buffer 15 26 MH z Programmable DDS divider ratio 22 bits 0 4194303 DDS divider resolution, Dƒ N × ƒref ÷ 224 FSK – modulation register ratio 8 bits 0 1020 FSK – modulation resolution N × ƒref ÷ 222 PLL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RF input frequency 850 950 MHz RF input power Internal VCO by-passed; external input applied to VCO_TANK2 –10 dBm RF input divider ratio, N 256 512 RF output frequency resolution N × ƒref ÷ 224 Charge pump current Programmable with external resistor, 100 kW nominal, APLL = 0 70 mA power amplifier PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Frequency range 850 950 MHz 0 dB attenuation –1 4.5 Am plifier outputpower 10 dB attenuation –5 –0.5 dBmAmplifier output pow er 20 dB attenuation –14 –8 dBm Amplifier off –56 Optimal load impedance See Figure 22 W 2nd-order harmonic VCC = 3 V, 0 dB attenuation –6 dBc 3rd-order harmonic VCC = 3 V, 0 dB attenuation –20 dBc typical mode switching and lock times OPERATION TEST CONDITIONS MIN TYP MAX UNIT Frequency hop time between adjacent channels, during receive‡ From transition of MODE to DATA_OUT valid, Channel spacing = 500 kHz, APLL = 111b (maximum) 30 ms Receive-to-transmit turnaround time‡ From transition of MODE to valid RF signal at PA_OUT, PLL locked, 10.7 MHz RX to TX separation 200 ms Transmit-to-receive turnaround time‡ From transition of MODE to valid data at DATA_OUT, PLL locked, 10.7 MHz RX to TX separation 200 ms Standby to receive time‡ From rising edge of STDBY to valid data at DATA_OUT, APLL = 111b (maximum) 600 ms Standby to transmit time‡ From rising edge of STDBY to valid RF signal at PA_OUT, APLL = 111b (maximum) 500 ms ‡ Highly dependent upon loop filter topology.

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NOTE 2: CLOCK and DATA must both be low when STROBE is asserted (STROBE= 1). Figure 2. Serial Data Interface Timing

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Figure 5. Typical RF Mixer Input Impedance Figure 6. Typical RF Mixer Output Impedance filters. If filters with different impedances are used, an impedance matching network is required. dc-blocking capacitor of 0.1 mF should be used to connect terminal 44 to 42 to maximize receiver sensitivity. Figure 7. Bypassing the 1st IF Amplifier Figure 8 and Figure 9 show the 1st IF amplifier input and output impedances, respectively.

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received signal strength indicator (RSSI) The received signal strength indicator provides a voltage at terminal 33, RSSI_OUT, that is proportional to the RF limiter input level. The slope of the RSSI circuit is typically 19 mV/dB over a frequency range of 10 MHz to 21.4 MHz. Because of its ultrafast response time (typically 1 ms per –20 dBm to off step), the RSSI can easily be used as an amplitude-shift keying (ASK) or on/off keying (OOK) demodulator for data rates up to 100 kBit/sec. FM/FSK demodulator The demodulator is intended for analog (FM) and digital (FSK) frequency demodulation. It consists of a quadrature demodulator with an external LC tank circuit. A variable inductor, internal to the TRF6900, operates in parallel with the external tank circuit (see Figure 13), and is used to adjust the external tank circuit’s resonant frequency. If the tolerances of the external demodulator tank circuit components can provide a maximum frequency error of less than 5%, then no additional adjustments are required. As long as the device is in the learning mode, the internal reactance automatically fine-adjusts the resonant frequency of the external LC tank circuit. Depending on the supply voltage, the tank circuit tuning range is approximately four times the discriminator 3-dB bandwidth. While in the LC demodulator tank circuit are compensated and an external capacitor (connected to terminal 29, S&H_CAP) is charged to a dc voltage that is proportional to the average demodulation dc level. This level establishes the decision threshold voltage and consequently sets the zero reference for the data slicer to generate the logical levels of the data sequence that follow the learning sequence. Therefore, the user can use a non-dc-free data signal. The demodulator will be automatically activated if the limiter (x_LIM) and low-pass filter amplifier (x_LPF) are activated and the data switch is set to FSK/FM reception (x_SW = 0). data switch The TRF6900 incorporates an internal data switch used to select the input signal for the low-pass filter amplifier/post detection amplifier. Depending on the settings in the Mode0 or Mode1 enable registers (C-word, D-word), the user can select between OOK/ASK or FSK baseband processing without having to change external components. low-pass filter amplifier/post-detection amplifier The low-pass filter amplifier/post-detection amplifier is configured to operate as a current-to-voltage amplifier and may be used to realize a low pass filter for post detection. The low-pass amplifier bandwidth may be adjusted according to noise and signal bandwidth requirements. An internal 10 pF capacitor sets the maximum –3 dB corner frequency to approximately 0.75 MHz (see Figures 11 and 12).

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voltage proportional to the frequency error of the external tank circuit as compared to the limiter output signal. AFC loop is open and an external dc voltage can be applied at terminal 29 to set the threshold of the data slicer. dc threshold voltage of the data slicer in hold mode. 23) should be left open or can be used as a buffered version of the signal applied at terminal 24 (see Figure 14). Figure 14. Applying an External Oscillator Signal

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the mode0 frequency, the B-word determines the mode1 frequency) with the two MSB bits set to zero. (see Figure 16 and Figure 17). Figure 17. Implementation of the DDS Frequency and FSK Frequency This frequency modulated output signal is used as a reference input signal for the PLL circuit.

Channel width (frequency deviation) for 2-FSK modulation and channel spacing are software programmable. The minimum channel width and minimum channel spacing depend on the RF system frequency plan. fast lock-times. The PLL lock-times ultimately determine when data can be transmitted or received. prescaler (N-divider) in the feedback loop (see Figure 18). unwanted spurious signals produced by the direct digital synthesizer. Figure 18. Basic PLL Structure for the external tank circuit. x_VCO bit should be set to 0. (used in conjunction with the phase detector). generates the current pulses IPD_1 during normal operation (PLL locked).

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pump current IPD_1 is determined by the nominal value I0 (see Figure 19). Figure 19. Normal Operation Charge Pump Current, IPD_1 Each time the PLL is in an unlocked condition, the acquisition aid charge pump generates current pulses IPD_2 . The IPD_2 current pulses are APLL times larger than I0 (see Figure 20). Figure 20. Acquisition Aid, IPD_2 , and Normal Operation, IPD_1 , Charge Pump Currents noise within the multiplication loop, the lowest divider ratio possible for the target application should be used. Figure 21. Basic 3rd-Order Loop Filter Structure performed and later verified on PCB implementations.

Figure 22. Power Amplifier Output Impedance (S22) at Device Terminal 5

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A 3-wire unidirectional serial bus (CLOCK, DATA, STROBE) is used to program the TRF6900 (see Figure 23). as well as all control registers. At each rising edge of the CLOCK signal, the logic value on the DATA terminal is written into a 24-bit shift register. signals are asynchronous, care should be taken to ensure these signals remain free of glitches and noise. As additional leading bits are ignored, only the least significant 24 bits are serial-clocked into the shift register. in active as well as in standby mode. Figure 23. Serial Interface Block Diagram The control words are 24 bits in length. The first incoming bit functions as the most significant bit ( MSB ). a word are to be changed, then it is sufficient to program only the appropriate 24-bit word. An ADDR equal to 111 is reserved for test purposes and should not be used.

NOTE: Start programming with MSB and ensure that the CLOCK and DATA lines are low during the rising edge of the strobe signal. Figure 24. Serial Control Word Format

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Table 1. Mode0 Control Register Description (D-Word)

Table 2. Mode1 Control Register Description (C-Word)

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Table 3. Miscellaneous Control Register Description terminals used in conjunction with the DDS frequency settings. Table 4. Transmitting Data in FSK Mode (MM bit set to 0) Table 5. Operating Mode Per STDBY Terminal

0 Standby/programming mode – power down of all blocks

1 Operating mode and programming mode

in Figure 25. Several examples of operating sequences are shown in Table 6.

Figure 25. Interaction Between MODE Terminal and Preprogrammed Mode0 and Mode1 Control Registers Table 6. Operating Mode Examples

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standby/programming mode and then receive baseband data while in operating mode. Figure 26. Preloading Serial Control Word and Receiving Baseband Data

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APPLICATION INFORMATION

A typical application schematic for an FSK system operating in the European 868 MHz to 870 MHz ISM band is shown in Figure 27. DIG_VCC DIG_GND GND STDBY DDS_GND MODE DDS_VCC TX_DATAVCO LOCKDET PD_OUT1 PD_OUT2 PD_SET PLL PLL_GND PA_GND Power Amplifier PA_VCC LNA_GND LNA LNA_GND PLL_VCC IF2_IN DEM_GND VREF MIX_IN MIX_OUT MIX_GND IF1_IN IF1_OUT IF_GND LNA_OUT LNA_VCC MIX_VCC RF Mixer 1st IF Amp 2nd IF Amplifier/ Limiter FM/FSK Demodulator DEM_VCC RSSI_OUT AMP_IN AMP_CAP AMP_OUT S&H_CAP DATA_OUT DATA CLOCK STROBE RSSI Data SlicerTRF6900 (TOP VIEW) 470 pF 6.8 nH 100 pF 150 pF 3.3 pF RF_Out 8.2 nF 10 kW 10 nH C23 3.3 pF 820 W

1 MWC22

18 MHz

AMP_OUT RSSI_OUT RX_DATA DATA CLOCK STROBE MODE STDBY TX_DATA LOCKDET C20 12 nF TBD C18 220 pF C19 15 pF 12 nH L4 33 nH FLT-SMD BPF1 FLT-SMD BPF2 C15 47 nF C24 6.8 pF LNA_in 68 kW 8.2 kW Serial Interface Direct Digital Synthesizer and Power-Down Logic XOSC1 XOSC2 150 pF SMV1233–011 820 pF SMA/B/L SMA/B/L 1.2 pF RF Buffer Amplifier Data Switch Buffer Amplifier LPF Amplifier/ Post-Detection Amplifier 48 47 46 45 44 43 42 41 40 39 38 37 242322212019181716151413 C41 150 pF C40 150 pFL1 5.6 nH R5 22 kW C16 18 pF C17 100 pF R28 5.6 kW 2.2 mH Figure 27. Typical Application Schematic for 868 to 870 MHz European ISM Band

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external component list (5% tolerance unless otherwise noted) for Figure 27 DESIGNATOR DESCRIPTION (SIZE) VALUE MANUFACTURER PART NUMBER/COMMENTS C1 Capacitor 8.2 nF C2 Capacitor 820 pF C4 Capacitor 3.3 pF C5 Capacitor 150 pF C6 Capacitor 470 nF C7 Capacitor 100 pF C8 Capacitor 150 pF C9 Capacitor 1.2 pF C15 Capacitor 47 nF C16 Capacitor 18 nF C17 Capacitor 100 pF 1% tolerance C18 Capacitor 220 pF C19 Capacitor 15 pF C20 Capacitor 12 nF C21 Capacitor 15 pF C22 Capacitor 15 pF C23 Capacitor 3.3 pF C24 Capacitor 6.8 pF C40 Capacitor 150 pF C41 Capacitor 150 pF L1 Coil 5.6 nH Murata LQW1608 L2 Coil 6.8 nH Murata LQW1608 L3 Coil 12 nH Murata LQW1608 L4 Coil 33 nH Murata LQW1608 L7 Coil 2.2 mH Murata LQH1N2RZJ04, 5% tolerance L8 Coil 10 nH Murata LQW1608, 5% tolerance R1 Resistor 10 kW R2 Resistor 8.2 kW R3 Resistor 68 kW R4 Resistor Optional R5 Resistor 22 kW R6 Resistor 1 MW R7 Resistor 820 W R28 Resistor 5.6 kW V1 Varactor diode SMV1233-011 Alpha Industries CQ1 Crystal 18 MHz CMAC Frequency Products CX-1 SMI BPF1 Filter Murata SFECV10.7MJ-Z, 10.7 MHz IF filter BPF2 Filter Murata SFECV10.7MJ-Z, 10.7 MHz IF filter

SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 31POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 A typical application schematic for an FSK system operating in the North American 902 MHz to 928 MHz ISM band is shown in Figure 28. 100 W DIG_VCC DIG_GND GND STDBY DDS_GND MODE DDS_VCC TX_DATAVCO LOCKDET PD_OUT1 PD_OUT2 PD_SET PLL PLL_GND PA_GND Power Amplifier PA_VCC LNA_GND LNA LNA_GND PLL_VCC IF2_IN DEM_GND VREF MIX_IN MIX_OUT MIX_GND IF1_IN IF1_OUT IF_GND LNA_OUT LNA_VCC MIX_VCC RF Mixer 1st IF Amp 2nd IF Amplifier/ Limiter FM/FSK Demodulator DEM_VCC RSSI_OUT AMP_IN AMP_CAP AMP_OUT S&H_CAP DATA_OUT DATA CLOCK STROBE RSSI Data SlicerTRF6900 (TOP VIEW) 1 nF 10 nH 100 pF 1 nF 3.3 pF RF_Out 4.7 nF 10 kW C23 2.7 pF R6, 1 MW C22 10 pF C21 10 pF CQ1

25.6 MHz

AMP_OUT RSSI_OUT RX_DATA DATA CLOCK STROBE MODE STDBY TX_DATA LOCKDET C20 0.1 mF C18 100 pF C19 330 pF 8.2 nH L4 18 nH DNP FLT-SMD BPF1 FLT-SMD BPF2 C15 0.1 mF C24 2.7 pF LNA_in 100 kW 6.2 kW Serial Interface Direct Digital Synthesizer and Power-Down Logic XOSC1 XOSC2 0.1 mF SMV1247–079 470 pF SMA/B/L SMA/B/L 1 pF RF Buffer Amplifier Data Switch Buffer Amplifier LPF Amplifier/ Post-Detection Amplifier 48 47 46 45 44 43 42 41 40 39 38 37 242322212019181716151413 C41 0.1 mF C40 0.1 mF 4.7 nH R5 39 kW C25 0.1 mF C26 0.1 mF C27 0.1 mF C31 DNP SAT C29 0.1 mF V1 V2 10 kW C30 0.1 mF C32 4.7 pF 10k C17 100 pF C28 3 pF DNP SAT 2.2 mH L8, 10 nH SMV1247–079 Figure 28. Typical Application Schematic for 902 to 928 MHz North American ISM Band

SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000

32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

external component list (5% tolerance unless otherwise noted) for Figure 28 (continued) DESIGNATOR DESCRIPTION (SIZE) VALUE MANUFACTURER PART NUMBER/COMMENTS C5 Capacitor 1 nF C6 Capacitor 1 nF C7 Capacitor 100 pF C8 Capacitor 0.1 mF C9 Capacitor 1 pF C15 Capacitor 0.1 mF C17 Capacitor 100 pF 1% tolerance C18 Capacitor 100 pF C19 Capacitor 330 pF C20 Capacitor 0.1 mF C21 Capacitor 10 pF C22 Capacitor 10 pF C23 Capacitor 2.7 pF C24 Capacitor 2.7 pF C25 Capacitor 0.1 mF C26 Capacitor 0.1 mF C27 Capacitor 0.1 mF C28 Capacitor 3 pF Select at test (SAT), Do not place (DNP) C29 Capacitor 0.1 mF C30 Capacitor 0.1 mF C31 Capacitor Select at test (SAT), Do not place (DNP) C32 Capacitor 4.7 pF C40 Capacitor 0.1 mF C41 Capacitor 150 pF L1 Coil 4.7 nH Murata LQW1608 L2 Coil 10 nH Murata LQW1608 L3 Coil 8.2 nH Murata LQW1608 L4 Coil 18 nH Murata LQW1608 L7 Coil 2.2 mH Murata LQH1N2RZJ04, 5% tolerance L8 Coil 10 nH Murata LQW1608, 5% tolerance R1 Resistor 10 kW R2 Resistor 6.2 kW R3 Resistor 100 kW R4 Resistor 10 kW R5 Resistor 39 kW R6 Resistor 1 MW R7 Resistor 100 W R8 Resistor 10 kW V1, V2 Varactor diode SMV1247–079 Alpha Industries CQ1 Crystal 25.6 MHz ICM (International Crystal Manufacturing, Incorporated) 865842 BPF1 Filter Murata SFECV10.7H-A, 10.7 MHz IF filter, DNP. If not used, replace with 0.1 mF capacitor. BPF2 Filter Murata SFECV10.7H-A, 10.7 MHz IF filter

SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 33POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA PT (S-PQFP-G48) PLASTIC QUAD FLATPACK 4040052/C 11/96 0,13 NOM 0,17 0,27 SQ 6,80 7,20 5,50 TYP 0,25 0,45 0,75 0,05 MIN SQ9,20 8,80 1,35 1,45 1,60 MAX Gage Plane Seating Plane 0,10 0°–7° 0,50 M0,08 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 D. This may also be a thermally enhanced plastic package with leads connected to the die pads.

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