TRF5901

TRF5901 TI | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 30

Technical content

SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Single-Chip RF Transceiver for 915-MHz ISM Band /C0068902-MHz to 928-MHz Operation /C0068FM/FSK Operation for Transmit and Receive /C006824-Bit Direct Digital Synthesizer (DDS) With 11-Bit DAC /C0068On-Chip VCO and PLL /C0068On-Chip Reference Oscillator /C0068Minimal External Components Required /C0068Low Power Consumption /C0068Typical Output Power of 4.5 dBm /C0068Typical Output Frequency Resolution of 230 Hz /C0068Ultrafast Lock Times From DDS Implementation /C0068Two Fully Programmable Operational Modes /C00683-V to 3.6-V Operation /C0068Fast Radio Strength Signal Indicator (RSSI) /C0068Flexible Serial Interface to TI MSP430 Microcontroller /C006848-Pin Low-Profile Plastic Quad Flat Package (PQFP) 14 15 17 18 19 20 IF1_OUT IF_GND IF2_IN DEM_GND 47 46 45 44 4348 42 LNA_VCC LNA_OUT MIX_IN MIX_VCC MIX_OUT GND XOSC1 XOSC2 DDS_GND MODE DDS_VCC TX_DATA DIG_VCC DIG_GND 40 39 3841 21 22 23 24 VREF MIX_GND IF1_IN VCO_TANK2 VCO_TANK1 STDBY PQFP PACKAGE (TOP VIEW) LNA_GND LNA_IN LNA_GND PA_VCC PA_OUT PA_GND PLL_GND PD_SET PD_OUT2 PD_OUT1 LOCKDET PLL_VCC DEM_VCC DEM_TANK DEM_TANK RSSI_OUT AMP_IN AMP_CAP AMP_OUT S&H_CAP DATA_OUT DATA CLOCK STROBE These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Copyright  2002, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description

The TRF5901 single-chip solution is a low cost FSK transceiver to establish a frequency-agile, half-duplex, bidirectional RF link. The device is available in a 48-lead TQFP package and is designed to provide a fully functional multichannel FM transceiver. The single-chip transceiver operates down to 3 V and is expressly designed for low power consumption. The synthesizer has a typical channel spacing of approximately 230 Hz to allow narrow-band as well as wide-band application. Due to the narrow channel spacing of the direct digital synthesizer (DDS), the DDS can be used to adjust the TX/RX frequency and allows the use of inexpensive reference crystals. Two fully-programmable operation modes, Mode0 and Mode1, allow fast switching between two preprogrammed settings (e.g., TX(RX)_frequency_0, RX(TX)_frequency_1) without reprogramming the device. Each functional block of the transceiver can be specifically enabled or disabled via the serial interface. transmitter The transmitter consists of an integrated VCO, a complete fully programmable direct digital synthesizer, and a power amplifier. The internal VCO can be used with an external tank circuit or an external VCO. The divider, prescaler, and reference oscillator require only the addition of an external crystal and a loop filter to provide a complete DDS with a typical frequency resolution of 230 Hz. The 8-bit FSK frequency deviation register determines the frequency deviation in FSK mode. The modulation itself is done in the direct digital synthesizer, hence no additional external components are necessary. Since the typical RF output power is approximately 4.5 dBm, no additional external RF power amplifier is necessary in most applications. receiver The integrated receiver is intended to be used as a single-conversion FSK receiver. It consists of an integrated VCO, a complete fully programmable direct digital synthesizer, a low-noise amplifier, mixer, IF amplifier, limiter, FM/FSK demodulator with an external LC tank circuit, and a data slicer. The receive strength signal indicator ( RSSI ) can be used for fast carrier sense detection or as an on/off keying, or amplitude shift keying, (OOK/ASK) demodulator tank circuit are compensated and an external capacitor is charged to a dc voltage that is proportional to the average demodulation dc level. This level is the zero reference for the data slicer to generate the logical levels of the data sequence that follow the learning sequence. Using the internal data switch, the demodulated OOK and FSK signals are available at the same DATA_OUT terminal. baseband interface The TRF5901 can easily be interfaced to a baseband processor such as the Texas Instruments MSP430 ultralow-power microcontroller (see Figure 1). The TRF5901 serial control registers are programmed by the MSP430 and the MSP430 performs baseband operations in software.

Figure 1. System Block Diagram for Interfacing to the MSP430 Microcontroller

SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DIG_VCC DIG_GND GND STDBY VCO_TANK1 MODE DDS_VCC TX_DATA VCO Direct Digital Synthesizer, Power-Down Logic, and Buffers LOCKDET PD_OUT1 PD_OUT2 PD_SET PLL PA_GND PA_OUT PA_VCC LNA_GND LNA_IN LNA_GND PLL_VCC IF2_IN DEM_GND VREF MIX_IN MIX_OUT MIX_GND IF1_IN IF1_OUT IF_GND LNA_OUT LNA_VCC MIX_VCC RF Mixer 1st IF Amplifier 2nd IF Amplifier/ Limiter FM/FSK Demodulator DEM_VCC RSSI_OUT AMP_IN AMP_CAP AMP_OUT S&H_CAP DATA_OUT DATA CLOCK STROBE RSSI Data SlicerTRF5901 (TOP VIEW) DEM_TANK DEM_TANK VCO_TANK2 DDS_GND XOSC1 XOSC2 PLL_GND 12 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 45 44 43 42 41 40 39 38 3746 Serial Interface RF Buffer Amplifier LO Buffer Amplifier Power Amplifier Data Switch LPF Amplifier/ Post-Detection Amplifier LNA Buffer Amplifier Terminal Functions TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION AMP_CAP 31 I/O Connection for LPF amplifier/post-detection amplifier capacitor/resistor used to reduce the internal low-pass filter frequency and to adjust the post-detection gain. AMP_IN 32 I Analog post-detection amplifier input AMP_OUT 30 O Analog post-detection amplifier output CLOCK 26 I Serial interface clock signal DATA 27 I Serial interface data signal DATA_OUT 28 O Digital output of the data slicer, active high DDS_GND 15 Direct digital synthesizer ground

SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION DDS_VCC 18 Direct digital synthesizer supply voltage DEM_GND 38 Quadrature demodulator ground DEM_TANK 34, 35 I/O Quadrature demodulator tank connection DEM_VCC 36 Quadrature demodulator supply voltage DIG_GND 21 Digital ground DIG_VCC 20 Digital supply voltage IF_GND 40 Intermediate frequency (IF) section ground IF1_IN 42 I Single-ended input for the 1st intermediate frequency (IF) amplifier IF1_OUT 41 O Single-ended output for the 1st intermediate frequency (IF) amplifier IF2_IN 39 I Single-ended input for the 2nd IF amplifier/limiter LNA_GND 1, 3 Low-noise amplifier ground LNA_IN 2 I Low-noise amplifier input LNA_OUT 47 O Low-noise amplifier output, open collector LNA_VCC 48 Low-noise amplifier supply voltage LOCKDET 11 O PLL lock detect output, active high. PLL locked when LOCKDET = 1. MIX_GND 43 Mixer ground MIX_IN 46 I Single-ended RF mixer input MIX_OUT 44 O Single-ended RF mixer output MIX_VCC 45 Mixer supply voltage MODE 17 I Mode select input. The functionality of the device in Mode0 or Mode1 can be programmed via the A-, B-, C-, and D-word of the serial control interface. GND 22 Ground PA_GND 6 Power amplifier ground PA_OUT 5 O Power amplifier output, open collector PA_VCC 4 Power amplifier supply voltage PD_OUT1 10 O Charge pump output – PLL in locked condition PD_OUT2 9 O Charge pump output – PLL in unlocked condition PD_SET 8 Charge pump current setting terminal. An external resistor (RPD ) is connected to this terminal to set the nominal charge pump current. PLL_GND 7 PLL ground PLL_VCC 12 PLL supply voltage RSSI_OUT 33 O Receive strength signal indicator, analog output S&H_CAP 29 I/O Connection for sample and hold capacitor for the data slicer. This capacitor determines the integration time constant of the integrator while in the learning mode. STDBY 16 I Standby control for the TRF5901, active low. While STDBY = 0, the contents of the control registers are still valid and can be programmed via the serial control interface. STROBE 25 I Serial interface strobe signal TX_DATA 19 I Digital modulation buffered input for FSK/FM modulation of the carrier, active high VCO_TANK1 13 I VCO tank circuit connection. Should be left open if an external VCO is used. VCO_TANK2 14 I VCO tank circuit connection. May also be used to input an external VCO signal. VREF 37 I Reference voltage for the quadrature demodulator XOSC1 23 O Reference crystal oscillator connection XOSC2 24 I Reference crystal oscillator connection. May be used as a single-ended clock input if an external crystal is not used.

SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, PLL_VCC, DDS_VCC, DIG_VCC, PA_VCC, † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All GND and VCC terminals must be connected to either ground or supply, respectively, even if the function block is not used. ESD NOTE: Terminal 5 is not protected against ESD; other terminals have limited ESD protection to 1 kV HBM. recommended operating conditions MIN TYP MAX UNIT Supply voltage, PA_VCC, PLL_VCC, DIG_VCC, DDS_VCC, DEM_VCC, MIX_VCC, LNA_VCC 3 3.6 V Operating temperature –40 85 °C High-level input voltage, VIH (DATA, CLOCK, STROBE, TX_DATA, MODE, STDBY ) VCC –0.5 V Low-level input voltage, VIL (DATA, CLOCK, STROBE, TX_DATA, MODE, STDBY ) 0.5 V High-level output voltage, VOH (LOCKDET, DATA_OUT); IOH = 0.5 mA VCC –0.5 V Low-level output voltage, VOL (LOCKDET, DATA_OUT); IOL = 0.5 mA 0.5 V electrical characteristics over full range of operating conditions, (typical values are at PLL_VCC, DDS_VCC, DIG_VCC, DEM_VCC, MIX_VCC, LNA_VCC, PA_VCC = 3 V, TA = 25°C) (unless otherwise noted) supply current consumption in each mode MODE ACTIVE STAGES MIN TYP MAX UNIT Power down (standby mode) None 0.5 5 µA RX – FSK (narrow band) or carrier sense DDS, PLL, VCO, LNA (normal mode), mixer, first IF amplifier, limiter, (demodulator, LPF amplifier, data slicer or RSSI) 28 35 mA PA STATE 0-dB attenuation 37 53 TX 10-dB attenuation DDS, PLL, VCO, PA 26 35 mA 20-dB attenuation ,, , 21 27 PA disabled 9.5 13

SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over full range of operating conditions, (typical values are at PLL_VCC, DDS_VCC, DIG_VCC, DEM_VCC, MIX_VCC, LNA_VCC, PA_VCC = 3 V, TA = 25°C) (unless otherwise noted) (continued) LNA/RF mixer PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RF frequency range 902 928 MHz LNA gain LNA in normal mode 7.5 12 dB LNA gain LNA in low-gain mode 4 dB LNA noise figure LNA in normal mode 4 5.8 dB LNA input 1 dB compression LNA in normal mode –20 –15 dBm LNA input 1-dB compression LNA in low-gain mode –18 –13 dBm LNA input IP3 LNA in normal mode –12 –5 dBm LNA input IP3 LNA in low-gain mode –6 1 dBm LNA input impedance See Figure 3 Ω LNA output impedance See Figure 4 Ω LO frequency range 891 939 MHz IF frequency range 10.7 MHz Mixer conversion gain 3 7.5 dB Mixer SSB noise figure IF frequency = 10.7 MHz 17.5 dB Mixer input impedance See Figure 5 Ω Mixer input IP3 –8 1 dBm Mixer input 1-dB compression –9 dBm LO level at mixer input –35 dBm Mixer output impedance IF frequency = 10.7 MHz, See Figure 6 330 Ω VCO PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Frequency range 891 939 MHz Tuning range 60 MHz Phase noise 50-kHz offset –86 dBc/Hz Tuning voltage 0.5 VCC –0.4 V first IF amplifier PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IF amplifier frequency range 10.7 MHz IF amplifier gain 5.5 7 dB IF amplifier noise figure 12 14 dB IF amplifier input 1-dB compression –12 –3 dBm IF amplifier input IP3 –3.5 4 dBm IF amplifier input impedance IF frequency = 10.7 MHz, See Figure 8 330 Ω IF amplifier output impedance IF frequency = 10.7 MHz, See Figure 9 330 Ω

SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over full range of operating conditions, (typical values are at PLL_VCC, DDS_VCC, DIG_VCC, DEM_VCC, MIX_VCC, LNA_VCC, PA_VCC = 3 V, TA = 25°C) (unless otherwise noted) (continued) second IF amplifier/limiter PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IF amplifier/limiter frequency range 10.7 MHz IF amplifier/limiter gain† 80 dB IF amplifier/limiter noise figure† 9 dB IF amplifier/limiter input impedance IF frequency = 10.7 MHz, See Figure 10 330 Ω † Not directly accessible, specified by design RSSI PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RSSI range at limiter input –80 –10 dBm RSSI output voltage range 0.44 2.6 V Nominal slope 19 mV/dB Response time step from power off to –20 dBm at limiter input 1 5 µs low-pass filter amplifier [second order] PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Internal low-pass filter frequency 0.75 MHz demodulator PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Demodulation output bandwidth/C0125 IF frequency = 10.7 MHz 0.3 MHz Acquisition range/C0125 IF frequency = 10.7 MHz 300 kHz Slew rate/C0125 2 V/µs ‡ Dependent upon external LC tank circuit. data slicer PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Output current R (load) = 3.3 kΩ , C(load) = 10 pF 1 mA Rise time R (load) = 3.3 kΩ , C(load) = 10 pF 0.1 µs direct digital synthesizer (DDS) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Reference oscillator input frequencyƒ as oscillator 15 26 MHzReference oscillator input frequency, ƒref as buffer 15 26 MHz Programmable DDS divider ratio 22 bits 0 4194303 DDS divider resolution, ∆ƒ N × ƒref ÷ 224 FSK – modulation register ratio 8 bits 0 1020 FSK – modulation resolution N × ƒref ÷ 222

SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over full range of operating conditions, (typical values are at PLL_VCC, DDS_VCC, DIG_VCC, DEM_VCC, MIX_VCC, LNA_VCC, PA_VCC = 3 V, TA = 25°C) (unless otherwise noted) (continued) PLL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RF input frequency 891 939 MHz RF input power Internal VCO bypassed; external input applied to VCO_TANK2 –10 dBm RF input divider ratio, N 256 512 RF output frequency resolution N × ƒref ÷ 224 Charge pump current Programmable with external resistor, 100 kΩ nominal, APLL = 0 70 µA power amplifier PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Frequency range 902 928 MHz 0-dB attenuation –1 4.5 Amplifier output power 10-dB attenuation –5 –0.5 dBmAmplifier output power 20-dB attenuation –14 –8 dBm Amplifier off –56 Optimal load impedance See Figure 22 2nd-order harmonic VCC = 3 V, 0-dB attenuation –13 dBc 3rd-order harmonic VCC = 3 V, 0-dB attenuation –27 dBc typical mode switching and lock times OPERATION TEST CONDITIONS MIN TYP MAX UNIT Frequency hop time between adjacent channels, during receive† From transition of MODE to DATA_OUT valid, channel spacing = 500 kHz, APLL = 111b (maximum) 30 µs Receive-to-transmit turnaround time† From transition of MODE to valid RF signal at PA_OUT, PLL locked, 10.7 MHz RX to TX separation 200 µs Transmit-to-receive turnaround time† From transition of MODE to valid data at DATA_OUT, PLL locked, 10.7 MHz RX to TX separation 200 µs Standby to receive time† From rising edge of STDBY to valid data at DATA_OUT, APLL = 111b (maximum) 600 µs Standby to transmit time† From rising edge of STDBY to valid RF signal at PA_OUT, APLL = 111b (maximum) 500 µs † Highly dependent upon loop filter topology. timing data for serial interface (see Figure 2) PARAMETER MIN MAX UNIT f(CLOCK) CLOCK frequency 20 MHz tw(CLKHI) CLOCK high time pulse width, CLOCK high 25 ns tw(CLKLO) CLOCK low time pulse width, CLOCK low 25 ns tsu(DATA) Setup time, data valid before CLOCK high 25 ns th(DATA) Hold time, data valid after CLOCK high 25 ns tw(STROBEHI) Strobe high time pulse width, STROBE high (see Note 2) 25 ns tw(STROBELO) Strobe low time pulse width, STROBE low 25 ns NOTE 2: CLOCK and DATA must both be low when STROBE is asserted (STROBE = 1).

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Figure 2. Serial Data Interface Timing The low-noise amplifier (LNA) provides a typical gain of 13 dB and a typical noise figure of 3.3 dB. Figure 3. Typical LNA Input Impedance (S11) Figure 4. Typical LNA Output Impedance The low impedance of the LNA input can be easily matched to 50 Ω to interface with a filter or an RF switch.

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Figure 7. Bypassing the First IF Amplifier Figure 8 and Figure 9 show the first IF amplifier input and output impedances, respectively. Figure 8. Typical First IF Amplifier Input Figure 9. Typical FIrst IF Amplifier Output generate a limited signal at the limiter output. The limiter output is directly fed to the FM/FSK demodulator. Figure 10 shows the second IF amplifier/limiter input impedance.

Figure 10. Typical Second IF Amplifier/Limiter Input Impedance (S11) at Device Terminal IF2_IN discriminator 3-dB bandwidth. activated and the data switch is set to FSK/FM reception (x_SW = 0).

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

–3-dB corner frequency to approximately 0.75 MHz (see Figure 11 and Figure 12). Figure 11. First-Order Low-Pass Filter Figure 12. Second-Order Low-Pass Filter the TRF5901 is shown in Figure 13.

Figure 13. AFC Loop to Control the Data Slicer Decision Threshold voltage proportional to the frequency error of the external tank circuit as compared to the limiter output signal. AFC loop is open and an external dc voltage can be applied at terminal 29 to set the threshold of the data slicer. dc threshold voltage of the data slicer in hold mode.

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Figure 14. Applying an External Oscillator Signal programmability, and extremely fast lock times. table, a digital-to-analog converter, and a low-pass filter. All digital blocks are clocked by the reference oscillator. Figure 15. Typical DDS Block Diagram conversion, a low-pass filter is necessary to suppress unwanted spurious responses. multiplies the reference frequency by a predefined factor.

SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TRF5901 direct digital synthesizer implementation (continued) The VCO output frequency, ƒout, which is dependent on the DDS_x frequency settings ( DDS_0 in the A-word or DDS_1 in the B-word ), can be calculated as follows: ƒout/C0043DDS_x /C0032N /C0032 ƒref 224 /C0043N /C0032 ƒref/C0032DDS_x 224 If FSK modulation is selected (MM=0; C-Word, bit 16) the 8-bit FSK deviation register can be used to program the frequency deviation of the 2-FSK modulation. Figure 17 illustrates where the 8 bits of the FSK deviation register map into the 24-bit DDS frequency register. Since the two LSBs are set to zero, the total FSK deviation can be determined as follows: /C0068ƒ2–FSK /C0043N /C0032 DEV /C0032ƒref 222 Hence, the 2-FSK frequency, set by the level of TX_DATA, is calculated as follows: ƒout1:TX_DATA/C0043Low /C0043N /C0032 ƒref/C0032DDS_x 224 ƒout2:TX_DATA/C0043High /C0043N /C0032 ƒref/C0032(DDS_x /C00414 /C0032DEV ) 224 This frequency modulated output signal is used as a reference input signal for the PLL circuit. Note that the frequencies ƒout1 and ƒout2 are centered about the frequency ƒcenter = (ƒout1 + ƒout2)/2. When transmitting FSK, ƒcenter is considered to be the effective carrier frequency and any receiver local oscillator (LO) should be set to the same ƒcenter frequency ± the receiver’s IF frequency (ƒIF) for proper reception and demodulation. For the case of low-side injection, the receiver LO would be set to ƒLO = ƒcenter – ƒIF. Using low-side injection, the received data at terminal 28, DATA_OUT, would be inverted from the transmitted data applied at terminal 19, TX_DATA. Conversely, for high-side injection, the receiver LO would be set to ƒ LO = ƒcenter + ƒIF. Using high-side injection, the received data would be the same as the transmitted data. In addition, when the TRF5901 is placed in receive mode, it is recommended that the TX_DATA terminal be kept low. In this manner, the actual LO frequency injected into the mixer is ƒout1 = ƒLO . If TX_DATA is set high, the contents of the deviation register would offset the receiver LO resulting in poor receiver sensitivity. Channel width (frequency deviation) for 2-FSK modulation and channel spacing are software programmable. The minimum channel width and minimum channel spacing depend on the RF system frequency plan. Since the DDS registers are static, preprogrammed values are retained during standby mode. This feature greatly reduces turnon time, reduces current consumption when coming out of standby mode, and enables very fast lock-times. The PLL lock-times ultimately determine when data can be transmitted or received. phase-locked loop The phase-locked loop (PLL) of the TRF5901 consists of a phase detector (PD) and a frequency acquisiton aid (FD), two charge pumps, an external loop filter, a voltage controlled oscillator (VCO), and a programmable fixed prescaler (N-divider) in the feedback loop (see Figure 18). The PLL as implemented in the TRF5901 multiplies the DDS output frequency and further suppresses the unwanted spurious signals produced by the direct digital synthesizer.

20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Figure 20. Acquisition Aid (IPD_2 ) and Normal Operation (IPD_1 ) Charge Pump Currents noise within the multiplication loop, the lowest divider ratio possible for the target application should be used. be used as a first approach to calculate a basic loop filter. Figure 21 illustrates a basic third-order loop filter. Figure 21. Basic Third-Order Loop Filter Structure performed and later verified on PCB implementations.

Figure 22. Power Amplifier Output Impedance (S22) at Device Terminal 5

22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

A 3-wire unidirectional serial bus (CLOCK, DATA, STROBE) is used to program the TRF5901 (see Figure 23). as well as all control registers. At each rising edge of the CLOCK signal, the logic value on the DATA terminal is written into a 24-bit shift register. signals are asynchronous, care should be taken to ensure these signals remain free of glitches and noise. As additional leading bits are ignored, only the least significant 24 bits are serial-clocked into the shift register. in active as well as in standby mode. The control words are 24 bits in length. The first incoming bit functions as the most significant bit ( MSB ). a word are to be changed, then it is sufficient to program only the appropriate 24-bit word. Figure 23. Serial Interface Block Diagram The E-latch, addressed by an ADDR equal to 111, is reserved for test purposes and should not be used. Inadvertently addressing the E-latch activates the test modes of the TRF5901. starting further operations with the TRF5901.

NOTE: Start programming with MSB and ensure that the CLOCK and DATA lines are low during the rising edge of the strobe signal. Figure 24. Serial Control Word Format

24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Table 1. Mode0 Control Register Description (D-Word)

Table 2. Mode1 Control Register Description (C-Word)

26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Table 3. Miscellaneous Control Register Description TX_DATA terminals used in conjunction with the DDS frequency settings. Table 4. Transmitting Data in FSK Mode (MM bit set to 0) Table 5. Operating Mode Per STDBY Terminal

0 Standby/programming mode – power down of all blocks

1 Operating mode and programming mode

in Figure 25. Several examples of operating sequences are shown in Table 6.

Figure 25. Interaction Between MODE Terminal and Preprogrammed Mode0 and Mode1 Control Registers Table 6. Operating Mode Examples

28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

standby/programming mode and then receive baseband data while in operating mode. Figure 26. Preloading Serial Control Word and Receiving Baseband Data

SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002 29POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA PT (S-PQFP-G48) PLASTIC QUAD FLATPACK 4040052/C 11/96 0,13 NOM 0,17 0,27 SQ 6,80 7,20 5,50 TYP 0,25 0,45 0,75 0,05 MIN SQ9,20 8,80 1,35 1,45 1,60 MAX Gage Plane Seating Plane 0,10 0°–/C02577° 0,50 M0,08 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 D. This may also be a thermally enhanced plastic package with leads connected to the die pads.

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third–party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright  2002, Texas Instruments Incorporated