TRF4903PW

TRF4903 TI | Alldatasheet

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/C0084/C0082/C0070/C0052/C0057/C0048/C0051 /C0083/C0073/C0078/C0071/C0076/C0069/C0262/C0067/C0072/C0073/C0080 /C0077/C0085/C0076/C0084/C0073/C0066/C0065/C0078/C0068 /C0082/C0070 /C0084/C0082/C0065/C0078/C0083/C0077/C0073/C0084/C0084/C0069/C0082 SWRS023B − MAY 2004 − REVISED MARCH 2005 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Single-Chip RF Transmitter for 315-MHz, 433-MHz, 868-MHz, and 915-MHz Industrial, Scientific, and Medical (ISM) Bands /C00682.2-V to 3.6-V Operation /C0068Low Power Consumption /C0068FSK/OOK Operation /C0068Integer-N Synthesizer With Fully Integrated Voltage Controlled Oscillator (VCO) /C0068On-Chip Reference Oscillator and Phase-Locked Loop (PLL) /C0068Power Amplifier With 8-dBm Typical Output Power /C0068Programmable Brownout Detector /C0068Integrated Data Bit Synchronizer and Baud Rate Selection /C0068Flexible 3-Wire Serial Interface /C0068Minimal Number of External Components Required /C006824-Pin Plastic Thin-Shrink Small Outline Package (TSSOP) /C0068Programmable XTAL Trimming /C0068Lock Detect Indicator /C0068Companion Transmitter to the TRF6903 Transceiver PW PACKAGE (TOP VIEW) TX_DATA MODE STDBY PA_OUT PA_GND1 PA_VCC PA_GND2 VCO_PRE_VCC VCO_GND VCO_CORE_VCC VCO_BYPASS VCO_TUNE CLOCK DATA STROBE GND XTAL_SW XTAL DGND DVDD DET_LD_DCLK CP_GND CP_OUT CP_VCC These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the gates. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2005, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046

/C0084/C0082/C0070/C0052/C0057/C0048/C0051 /C0083/C0073/C0078/C0071/C0076/C0069/C0262/C0067/C0072/C0073/C0080 /C0077/C0085/C0076/C0084/C0073/C0066/C0065/C0078/C0068 /C0082/C0070 /C0084/C0082/C0065/C0078/C0083/C0077/C0073/C0084/C0084/C0069/C0082 SWRS023B − MAY 2004 − REVISED MARCH 2005

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description

The TRF4903 single-chip solution is an integrated circuit intended for use as a low-cost multiband FSK or OOK transmitter to establish a frequency-programmable, half-duplex RF link. The multichannel transmitter is intended for digital (FSK, OOK) modulated applications in the North American and European 315-MHz, 433-MHz, 868-MHz, and 915-MHz ISM bands. The single-chip operates down to 2.2 V and is designed for low power consumption. The synthesizer has a typical channel spacing of better than 200 kHz and features a fully-integrated VCO. Only the PLL loop filter is external to the device. Two fully-programmable operation modes, Mode0 and Mode1, allow extremely fast switching between two preprogrammed settings (for example, TX_frequency_0/TX_frequency_1; …) without reprogramming the device. ISM band standards Europe has assigned an unlicensed frequency band of 868 MHz to 870 MHz. This band is specifically defined for short range devices with duty cycles from 0.1% to 100% in several subbands. The new European frequency band, due to the duty cycle assignment, allows a reliable RF link and makes many new applications possible. The North American unlicensed ISM band covers 902 MHz to 928 MHz (center frequency of 915 MHz) and is suitable for short range RF links. transmitter The transmitter consists of an integrated VCO and tank circuit, a complete integer-N synthesizer, and a power amplifier. The dividers, prescaler, and reference oscillator require only the addition of an external crystal and a loop filter to provide a complete PLL with a typical frequency resolution of better than 200 kHz. Since the typical RF output power is approximately 8 dBm, no additional external RF power amplifier is necessary in most applications. Four attenuation setting for the power amplifier are offered. This feature allows the user to fine tune the amplifier for optimal output power. baseband interface The TRF4903 can easily be interfaced to a baseband processor such as the Texas Instruments MSP430 ultralow-power microcontroller (see Figure 1). The TRF4903 serial control registers are programmed by the MSP430 and the MSP430 performs baseband operations in the software. A synchronized data clock, programmable for most common data rates, is provided by the TRF4903. During transmit, the data clock can be used to clock the transmit data from the microcontroller to the TRF4903 at predefined data rates.

Figure 1. System Block Diagram for Interfacing to the MSP430 Microcontroller

14 CP_OUT12VCO_TUNE

/C0084/C0082/C0070/C0052/C0057/C0048/C0051 /C0083/C0073/C0078/C0071/C0076/C0069/C0262/C0067/C0072/C0073/C0080 /C0077/C0085/C0076/C0084/C0073/C0066/C0065/C0078/C0068 /C0082/C0070 /C0084/C0082/C0065/C0078/C0083/C0077/C0073/C0084/C0084/C0069/C0082 SWRS023B − MAY 2004 − REVISED MARCH 2005

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I/O DESCRIPTIONNAME NO. I/O DESCRIPTION CLOCK 24 I Serial interface clock signal input CP_GND 15 Charge pump ground CP_OUT 14 O Charge pump output CP_VCC 13 Charge pump supply voltage DATA 23 I Serial interface data signal input DET_LD_DCLK 16 O Brownout detector (active high), PLL lock detect (active high), and data clock multiplexed output DGND 18 Digital and XTAL oscillator ground DVDD 17 Digital and XTAL oscillator power supply GND 21 Substrate ground MODE 2 I Mode select input PA_GND1 5 Power amplifier ground PA_GND2 7 Power amplifier ground PA_OUT 4 O Power amplifier output PA_VCC 6 Power amplifier supply voltage STDBY 3 I Standby input signal; active low STROBE 22 I Serial interface strobe signal TX_DATA 1 I Buffered TX data input VCO_BYPASS 11 I VCO bypass; connect to ground through a 100-pF capacitor VCO_GND 9 VCO ground VCO_TUNE 12 I Tuning voltage for the integrated VCO VCO_CORE_VCC 10 VCO core supply voltage VCO_PRE_VCC 8 Divider and prescaler supply voltage XTAL 19 I/O Connection to an external crystal reference XTAL_SW 20 I Connection to external capacitor, which sets the frequency deviation of the transmitted signal absolute maximum ratings over operating free-air temperature (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Analog supply voltage 2.2 3.6 V Digital supply voltage 2.2 3.6 V Operating free-air temperature −40 85 °C

/C0084/C0082/C0070/C0052/C0057/C0048/C0051 /C0083/C0073/C0078/C0071/C0076/C0069/C0262/C0067/C0072/C0073/C0080 /C0077/C0085/C0076/C0084/C0073/C0066/C0065/C0078/C0068 /C0082/C0070 /C0084/C0082/C0065/C0078/C0083/C0077/C0073/C0084/C0084/C0069/C0082 SWRS023B − MAY 2004 − REVISED MARCH 2005 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 dc electrical characteristics, VCC = 2.7 V, TA = 25°C supply current PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Standby current STDBY low 0.6 4 µA 315-MHz band 12 15 TX current, PA disabled. PLL, VCO, dividers, and reference active 433-MHz band 11 14 mATX current, PA disabled. PLL, VCO, dividers, and reference active868-MHz band 10 12 mA 915-MHz band 10 12 0-dB attenuation 315-MHz band 37 43 10-dB attenuation 315-MHz band 30 20-dB attenuation 315-MHz band 29 0-dB attenuation 433-MHz band 36 42 10-dB attenuation 433-MHz band 29 TX current‡, PA enabled. PLL, VCO, dividers,20-dB attenuation 433-MHz band 28 mATX current‡, PA enabled. PLL, VCO, dividers, reference, and data clock active 0-dB attenuation 868-MHz band 35 40 mA 10-dB attenuation 868-MHz band 28 20-dB attenuation 868-MHz band 27 0-dB attenuation 915-MHz band 35 40 10-dB attenuation 915-MHz band 28 20-dB attenuation 915-MHz band 27 ‡ The TX current consumption is dependent upon the external PA matching circuit. The matching network is normally designed to achieve the highest output power at the 0-dB attenuation setting. Changing the external matching components to optimize the output power for other attenuation settings alters the typical current consumption from the typical values noted. digital interface PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH High-level input voltage VDD −0.4 VDD V VIL Low-level input voltage 0 0.4 V VOH High-level output voltage IOH = 0.5 mA VDD −0.4 V VOL Low-level output voltage IOL = 0.5 mA 0.4 V Digital input leakage current <0.01 µA VCO/output divider PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Frequency range: 315-MHz band Low-side injection, A<1:0> = 11 304 315 316 MHz Frequency range: 433-MHz band High-side injection, A<1:0> = 10430 433 450 MHz Frequency range: 868-MHz band High-side injection, A<1:0> = 01868 869 870 MHz Frequency range: 915-MHz band Low-side injection, A<1:0> = 01 902 915 928 MHz Closed loop phase noise Frequency offset = 50 kHz −77 dBc/HzClosed loop phase noise Frequency offset = 200 kHz −90 dBc/Hz Tuning voltage 0.1 VCC at terminal 11 V

/C0084/C0082/C0070/C0052/C0057/C0048/C0051 /C0083/C0073/C0078/C0071/C0076/C0069/C0262/C0067/C0072/C0073/C0080 /C0077/C0085/C0076/C0084/C0073/C0066/C0065/C0078/C0068 /C0082/C0070 /C0084/C0082/C0065/C0078/C0083/C0077/C0073/C0084/C0084/C0069/C0082 SWRS023B − MAY 2004 − REVISED MARCH 2005

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ac electrical characteristics, VCC = 2.7 V, TA = 25°C (continued) impedances and loads PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PA_OUT See Figure 6 transmitter (XTAL, PLL, VCO, and PA), 315-MHz band PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TX frequency range A<1:0> = 11 304 315 316 MHz 0-dB attenuation 8 Output power† 10-dB attenuation −2 dBmOutput power† 20-dB attenuation −12 dBm Disabled, B<3> = 0 −80 Second harmonic −25 dBc Third harmonic −30 dBc DCLK spurious at fC ± fDCLK /C0119 DCLK active: E<15> = 1, E<12:11> = 01 −28 dBc Frequency deviation‡ FSK ±32 kHz Power ON-OFF ratio OOK, 0-dB mode 75 dB Maximum data rate (NRZ) FSK 64 kbit/sMaximum data rate (NRZ) OOK 32 kbit/s † Matched to 50 Ω using external matching network. ‡ Dependent upon external circuitry. § This spur is only present if DCLK is active. The resulting spur is within modulation (OOK or FSK) bandwidth and is considered a modulation product. Within the authorized bands, this spur does not violate FCC or ETSI regulatory compliance. transmitter (XTAL, PLL, VCO, and PA), 433-MHz band PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TX frequency range A<1:0> = 10 430 433 450 MHz 0-dB attenuation 8 Output power† 10-dB attenuation −2 dBmOutput power† 20-dB attenuation −12 dBm Disabled, B<3> = 0 −80 Second harmonic −25 dBc Third harmonic −30 dBc DCLK spurious at fC ± fDCLK /C0119 DCLK active: E<15> = 1, E<12:11> = 01 −28 dBc Frequency deviation‡ FSK ±32 kHz Power ON-OFF ratio OOK, 0-dB mode 75 dB Maximum data rate (NRZ) FSK 64 kbit/sMaximum data rate (NRZ) OOK 32 kbit/s † Matched to 50 Ω using external matching network. ‡ Dependent upon external circuitry. § This spur is only present if DCLK is active. The resulting spur is within modulation (OOK or FSK) bandwidth and is considered a modulation product. Within the authorized bands, this spur does not violate FCC or ETSI regulatory compliance.

/C0084/C0082/C0070/C0052/C0057/C0048/C0051 /C0083/C0073/C0078/C0071/C0076/C0069/C0262/C0067/C0072/C0073/C0080 /C0077/C0085/C0076/C0084/C0073/C0066/C0065/C0078/C0068 /C0082/C0070 /C0084/C0082/C0065/C0078/C0083/C0077/C0073/C0084/C0084/C0069/C0082 SWRS023B − MAY 2004 − REVISED MARCH 2005 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ac electrical characteristics, VCC = 2.7 V, TA = 25°C (continued) transmitter (XTAL, PLL, VCO, and PA), 868-MHz band PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TX frequency range A<1:0> = 11 868 869 870 MHz 0-dB attenuation 8 Output power† 10-dB attenuation −2 dBmOutput power† 20-dB attenuation −12 dBm Disabled, B<3> = 0 −80 Second harmonic −25 dBc Third harmonic −30 dBc DCLK spurious at fC ± fDCLK /C0119 DCLK active: E<15> = 1, E<12:11> = 01 −28 dBc Frequency deviation‡ FSK /C000632 kHz Power ON-OFF ratio OOK, 0-dB mode 75 dB Maximum data rate (NRZ) FSK 64 kbit/sMaximum data rate (NRZ) OOK 32 kbit/s † Matched to 50 Ω using external matching network. ‡ Dependent upon external circuitry. § This spur is only present if DCLK is active. The resulting spur is within modulation (OOK or FSK) bandwidth and is considered a modulation product. Within the authorized bands, this spur does not violate FCC or ETSI regulatory compliance. transmitter (XTAL, PLL, VCO, and PA), 915-MHz band PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TX frequency range A<1:0> = 11 902 915 928 MHz 0-dB attenuation 8 Output power† 10-dB attenuation −2 dBmOutput power† 20-dB attenuation −12 dBm Disabled, B<3> = 0 −80 Second harmonic −25 dBc Third harmonic −30 dBc DCLK spurious at fC ± fDCLK /C0119 DCLK active: E<15> = 1, E<12:11> = 01 −28 dBc Frequency deviation‡ FSK /C000632 kHz Power ON-OFF ratio OOK, 0-dB mode 75 dB Maximum data rate (NRZ) FSK 64 kbit/sMaximum data rate (NRZ) OOK 32 kbit/s † Matched to 50 Ω using external matching network. ‡ Dependent upon external circuitry. § This spur is only present if DCLK is active. The resulting spur is within modulation (OOK or FSK) bandwidth and is considered a modulation product. Within the authorized bands, this spur does not violate FCC or ETSI regulatory compliance.

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Note: Most significant bit (MSB) clocked in first to the synthesizer. Figure 2. Timing Data for Serial Interface

NOTE: TX_DATA is latched at the rising edge of DCLK. Figure 3. Timing Data for DCLK and TX_DATA can then latch TXDATA on the rising edge of DCLK. For more details, see the data clock section. (kbps) vs selected crystal frequencies (MHz) and the respective settings of D1, D2, and D3. The data clock circuit is designed to reset/clear internally with no user action required.

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Table 1. Common Bit Rates, Corresponding Crystal Frequencies, and Values of D1, D2, and D3

/C0084/C0082/C0070/C0052/C0057/C0048/C0051 /C0083/C0073/C0078/C0071/C0076/C0069/C0262/C0067/C0072/C0073/C0080 /C0077/C0085/C0076/C0084/C0073/C0066/C0065/C0078/C0068 /C0082/C0070 /C0084/C0082/C0065/C0078/C0083/C0077/C0073/C0084/C0084/C0069/C0082 SWRS023B − MAY 2004 − REVISED MARCH 2005 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 detailed description (continued) PLL The phase-locked loop is the radio frequency synthesizer for the TRF4903. It is used to generate the transmit signal and as the local oscillator for the receive mixer. The signal (FX) from a reference crystal oscillator (XO) is divided by an integer factor R down to FR . The minimum frequency resolution, and thus, the minimum channel spacing, is FR . FR = FX ÷ R where 1 ≤ R ≤ 256 The phase-locked loop is an integer-N design. The voltage-controlled oscillator (VCO) signal is divided by an integer factor N to get a frequency at the phase detector input. FPD = FVCO ÷ N The phase detector compares the divided VCO signal to the divided crystal frequency and implements an error signal from two charge pumps. The error signal corrects the VCO output to the desired frequency. As is in any integer-N PLLs, the VCO output has spurs at integer multiples of the reference frequency (nFR ). In applications requiring contiguous frequency channels, the reference frequency is often chosen to be equal to the channel spacing, thus, channel spacing = F R = FX ÷ R. When enabled and when the PLL is locked, the DET_LD_DCLK terminal is high. With the addition of an output divider for multiband operation, the actual output frequency, Fout, is given by: Fout/C0043 FVCO P /C0043 FX R /C0032N P /C0043FR /C0032N P /C0043A /C004132B P /C0032FR where FR = FPD under locked conditions. The actual minimum channel spacing is: FR P /C0043 FX /C0066R P where P = 1, 2, 3 and is set by A<1:0>. oscillator circuit and reference divider The reference divider reduces the frequency of the external crystal (FX) by an 8-bit programmable integer divisor, R, to an internal reference frequency (FR ) used for the phase-locked loop. The choice of internal reference frequency also has implications for lock time, maximum data rate, noise floor, and loop-filter design. The crystal frequency can be tuned using the F word to control internal trimming capacitors, which are placed in parallel with the crystal. These offset a small frequency error in the crystal. In an FSK application, an additional capacitor is placed in parallel (through terminal 19) with the external capacitor that is connected in series with the crystal, thus, changing the load capacitance as the transmit data switch (TX_DATA, terminal 1) is toggled. The change in load capacitance pulls the crystal off-frequency by the total frequency deviation. Hence, the 2-FSK frequency, set by the level of TX_DATA and the external capacitor, can be represented as follows: ƒ out1/C0043TX_DATA Low (XTAL switch closed)ƒout2/C0043TX_DATA High (XTAL switch open) Note that the frequencies ƒout1 and ƒout2 are centered about the frequency ƒcenter = (ƒout1 + ƒout2)/2. When transmitting FSK, ƒcenter is considered to be the effective carrier frequency and any receiver local oscillator (LO) should be set to the same ƒcenter frequency ± the receiver’s IF frequency (ƒIF) for proper reception and demodulation.

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

would be the same as the transmitted data.

14 External

Figure 4. TRF4903 PLL and Output Divider three steps: 250 µA, 500 µA, and 1000 µA. using standard formulas in reference literature. Some third-order filter examples are shown in Table 2.

Figure 5. Third-Order Loop Filter and Transfer Function Table 2. Loop Filter Component Values For Various Data Rates at a Reference Frequency of 409.6 kHz, inductors. The open-loop VCO gain is approximately 100 MHz/V. these blocks are powered down. amplifier on and off according to the transmit data incident at terminal 1.

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Figure 6. Typical PA Output Impedance (S22) at Device Terminal PA_OUT threshold is set with the B word. Four different thresholds are available. varies from 15 bits to 22 bits. Normal (write) operation of the serial interface is to clock in 24 bits through the CLOCK and DATA terminals. value is decoded and written into the appropriate data register on the rising edge of STROBE.

/C0084/C0082/C0070/C0052/C0057/C0048/C0051 /C0083/C0073/C0078/C0071/C0076/C0069/C0262/C0067/C0072/C0073/C0080 /C0077/C0085/C0076/C0084/C0073/C0066/C0065/C0078/C0068 /C0082/C0070 /C0084/C0082/C0065/C0078/C0083/C0077/C0073/C0084/C0084/C0069/C0082 SWRS023B − MAY 2004 − REVISED MARCH 2005 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION register description /C0050/C0051/C0050/C0050/C0050/C0049/C0050/C0048/C0049/C0057/C0049/C0056/C0049/C0055/C0049/C0054/C0049/C0053/C0049/C0052/C0049/C0051/C0049/C0050/C0049/C0049/C0049/C0048/C0057/C0056/C0055/C0054/C0053/C0052 /C0051/C0050/C0049/C0048 /C0087/C0111/C0114/C0100/C0065/C0100/C0100/C0114/C0101/C0115/C0115 /C0065/C0100/C0100/C0114/C0101/C0115/C0115 /C0065/C0048/C0048 /C0077/C0097/C0105/C0110 /C0065/C0262/C0068/C0105/C0118/C0105/C0100/C0101/C0114 /C0067/C0111/C0101/C0102/C0102/C0105/C0099/C0105/C0101/C0110/C0116 /C0040/C0077/C0111/C0100/C0101 /C0048/C0041 /C0077/C0097/C0105/C0110 /C0066/C0262/C0068/C0105/C0118/C0105/C0100/C0101/C0114 /C0067/C0111/C0101/C0102/C0102/C0105/C0099/C0105/C0101/C0110/C0116 /C0040/C0077/C0111/C0100/C0101 /C0048/C0041 /C0080/C0065/C0048/C0049 /C0114 /C0067/C0080 /C0065/C0099/C0099/C0046/C0066/C0078/C0068 /C0066/C0048/C0049 /C0077/C0097/C0105/C0110 /C0065/C0262/C0068/C0105/C0118/C0105/C0100/C0101/C0114 /C0067/C0111/C0101/C0102/C0102/C0105/C0099/C0105/C0101/C0110/C0116 /C0040/C0077/C0111/C0100/C0101 /C0049/C0041 /C0077/C0097/C0105/C0110 /C0066/C0262/C0068/C0105/C0118/C0105/C0100/C0101/C0114 /C0067/C0111/C0101/C0102/C0102/C0105/C0099/C0105/C0101/C0110/C0116 /C0040/C0077/C0111/C0100/C0101 /C0049/C0041 /C0080/C0065/C0049/C0049/C0070/C0083/C0075/C0047 /C0079/C0079/C0075/C0080/C0065/C0069/C0068/C0068/C0101/C0116/C0101/C0099/C0116/C0111/C0114 /C0084/C0104/C0114/C0101/C0115/C0104/C0111/C0108/C0100 /C0068/C0101/C0116/C0046 /C0069/C0110/C0097/C0098/C0108/C0101 /C0067/C0049/C0048 /C0082/C0101/C0102/C0101/C0114/C0101/C0110/C0099/C0101 /C0068/C0105/C0118/C0105/C0100/C0101/C0114 /C0067/C0111/C0101/C0102/C0102/C0105/C0099/C0105/C0101/C0110/C0116/C0082/C0101/C0115/C0101/C0114/C0118/C0101/C0100/C0114/C0114 /C0114 /C0114/C0114/C0048/C0048 /C0069/C0049/C0048 /C0066/C0082/C0065/C0066/C0082/C0066/C0066/C0082/C0067/C0084/C0088/C0077/C0048/C0048 /C0077/C0085/C0088/C0114/C0114/C0114/C0114/C0114/C0114 /C0114 /C0114/C0114/C0048/C0049 /C0068/C0049/C0049/C0114/C0079/C0079/C0075/C0088/C0083/C0114 /C0088/C0084/C0065/C0076/C0095/C0084/C0117/C0110/C0101/C0080/C0070/C0068 /C0114/C0101/C0115/C0101/C0116/C0049 /C0049 /C0114 /C0114 /C0114/C0114/C0114/C0114/C0114/C0114 /C0114 /C0114/C0114/C0114/C0048 NOTE: r = reserved. All reserved bits should be set low (0) during normal operation. NOTE: All bits indicated as 1 should be set high (1) during normal operation. NOTE: All bits indicated as 0 should be set low (0) during normal operation. ADDRESS LOCATION NO. OF BITS DESCRIPTION DEFAULT VALUE 00xx 21:17 5 Main A divider coefficient (Mode 0) 00000 00xx 16:8 9 Main B divider coefficient (Mode 0) 001110000 00xx 7:6 2 Controls the PA attenuation (Mode 0) 10 00xx 5 1 Enables transmit path (Mode 0); set to 1 1 00xx 3:2 2 Controls charge pump peak current 00 00xx 1:0 2 Output divider coefficient; band select 10 01xx 21:17 5 Main A divider coefficient (Mode 1) 00000 01xx 16:8 9 Main B divider coefficient (Mode 1) 001110000 01xx 7:6 2 Controls the PA attenuation (Mode 1) 10 01xx 5 1 Enables transmit path (Mode 1); set to 1 1 01xx 4 1 Controls modulation scheme (FSK or OOK) 0 01xx 3 1 Enables or disables the power amplifier 0 01xx 2:1 2 Sets threshold for the brownout detector 00 01xx 0 1 Enables brownout detector 0 1000 21:14 8 Reference divider coefficient 01000000 1001 21:20 2 Bit-rate divider D1 11 1001 19:17 3 Bit-rate divider D2 010 1001 16 1 Bit-rate divider D3 0 1001 15 1 Transmit capture mode select 0 1001 12:11 2 Determines the function of terminal 16, DET_LD_DCLK 00 11x0 20 1 Controls the position of the XTAL switch during OOK operation0 11x0 18:16 3 Tunes the XTAL frequency by using an internal capacitor bank000 11x0 15 1 PFD reset 1 NOTE: x = don’t care

/C0084/C0082/C0070/C0052/C0057/C0048/C0051 /C0083/C0073/C0078/C0071/C0076/C0069/C0262/C0067/C0072/C0073/C0080 /C0077/C0085/C0076/C0084/C0073/C0066/C0065/C0078/C0068 /C0082/C0070 /C0084/C0082/C0065/C0078/C0083/C0077/C0073/C0084/C0084/C0069/C0082 SWRS023B − MAY 2004 − REVISED MARCH 2005

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

At power on/startup, all of the TRF4903 register contents are as per the default values. Address 00XX (A-Word) Word A is a 22-bit data register comprising five fields. The main A-divider coefficient (mode 0), A<21:17>, is the 5-bit divider ratio of the A counter when the MODE terminal is low. The main B-divider coefficient (mode 0), A<16:8>, is the 9-bit value of the B counter when the MODE terminal is low. A <21:17> and A <16:8> are unsigned binary values. PA0, A<7:6>, is the 2-bit PA attenuation setting when the MODE terminal is low. CP Acc., A<3:2>, sets the charge pump current. BND, A<1:0>, sets the output divider, which in turn determines the band of operation. Terminal 2 (MODE) selects bits A<21:5> if low, or B<21:5> if high. Main divider A<21:17>: 5-bit value for divider ratio of the A counter Main divider A<16:8>: 9-bit value for divider ratio of the B counter PA attenuation A<7:6>: 2 bits for setting the PA attenuation A<7:6> PA ATTENUATION 00 0 dB 01 10 dB 10 20 dB

11 Not defined

A<5>: 1-bit; set high A<3:2>: 2 bits for setting the charge pump current A<3:2> CP CURRENT 00 0.5 mA 01 1 mA 10 0.25 mA A<1:0>: 2-bit value to set the output divider and thus select the band of operation. A<1:0> OUTPUT DIVIDER RATIO, P BAND OF OPERATION 00 3 315 MHz 01 2 433 MHz 10 1 868 MHz or 915 MHz 11 1 868 MHz or 915 MHz Bit A<4> is reserved and should be set to 0.

/C0084/C0082/C0070/C0052/C0057/C0048/C0051 /C0083/C0073/C0078/C0071/C0076/C0069/C0262/C0067/C0072/C0073/C0080 /C0077/C0085/C0076/C0084/C0073/C0066/C0065/C0078/C0068 /C0082/C0070 /C0084/C0082/C0065/C0078/C0083/C0077/C0073/C0084/C0084/C0069/C0082 SWRS023B − MAY 2004 − REVISED MARCH 2005 17POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION Address 01XX (B-Word) Word B is a 22-bit data register comprising seven fields. The main A-divider coefficient (mode 1), B<21:17>, is the 5-bit divider ratio of the A counter when the MODE terminal is high. The main B-divider coefficient (mode 1), B<16:8>, is the 9-bit value of the B counter when the MODE terminal is high. B<21:17> and B<16:8> are unsigned binary values. PA1, B<7:6>, is the 2-bit PA attenuation setting when the MODE terminal is high. FSK/OOK, B<4>, sets the modulation scheme for TX. Bit B<3> enables/disables the power amplifier while in transmit mode. The detector threshold, B<2:1>, is the 2-bit setting for the threshold voltage of the brownout detector. Det. Enable, B<0>, is the brownout detector enable flag. Terminal 21 (MODE) selects bits A<21:5> if low, or B<21:5> if high. Main divider B<21:17>: 5-bit value for divider ratio of the A-counter Main divider B<16:8>: 9-bit value for divider ratio of the B-counter PA attenuation B<7:6>: 2 bits for setting the PA attenuation B<7:6> PA ATTENUATION 00 0 dB 01 10 dB 10 20 dB B<5>: 1-bit; set high B<4> 1-bit modulation select B<4> TX MODULATION

0 OOK

1 FSK

B<3>: 1-bit PA enable/disable B<3> PA ENABLE/DISABLE

0 PA disabled

1 PA enabled

B<2:1>: 2-bit value to set the threshold voltage for the brownout detector B<2:1> THRESHOLD VOLTAGE 00 2.2 V 01 2.4 V 10 2.6 V 11 2.8 V B<0>: 1 bit to enable brownout detector B<0> BROWNOUT DETECTOR

0 Off

/C0084/C0082/C0070/C0052/C0057/C0048/C0051 /C0083/C0073/C0078/C0071/C0076/C0069/C0262/C0067/C0072/C0073/C0080 /C0077/C0085/C0076/C0084/C0073/C0066/C0065/C0078/C0068 /C0082/C0070 /C0084/C0082/C0065/C0078/C0083/C0077/C0073/C0084/C0084/C0069/C0082 SWRS023B − MAY 2004 − REVISED MARCH 2005

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Address 1000 (C-Word) Word C is a 20-bit data register comprising four fields. The reference divider coefficient, C<21:14>, is the 8-bit divider ratio of the reference divider. The allowable reference divider range is 2 (C <21:14> = 00000010) through 255 (C <21:14> = 11111111). Reference divider C <21:14>: 8-bit value for divider ratio of reference divider. C<21:14> is an unsigned binary value. Bits C<13> through C<2> are reserved and should be set to 0.

/C0084/C0082/C0070/C0052/C0057/C0048/C0051 /C0083/C0073/C0078/C0071/C0076/C0069/C0262/C0067/C0072/C0073/C0080 /C0077/C0085/C0076/C0084/C0073/C0066/C0065/C0078/C0068 /C0082/C0070 /C0084/C0082/C0065/C0078/C0083/C0077/C0073/C0084/C0084/C0069/C0082 SWRS023B − MAY 2004 − REVISED MARCH 2005 19POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION Address 1001 (E-Word) Word E is a 20-bit data register comprising five fields. The bit rate or bit frequency, used by the transmit synchronous mode is controlled by the BRA, E<21:20>, BRB, E<19:17>, and BRC, E<16>, fields. These three fields control a sequence of dividers, D1 through D3, that divide the reference (crystal) frequency, F E<21:20>: 2 bits to set D1 divider setting E<21:20> D1 00 1 01 5 10 6 11 8 E<19:17>: 3 bits to set D2 divider setting E<19:17> D2 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 E<16>: 1 bit to set D3 divider setting E<16> D3 0 16 1 15 TXM, E<15>, sets the transmit capture mode. If TXM is low, the TX_DATA terminal controls the transmit function asynchronously. If TXM is high and the bit-rate clock enabled, the bit-rate clock, DCLK, is output at the DET_LD_DCLK terminal and the transmit data at the TX_DATA terminal is latched on the rising edge of DCLK. E<12:11>: 2 bits to determine the function of terminal 16 E<12:11> TERMINAL 16, DET_LD_DCLK, FUNCTION

00 PLL lock detect output (default)

01 Data clock output

10 Brownout detect output

11 Not used

Bits E<14>, E<13> and E<10> through E<2> are reserved and should be set to 0.

/C0084/C0082/C0070/C0052/C0057/C0048/C0051 /C0083/C0073/C0078/C0071/C0076/C0069/C0262/C0067/C0072/C0073/C0080 /C0077/C0085/C0076/C0084/C0073/C0066/C0065/C0078/C0068 /C0082/C0070 /C0084/C0082/C0065/C0078/C0083/C0077/C0073/C0084/C0084/C0069/C0082 SWRS023B − MAY 2004 − REVISED MARCH 2005

20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Address 11X0 (D-Word) Word D is a 21-bit data register comprising two fields. Bit D<20> controls the position of the XTAL switch during OOK operation. XTAL_Tune, D<18:16>, is used to fine tune the crystal frequency by using an internal capacitor bank. PFD reset, D<15>, selects the source of the PFD reset signal. D<20>: 1-bit value to control the position of the XTAL switch during OOK operation, when B<4>=0. D<20> XTAL SWITCH DURING OOK OPERATION TERMINAL 20

0 Unconnected (open) High-Z

1 Connected (closed) Shorted to ground externally

It is recommended that D<20> be set to 0 during OOK operation. D<18:16>: 3-bit value to fine-tune the XTAL frequency by using an internal capacitor bank D<18:16> TYPICAL LOAD CAPACITANCE 000 13.23 pF 001 22.57 pF 010 17.9 pF 011 27.24 pF 100 15.56 pF 101 24.9 pF 110 20.23 pF 111 29.57 pF D<15>: 1-bit value to select the reset signal for the PFD D<15> RESET SIGNAL

0 Derived from XTAL

1 Derived from prescaler

NOTE: The default setting for D<15> is 1. Bits D<21>, D<19>, and D<12> through D<1> are reserved and should be set to 0. operating modes Controlled with terminal 3, STDBY STDBY OPERATING MODE

0 Power down of all blocks—programming mode

1 Operational mode and programming mode

Controlled with terminal 2, MODE MODE OPERATING MODE

0 Enable A-word

1 Enable B-word

/C0084/C0082/C0070/C0052/C0057/C0048/C0051 /C0083/C0073/C0078/C0071/C0076/C0069/C0262/C0067/C0072/C0073/C0080 /C0077/C0085/C0076/C0084/C0073/C0066/C0065/C0078/C0068 /C0082/C0070 /C0084/C0082/C0065/C0078/C0083/C0077/C0073/C0084/C0084/C0069/C0082 SWRS023B − MAY 2004 − REVISED MARCH 2005 21POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 operating modes (continued) The transmit mode is controlled by the A<5>, B<5>, and B<3> fields and the MODE and STDBY terminals. A<5> B<5> B<3> MODE STDBY OPERATING MODE X X X X 0 Off, programming mode; SPI enabled

1 X 0 0 1 Transmit mode 0, PA disabled; reference, PLL, VCO, and dividers enabled

1 X 1 0 1 Transmit mode 0, PA enabled; reference, PLL, VCO, and dividers enabled

X 1 0 1 1 Transmit mode 1, PA disabled; reference, PLL, VCO, and dividers enabled X 1 1 1 1 Transmit mode 1, PA enabled; reference, PLL, VCO, and dividers enabled

/C0084/C0082/C0070/C0052/C0057/C0048/C0051 /C0083/C0073/C0078/C0071/C0076/C0069/C0262/C0067/C0072/C0073/C0080 /C0077/C0085/C0076/C0084/C0073/C0066/C0065/C0078/C0068 /C0082/C0070 /C0084/C0082/C0065/C0078/C0083/C0077/C0073/C0084/C0084/C0069/C0082 SWRS023B − MAY 2004 − REVISED MARCH 2005

22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

PA_OUT 1, 2, 3 Divider Bit Synchronizer and Data Clock VCO CP_OUT PLL MUX Brownout Detector Reference Generator XTAL_SW XTAL TX_DATA MODE STDBY VCO_VCC C15 C13 C12 CP_VCC DET_LD_DCLK DVDD XTAL 1 STROBE DATA CLOCK TRF4903 Crystek 100 pF VCO_VCC PA_VCC2 TX_OUT 017119 PA_VCC1 C14 0.1 /C0109F 100 /C0087 (See Note B) 0.1 /C0109F C16 0.1 /C0109F VCO_VCC PA_VCC1 CP_VCC PA_VCC2 DVDD C11 10 /C0109F C10 0.1 /C0109F VCC Component Selection for Band of Operation

315 MHz 433 MHz 868 MHz 915 MHz

Component Value Component Value Component Value Component Value C1 390 pF C1 270 pF C1 43 pF C1 43 pF TX PA C3 5.1 pF C3 4.7 pF C3 1.5 pF C3 1.5 pF TX PA Matching C4 390 pF C4 270 pF C4 39 pF C4 33 pF Matching Network C5 390 pF C5 270 pF C5 39 pF C5 33 pFNetwork L1 560 nH L1 470 nH L1 330 nH L1 270 nH L2 75 nH L2 43 nH L2 18 nH L2 15 nH C12 5600 pF C12 5600 pF C12 5600 pF C12 5600 pF PLL Loop C13 120 pF C13 120 pF C13 120 pF C13 120 pF PLL Loop Filter C15 75 pF C15 75 pF C15 75 pF C15 75 pFFilter R2 15 kΩ R2 15 kΩ R2 15 kΩ R2 15 kΩ R3 7.5 kΩ R3 7.5 kΩ R3 7.5 kΩ R3 7.5 kΩ XTAL Switch C6 27 pF C6 27 pF C6 27 pF C6 27 pFXTAL Switch Capacitors C7 5.6 pF C7 9.1 pF C7 20 pF C7 22 pF Figure 7. Typical TRF4903 FSK Application Schematic B. R1 = 100 Ω is optional for operation in the 868-MHz and 915-MHz bands. C. XTAL switch capacitors selected for the frequency deviation of ±50 kHz.

/C0084/C0082/C0070/C0052/C0057/C0048/C0051 /C0083/C0073/C0078/C0071/C0076/C0069/C0262/C0067/C0072/C0073/C0080 /C0077/C0085/C0076/C0084/C0073/C0066/C0065/C0078/C0068 /C0082/C0070 /C0084/C0082/C0065/C0078/C0083/C0077/C0073/C0084/C0084/C0069/C0082 SWRS023B − MAY 2004 − REVISED MARCH 2005 23POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PA_OUT 1, 2, 3 Divider Bit Synchronizer and Data Clock VCO CP_OUT PLL MUX Brownout Detector Reference Generator XTAL_SW XTAL TX_DATA MODE STDBY VCO_VCC C15 C13 C12 CP_VCC DET_LD_DCLK DVDD XTAL 1 27 pF STROBE DATA CLOCK TRF4903 Crystek 100 pF VCO_VCC PA_VCC2 TX_OUT 017119 PA_VCC1 C14 0.1 /C0109F 0.1 /C0109F C16 0.1 /C0109F VCO_VCC PA_VCC1 CP_VCC PA_VCC2 DVDD C11 10 /C0109F C10 0.1 /C0109F VCC Component Selection for Band of Operation Component Value Component Value Component Value Component Value C1 390 pF C1 270 pF C1 43 pF C1 43 pF C3 5.1 pF C3 4.7 pF C3 1.5 pF C3 1.5 pF TX PA Matching C4 390 pF C4 270 pF C4 39 pF C4 33 pF Matching Network C5 390 pF C5 270 pF C5 39 pF C5 33 pFNetwork L1 560 nH L1 470 nH L1 330 nH L1 270 nH L2 75 nH L2 43 nH L2 18 nH L2 15 nH C12 5600 pF C12 5600 pF C12 5600 pF C12 5600 pF PLL Loop C13 120 pF C13 120 pF C13 120 pF C13 120 pF PLL Loop Filter C15 75 pF C15 75 pF C15 75 pF C15 75 pFFilter R2 15 kΩ R2 15 kΩ R2 15 kΩ R2 15 kΩ R3 7.5 kΩ R3 7.5 kΩ R3 7.5 kΩ R3 7.5 kΩ Figure 8. Typical TRF4903 OOK Application Schematic

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TRF4903PW ACTIVE TSSOP PW 24 60 TBD Call TI Call TI TRF4903PWR ACTIVE TSSOP PW 24 2000 TBD Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 Addendum-Page 1

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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